Abstract: A current controlled sense current source having a current source with a stable reference current output is provided with a sense current source having a sense current reference input connected to the stable reference current output with the sense current source having a sense current output. A current controlled word current source comprising a current source having a stable reference current output is also provided with a word current source having a word current reference input connected to the stable reference current output with the word current source having a word current output.

Abstract: A magnetoresistive random access memory is provided. The magnetoresistive random access memory includes a first magnetic layer of which the direction of a magnetic vector is fixed, a second magnetic layer which is positioned in parallel with the first magnetic layer and of which the direction of a magnetic vector is reversible, and a non-magnetic layer interposed between the first and second magnetic layers, the second magnetic layer having an aspect ratio of 2 or less, a thickness of 5 nm or less, and a saturation magnetization of 800 emu/cm3 or less. The magnetoresistive random access memory has kink-free, magneto-resistance characteristics, thereby exhibiting high selectivity regardless of process capability.

Abstract: A sense amplifying magnetic tunnel (SAMT) device is disclosed. In a particular embodiment, a field effect transistor (FET) having a drain, a source, a channel therebetween, a gate electrode and a tunneling gate oxide proximate to the channel is provided. In addition, a spin valve memory (SVM) cell is provided electrically coupled to the gate electrode. The electrical coupling between the SVM cell and the gate electrode serves to provide a control potential to the gate. In addition, the coupling provides a gain to a current passed through the SAMT device.

Abstract: A method is described for generating a reference current for sense amplifiers connected to cells of a memory matrix comprising the steps of generating a first reference current analog signal through a reference cell, performing an analog-to-digital conversion of the first analog signal into a reference current digital signal, sending the digital signal on a connection line to the sense amplifiers, and performing a digital-to-analog conversion of the digital signal into a second reference current analog signal to be applied as reference current to the sense amplifiers.

Abstract: A system and method for determining the logic state of a memory cell in a magnetic tunnel junction (MTJ) memory device based on the ratio of the current through the cell at different bias points are disclosed. A memory cell in an MJT memory device is sequentially subjected to at least two different bias voltages. The current through the cell at each of the bias voltages is measured, and a ratio of the different currents is determined. The ratio is then compared with a predetermined value to determine the logic state of the cell. The predetermined value can be a known value. Alternatively, the predetermined value can be determined by application of the system and method to a reference cell having a known logic state.

Abstract: Embodiments of the present invention provide a magnetic memory. In one embodiment, the magnetic memory comprises an array of memory cells configured to provide resistive states, and a read circuit. The read circuit is configured to sense a resistance through a memory cell in the array of memory cells to obtain a sense result and categorize the sense result into one of at least three different categories comprising a middle category situated between the resistive states.

Abstract: A semiconductor memory device includes word lines, bit lines, first memory cells, second memory cells, a memory cell array, a row decoder, a row driver, a column decoder, a column driver, and a sense amplifier. The first memory cell includes a magneto-resistive element which has either a first resistance or a second resistance smaller than the first resistance. The second memory cell includes a magneto-resistive element which has a resistance between the first and second resistances. The memory cell array includes the first and second memory cells disposed in intersections of the word line and bit line. The row driver supplies a first write current to the word line. The column driver supplies a second write current to the bit line. The sense amplifier amplifies data read from the first memory cell.

Abstract: A switch section for changing the function of an FPGA is provided with a data latch circuit used for connection control. The data latch circuit includes program sections in which program data is stored in advance, and latch unit. At the time of changing the function, control signals are selectively inputted, whereby latch unit and program section are electrically coupled to each other, and a data signal stored in program section is outputted from the data latch circuit. With this arrangement, it is possible to easily change the function of an FPGA without rewriting program data.

Abstract: A magnetic memory having a calibration system is disclosed. One embodiment of the magnetic memory includes a sense amplifier and a calibration system configured to monitor at least one operating parameter of the magnetic memory and calibrate the sense amplifier if a measured parameter corresponding to the at least one operating parameter is within a range.

Abstract: A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.

Abstract: An apparatus and method is disclosed for reducing power consumption when sensing a resistive memory. A switch, with one end coupled to a terminal of a capacitive element at a node, is coupled from the other end to a bit line from a resistive memory array. A sensing device is further connected to the node, wherein the switch closes and opens to sample and store voltage signals transmitted on the bit line in the capacitive element. The sampled signal is then transmitted to a sensing apparatus that performs sensing operations on the signal.

Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.

Abstract: A memory device, which includes a matrix of memory cells, and an arrangement of write lines electrically isolated from the memory cells. The write lines may be configured to write data to the memory cells, each write line of the arrangement being electrically coupled to a reverse current limiting device.

Abstract: A magnetic memory includes a magnetic substance composed of a disc-shaped first magnetic layer and a ring-shaped second magnetic layer which is formed on the first magnetic layer.

Abstract: This invention provides a method of making nano-scaled toroidal magnetic memory cells, such as may be used, for example, in magnetic random access memory (MRAM). In a particular embodiment a semiconductor wafer substrate is prepared and a conductor layer is provided upon the wafer. A hard layer is deposited upon the first conductor. From the hard layer, ion etching is employed to form an annular wall about a pillar, the wall and pillar defining an annular slot. A ferromagnetic data layer is deposited within the annular slot and a junction stack is then provided upon at least a portion of the data layer. A dielectric is applied to insulate the structure and then planarized to expose the pillar.

Abstract: A method and system for providing magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory elements and providing at least one wrapped write line. Each wrapped write line includes a bottom write line and a top write line electrically connected to the bottom write line. The bottom write line resides below a portion of the plurality of magnetic elements, while the top write resides above the portion of the plurality of magnetic elements. The bottom write line carries a first current in a first direction, while the top write line carries a second current in a second direction opposite to the first direction.

Abstract: Apparatus and methods sense or measure an input current, such as a current indicating a logic state of a memory cell. A sensing circuit includes an amplifier, a capacitor, a current source circuit, a clocked comparator and a clocked counter. The current source circuit operates responsive to an output of the comparator to supply or withdraw current to and from the capacitor during respective charging and discharging intervals. The count in the clocked counter results from periodic comparisons of the capacitor voltage with a reference voltage and is, therefore, related to the logic state of the memory cell. The magnitude of current supplied during charging is less than the magnitude withdrawn during discharging, allowing use of a smaller counter.

Abstract: A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.

Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.

Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.

Abstract: Data sensing circuits for a magnetic memory cell include a current source circuit that selectively supplies a current to the magnetic memory cell. A first storage device selectively coupled to the magnetic memory cell stores a voltage representing a state of the magnetic memory cell. A second storage device selectively coupled to the magnetic memory cell stores a voltage representing a state of the magnetic memory cell. A differential voltage sense circuit coupled to the first and second storage device that is configured to generate a sensed data output signal for the magnetic memory cell responsive to sensing a difference between voltages stored in the first and second storage devices. A control circuit generates control signals to control the current source to supply current to the magnetic memory cell and to control the coupling of the first and second storage devices to the magnetic memory cell. Magnetic memories and methods are also provided.

Abstract: An integrated charge sensing scheme for sensing the resistance of a resistive memory element is described. The current through a resistive memory cell is used to charge a capacitor coupled to a digit line. The voltage on the capacitor, which corresponds to the voltage on the digit line, is applied to one input of a comparator. When the voltage on the bit line exceeds a predetermined fixed voltage applied to the second input to the comparator less an offset, the comparator switches logic state, charge is drawn off from the capacitor and the capacitor charges again. The process of charging and discharging the capacitor occurs during a predetermined time period and the number of times the capacitor switches during the time period represents the resistance of the memory element.

Abstract: In a normal data reading, one of word lines and one of first and second dummy word lines are selected and data is read out through the access to selected regular memory cell and a reference cell. In a test mode, each of word lines are turned to a non-select state and both of first and second dummy word lines are selected and by setting one of first and second reference voltages to a level different from a level during the normal data reading, data is read out through the access to the reference cells.

Abstract: Capacitors are provided for changing the voltage level of data lines, respectively, in a data reading operation. A signal line electrically coupled to capacitors is provided. Capacitors charge data lines in accordance with the voltage level of signal line by capacitive coupling. Thus, data lines can be charged quickly to achieve a fast data reading operation.

Abstract: This invention provides a probe based magnetic memory storage device. In a particular embodiment, magnetic memory cells are provided in an array. Each cell provides a magnetic data layer and a conductor. At least one movable probe having a tip characterized by a conductor and a soft reference layer is also provided. In addition, an intermediate layer joined to either the movable probe or each memory cell is provided. The movable probe may be placed in contact with a given memory cell, the probe and cell thereby forming a tunnel junction memory cell with the intermediate layer serving as the tunnel junction. The magnetic field provided by the probe conductor may be combined with a field provided by the cell conductor to produce a switching field to alter the orientation of the data layer. The memory cells may include a material wherein the coercivity is decreased upon an increase in temperature. The probe may also include a heat generator.

Abstract: The invention includes an apparatus and a method for minimizing power supply sensitivity of a differential amplifier. The apparatus includes a current source providing a differential amplifier bias current to a common source node of the differential amplifier. A voltage sensor senses variations of a power supply associated with the current source. Variations sensed by the voltage sensor control a magnitude of the differential amplifier bias current. The method includes a current source providing the source current. A voltage potential of the common source node is sensed. The current source is adjusted depending upon the sensed voltage potential of the common source node, thereby adjusting a magnitude of the source current.

Abstract: An intergrated charge sensing scheme for sensing the resistance of a resistive memory element is described. The current through a resistive memory cell is used to charge a capacitor coupled to a digit line. The voltage on the capacitor, which corresponds to the voltage on the digit line, is applied to one input of a comparator. When the voltage on the bit line exceeds a predetermined fixed voltage applied to the second input to the comparator less an offset, the comparator switches logic state, charge is drawn off from the capacitor and the capacitor charges again. The process of charging and discharging the capacitor occurs during a predetermined time period and the number of times the capacitor switches during the time period represents the resistance of the memory element.

Abstract: A nonvolatile ferroelectric memory device having a multi-bit control function can store and sense multi-bit data in a ferroelectric memory cell. In the memory device, a plurality of cell array blocks generates a plurality of different sensing critical voltages in a reference timing strobe interval. As a result, in different time intervals, the plurality of sensing critical voltages are compared with a plurality of cell data sensing voltages applied from a main bitline. A data register array unit stores a plurality of cell data applied from the plurality of cell array blocks in response to a plurality of read lock signals activated at different timings in different time intervals, respectively. Therefore, the plurality of data bits can be stored in a cell.

Abstract: The present invention relates to a simplified reference current generator for a magnetic random access memory. The reference current generator is positioned in the vicinity of the memory cells of the magnetic random access memory, and applies reference elements which are the same as the magnetic tunnel junctions of the memory cell and bear the same cross voltages. The plurality of reference elements are used for forming the reference current generator by one or several bit lines, and the voltage which is the same as the voltage of the memory cell is crossly connected to the reference elements so as to generate a plurality of current signals; and a peripheral IC circuit is used for generating the plurality of midpoint reference current signals and judging the data states. Thanks to the midpoint current reference signals, the multiple-states memory cell, including the 2-states memory cell, can read data more accurately.

Abstract: In read operation, a current from a current supply transistor flows through a selected memory cell and a data line. Moreover, a bias magnetic field having such a level that does not destroy storage data is applied to the selected memory cell. By application of the bias magnetic field, an electric resistance of the selected memory cell changes in the positive or negative direction depending on the storage data level. A sense amplifier amplifies the difference between voltages on the data line before and after the change in electric resistance of the selected memory cell. Data is thus read from the selected memory cell by merely accessing the selected memory cell. Moreover, since the data line and the sense amplifier are insulated from each other by a capacitor, the sense amplifier can be operated in an optimal input voltage range regardless of magnetization characteristics of the memory cells.

Abstract: A dummy cell (reference electric potential generating circuit) DC has a paraelectric capacitor DCC1 and a ferro-electric capacitor DCC2. One end of the paraelectric capacitor DCC1 and one end of the ferro-electric capacitor DCC2 are commonly connected to a node N1. A dummy plate electric potential DPL1 is supplied to the other end of the paraelectric capacitor DCC1, and a dummy plate electric potential DPL2 is supplied to the other end of the ferro-electric capacitor DCC2. When data of a memory cell MC is read at a bit line (selective bit line) BL1, a reference electric potential is supplied to a bit line (reference bit line) BL2 from the dummy cell DC.

Abstract: A nonvolatile ferroelectric memory device having a multi-bit control function performs read/write operations by selecting a plurality of cells simultaneously, thereby improving the operation speed of a chip. In the nonvolatile ferroelectric memory device, a plurality of cells are selected at the same time, and stable sensing values of data having a small distribution can be obtained by using average characteristics of a plurality of selected cells. Accordingly, since two or more cells are simultaneously selected and a plurality of bits are read/written in the cells depending on stabilized charge, the operation speed of a chip can be improved.

Abstract: A magnetic memory which detects changes between resistive states of a memory cell is disclosed. In one embodiment the magnetic memory includes a memory cell which has first and second resistive states. First and second write conductors are configured to conduct first and second currents to change the memory cell between the first and the second resistive states. The first and the second write conductors are routed in first and second directions and intersect the memory cell. First and second sense conductors are configured to conduct a sense current through the memory cell. A sense circuit coupled to the second sense conductor is configured to detect the change between the first and the second resistive states.

Abstract: In one data read operation, data read for reading stored data before and after a predetermined data write magnetic field is applied to a selected memory cell, respectively, is executed, and the data read is executed in accordance with comparison of voltage levels corresponding to the data read operations before and after application of the predetermined data write magnetic field. In addition, data read operations before and after the application of a data write magnetic field are executed using read modify write. It is thereby possible to avoid an influence of an offset or the like resulting from manufacturing irregularities in respective circuits forming a data read path, to improve efficiency of the data read operation with accuracy and to execute a high rate data read operation.

Abstract: A four-conductor MRAM device comprising an array of memory cells, each of the memory cells including a first magnetic layer, a dielectric, and a second magnetic layer; a plurality of local column sense lines wherein one is electrically connected to the first magnetic layer of the array of memory cells; a plurality of local row sense lines wherein one of the local row sense lines is electrically connected to the second magnetic layer of the array of memory cells; a plurality of global column write lines parallel to the plurality of local column sense lines; a plurality of global row write lines parallel to the plurality of local row sense lines; and wherein the plurality of local column sense lines and the plurality of local row sense lines are connected to read data from the array of memory cells and the plurality of global column write lines and the plurality of global row write lines are connected to write data to the array of memory cells.

Abstract: Systems and methods for reading from or writing to memory blocks, are provided. An embodiment of the system comprises a plurality of memory blocks; a plurality of repeaters; and a line that couples the memory blocks with the repeaters such that the repeaters can read from the memory blocks. One embodiment of the method comprises coupling the memory blocks to repeaters; and reading from the memory blocks.

Abstract: A magnetic random access memory (MRAM) using a common line is described herein. An MTJ element is positioned on the common line of the MRAM. The common line connected to a source of a transistor transmits a ground level voltage for reading data and supplies a current for writing data.

Abstract: An information storage device is disclosed. In one embodiment, the information storage device includes first and second memory cells which store complementary first and second logic states. An error detection system coupled to the first and second memory cells is configured to indicate an error if a difference between a first current flowing through the first memory cell and a second current flowing through the second memory cell is less than a predefined value.

Abstract: A semiconductor memory device as claimed in the present invention has a reference cell, a first memory cell, a second memory cell located nearer the first memory cell than the reference cell and a data read circuit provided therein. The data read circuit identifies first data stored in the first memory cell based on a reference cell electrical state of the reference cell and a first electrical state of the first memory cell. Furthermore, the data read circuit identifies second data stored in the second memory cell based on the first electrical state of the first memory cell and a second electrical state of the second memory cell. The semiconductor memory device having such configuration is able to suppress influence of variation in electrical performance of memory cell and stably identify data stored in a memory cell.

Abstract: A semiconductor memory device includes a plurality of memory cells each capable of storing and programming N-level data; a reference cell storing a reference level used when reading a data level stored in the memory cells; a counter circuit counting number of times of reading of the reference cell; a check means for determining whether the reference level stored in the reference cell is within a preset range when the number of times of reading that is counted reaches a specified value; and a correction means for, if the check means determines that the reference level is out of the range, correcting the reference level to fall within the range in accordance with a master reference cell. With this constitution, it is possible to provide the semiconductor memory device capable of efficiently correcting the state of the reference cell, preventing the deterioration of the reference cell due to disturbance or the like, and highly accurately maintaining the level of the reference cell.

Abstract: An integrated charge sensing scheme for sensing the resistance of a resistive memory element is described. The current through a resistive memory cell is used to charge a capacitor coupled to a digit line. The voltage on the capacitor, which corresponds to the voltage on the digit line, is applied to one input of a comparator. When the voltage on the bit line exceeds a predetermined fixed voltage applied to the second input to the comparator less an offset, the comparator switches logic state, charge is drawn off from the capacitor and the capacitor charges again. The process of charging and discharging the capacitor occurs during a predetermined time period and the number of times the capacitor switches during the time period represents the resistance of the memory element.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: The invention includes an adjustable offset differential amplifier. The adjustable offset differential amplifier includes a first differential transistor receiving a first differential input, and a second differential transistor receiving a second differential input. A differential amplifier output includes an amplitude proportional to a difference between the first differential input and the second differential input. The first differential transistor includes a plurality of sub first differential transistors. Each sub first differential transistor includes an adjustable back gate bias. Control circuitry can be connected to the adjustable back gate bias of each of the sub first differential transistors for reducing offset errors of the differential amplifier output.

Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.

Abstract: Apparatus and methods sense or measure an input current, such as a current indicating a logic state of a memory cell. A sensing circuit includes an amplifier, a capacitor, a current source circuit, a clocked comparator and a clocked counter. The current source circuit operates responsive to an output of the comparator to supply or withdraw current to and from the capacitor during respective charging and discharging intervals. The count in the clocked counter results from periodic comparisons of the capacitor voltage with a reference voltage and is, therefore, related to the logic state of the memory cell. The magnitude of current supplied during charging is less than the magnitude withdrawn during discharging, allowing use of a smaller counter.

Abstract: Two complementary bit lines corresponding to a selected column are pulled down to a ground voltage via each of a selected MTJ memory cell and a dummy memory cell and are pulled up to a power supply voltage via a read drive selection gate. A read gate corresponding to the selected column drives the voltages of two complementary read data buses by driving force according to the voltage of corresponding complementary two bit lines, respectively. A data reading circuit executes data reading operation on the basis of a voltage difference between the complementary two read data buses. The power supply voltage is determined in consideration of reliability of a tunneling insulating film of an MTJ memory cell.

Abstract: The present invention relates to a simplified reference current generator for a magnetic random access memory. The reference current generator is positioned in the vicinity of the memory cells of the magnetic random access memory, and applies reference elements which are the same as the magnetic tunnel junctions of the memory cell and bear the same cross voltages. The plurality of reference elements are used for forming the reference current generator by using one or several bit lines, and the voltage which is the same as the voltage of the memory cell is crossly connected to the reference elements so as to generate a plurality of current signals; and a peripheral IC circuit is used for generating the plurality of midpoint reference current signals and judging the data states. Thanks to the midpoint reference current signals, the multiple-states memory cell, including the 2-states memory cell, can read data more accurately.

Abstract: A method for sensing the resistance value of a resistor-based memory cell. A current is driven through all unused row lines of a memory array while grounding the row line associated with the selected cell, thereby forcing the current through a comparatively low equivalent resistance formed by the parallel coupling of all unselected memory cells and also through a comparatively high resistance of the selected memory cell. The voltage on a column line corresponding to the selected memory cell is then measured to ground. The voltage level corresponds to either one of two resistance values (i.e., signifying either a logic “HIGH” or a logic “LOW”).

Abstract: In a memory cell array of an MRAM, a reference memory cell holding a reference value can generate accurate reference current of an intermediate value of data by uniformly supplying reference current to two sense amplifiers using two cells of a cell holding “H” data and a cell holding “L” data. Each bit line is connected to a data-storing memory cell and to the reference memory cell. When the data-storing memory cell connected to a bit line is accessed, the reference memory cell is accessed on the adjacent bit line. Only one row of reference memory cells is provided, reducing the chip area. Therefore, a non-volatile memory device that can reduce the area of a reference cell occupied on a chip while generating accurate reference current for determination can be provided.

Abstract: A memory cell sensor including an integrator for sensing a logical state of a memory cell. An integrator calibration circuit provides a corrective bias to the integrator, the corrective bias being based upon a difference between an initial integrator output value and a reference value. Another embodiment includes a method of sensing a logical state of a memory cell. The memory cell being sensed by an integrator. The method includes determining an initial integrator output value when a corrective bias of the integrator is zeroed, generating a correction value by comparing the initial integrator output value to a reference value, and applying the correction value to the corrective bias of the integrator.