Erase Patents (Class 365/218)
  • Patent number: 10929308
    Abstract: There is provided an apparatus that includes an input port to receive, from a requester, any one of: a lookup operation comprising an input address, and a maintenance operation. Maintenance queue circuitry stores a maintenance queue of at least one maintenance operation and address storage stores a translation between the input address and an output address in an output address space. In response to receiving the input address, the output address is provided in dependence on the maintenance queue. In response to storing the maintenance operation, the maintenance queue circuitry causes an acknowledgement to be sent to the requester. By providing a separate maintenance queue for performing the maintenance operation, there is no need for a requester to be blocked while maintenance is performed.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: February 23, 2021
    Assignee: Arm Limited
    Inventors: Andreas Lars Sandberg, Nikos Nikoleris, Prakash S. Ramrakhyani, Stephan Diestelhorst
  • Patent number: 10922000
    Abstract: A controller, an operating method thereof and a memory system including the same are disclosed. The operating method of a controller which controls a memory system including a nonvolatile memory device including a plurality of data storage regions, includes receiving a command from a host, determining whether a pre-condition command is included in the command by confirming whether the received command has a reserved area, and switching the memory system to a pre-condition state by performing a secure erase and patterning on the nonvolatile memory device according to the pre-condition command included in the command.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Do Hyun Kim
  • Patent number: 10901651
    Abstract: Embodiments of memory block erasure are described herein. An aspect includes determining an initial word line set consisting of a single word line. Another aspect includes activating the single word line such that a first memory cell that is connected to the single word line is erased by the activation. Another aspect includes determining a first word line set consisting of the single word line and one additional word line, and wherein the one additional word line corresponds to a second memory cell have a maximum distance from the first memory cell along a bit line that includes the first memory cell and the second memory cell. Another aspect includes activating the first word line set, such that a respective memory cell that is connected to each of the first word line set is erased by the activation.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin B. Schmidt, Peter Altevogt, Wolfgang Gellerich, Juergen Pille
  • Patent number: 10902922
    Abstract: A nonvolatile memory includes a first sub-block defined by a first string select line and a first word line; a second sub-block defined by a second string select line different from the first string select line and a second word line different from the first word line; a first vacant block defined by the first string select line and the second word line; and a second vacant block defined by the second string select line and the first word line. First data is programmed in the first sub-block with, second data is programmed in the second sub-block, and no data is programmed in the first vacant block and the second vacant block.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: January 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Seo, Kui Han Ko, Jin-Young Kim, Il Han Park, Bong Soon Lim
  • Patent number: 10878875
    Abstract: A computer-implemented method for writing to a printed memory device is disclosed. The computer-implemented method includes determining, by a microcontroller, a first encoding scheme from among a plurality of encoding schemes to write a first data portion from among a plurality of data portions, wherein the first encoding scheme comprises a first voltage and a first pulse width to be used to write the first data portion; providing, by the microcontroller, the first encoding scheme to an application-specific integrated circuit (ASIC); selecting, by the ASIC, a first target memory cell of the printed memory device corresponding to a first word line and a first bit line for the first data portion to be written; and writing, by the ASIC, the first data portion to the first target memory cell using the first encoding scheme.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: December 29, 2020
    Assignee: XEROX CORPORATION
    Inventors: Christopher P. Caporale, Alberto Rodriguez, Markus R. Silvestri, Terry L. Street, Ron Edward Dufort
  • Patent number: 10878927
    Abstract: A control circuit controls a column decoder and a row decoder to perform reprogramming where, before the count of reprogramming operations involving erasures, each targeting one of a plurality of memory cells included in a memory cell array, reaches a predetermined number, a first extent (e.g. a sub-block) including the targeted memory cell and being smaller than the entire extent of the memory cell array is used as the unit of reprogramming, and when the count of reprogramming operations reaches the predetermined number, a second extent (e.g. the memory cell array corresponding to one sector) including the targeted memory cell and being larger than the first extent is used as the unit of reprogramming, and resets the count of reprogramming operations each time it reaches the predetermined number.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: December 29, 2020
    Assignee: UNITED SEMICONDUCTOR JAPAN CO., LTD.
    Inventors: Taiji Ema, Makoto Yasuda
  • Patent number: 10878916
    Abstract: An erasing method adapted for a semiconductor memory device is provided. The erasing method includes executing a pre-program process on the semiconductor memory device, executing an erase process on the semiconductor memory device, executing an over-erase verification process on a plurality of memory cells of the semiconductor memory device, detecting a total current consumption of the plurality of memory cells, determining the number of the memory cells to be executed with a soft program process according to the total current consumption, and executing the soft program process on the memory cells based on the number of the memory cells.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: December 29, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Yu-Kai Liao, Chiang-Hung Chen, Wen Hung
  • Patent number: 10777239
    Abstract: A semiconductor storage device includes a sense amplifier configured to read and program data in memory cells, a first latch circuit to store read data or program data, a second latch circuit to store the first data transferred from the first latch circuit or the second data before the second data is transferred into the first latch circuit, an input/output circuit to output the first data stored in the second latch circuit and to transfer the second data received thereby to the second latch circuit, and a control circuit. Upon receiving a read command while the control circuit is performing a program operation on program data stored in second latch circuit, the control circuit interrupts the program operation to perform the read operation and resumes the program operation on the program data in response to a resume write command sequence that does not include the program data.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Junichi Sato, Akio Sugahara
  • Patent number: 10747909
    Abstract: A method and architecture for mitigating memory imprinting in electronic system volatile memory. At system power-up, a bus mode register control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal amounts of time in each mode over the system's lifecycle. A bi-directional data bus inverter is positioned between a system processor and volatile memory. When the system is running in inversion mode, data from non-volatile memory is inverted (0's and 1's are swapped) when copied to volatile memory, and the data bus inverter rectifies all data bits flowing in/out of the processor. By balancing the time spent by individual memory addresses in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as internal processor cache memory, and FPGA configuration memory, is also disclosed.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: August 18, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Kenneth R. Weidele, Kenneth F. McKinney, Christopher H. Meawad, Tim Manestitaya, Allan T. Hilchie, Timothy D. Schaffner
  • Patent number: 10658025
    Abstract: Apparatuses and methods for executing row hammer (RH) refresh are described. An example apparatus includes a RH control circuit to provide a row hammer address, and a refresh control circuit to perform a RH refresh operation on a memory address array related to the RH address. The RH control circuit includes first latches each to store an old row address used to access the memory and second latches provided correspondingly to the first latches each set to a state indicating whether the old row address stored in one of the first latches is valid. The RH control circuit further including a signal generator configured to assert a sample signal when a new row address to be used to access the memory array matches the old row address stored in any one of the first latches is valid based on a state of one of the second latches.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Yutaka Ito
  • Patent number: 10644873
    Abstract: A method for executing an operation by a circuit, may include using a first mask set of mask parameters including a same number of occurrences of all possible values of a word of an input data in relation to a size thereof, using an input set including for each mask parameter in the first mask set a data obtained by applying XOR operations to the input data and to the mask parameter and providing an output set including all data resulting from the application of the operation to a data in the input set. The output data may be obtained by applying XOR operations to any of the data in the output set and to a respective second mask parameter in a second mask set including a same number of occurrences of all possible values of the second mask parameters in relation to a size of thereof.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: May 5, 2020
    Assignee: ESHARD
    Inventors: Antoine Wurcker, Christophe Clavier
  • Patent number: 10565049
    Abstract: A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: February 18, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Brent Haukness
  • Patent number: 10564892
    Abstract: A storage device including a volatile memory, a non-volatile memory and a controller is provided. The controller sends a plurality of commands to the non-volatile memory. When the controller receives a reset signal, the controller determines whether a specific operation has been completed. When the controller has not yet finished the specific operation, the controller continuously provides the commands to the non-volatile memory. When the controller has finished the specific operation, the controller performs a reset operation according to the reset signal.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: February 18, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Chang-Wei Shen
  • Patent number: 10521133
    Abstract: A device for reading data from a first memory to a second memory based on real-time blank page detection includes a memory controller for reading a page of data from the first memory, a buffer for buffering a portion of the page data, a blank page pre-detection unit for generating a pre-detection result that indicates whether the page is a blank page based on a pre-determined part of the page data, a data processing unit for processing all of the page data to identify a page type, and a control unit for signaling the memory controller to read the page of data from the first memory and enabling the data processing unit based on the pre-detection result.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: December 31, 2019
    Assignee: NXP USA, INC.
    Inventors: Yong Wang, Chongbin Fan, Jun Xie
  • Patent number: 10366739
    Abstract: A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. A voltage supply circuit may supply a selected pulse and an unselected pulse to the selected and unselected sense circuits. The selected sense circuits may pass the selected pulse to associated charge-storing circuits, and reject the unselected pulse. The unselected sense circuits may pass the unselected pulse to associated charge-storing circuits, and reject the selected pulse. In addition, voltage-setting circuitry may set sense voltages in the unselected sense circuits to a pre-sense level that matches the pre-sense level of communication voltages in the unselected sense circuits.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 30, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Anirudh Amarnath, Tai-Yuan Tseng
  • Patent number: 10249382
    Abstract: Techniques are described for determining whether a non-volatile memory device is defective due to a word line that programs too fast, leading to an uncorrectable amount of data errors when programing data to the word line. In one set of examples, a set of memory cells are programmed by a series of voltage pulses applied along a word line without locking out the set of memory cells. A verify operation is then performed to see if the number of memory cells programmed above the verify level is too large and, if so, an error status is returned. In other examples, a lower limit on the number of voltage pulses needed to complete programming is introduced, and if the programming completes in less than this number of voltage pulses, an error status returned. A lower limit on the number of voltage pulses can be on a state by state basis or for all data states to complete.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: April 2, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Dana Lee, Ekam Singh, Ashish Ghai, Kalpana Vakati
  • Patent number: 10108561
    Abstract: A data storage device includes a nonvolatile memory device; a power management unit suitable for outputting first and second low voltage detection signals, each low voltage detection signal representing a voltage level of a source voltage equal to or lower than a predetermined reference voltage level; and a processor suitable for computing a detection interval between the first low voltage detection signal and the second low voltage detection signal before the first low voltage detection signal, comparing the computed detection interval and a predetermined threshold detection interval, and determining a subject to manage performing of a recovery operation according to low voltage generation based on a comparison result.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: October 23, 2018
    Assignee: SK Hynix Inc.
    Inventor: Jeen Park
  • Patent number: 10073877
    Abstract: One or more processors evaluate whether a subset of a dataset is sorted. One or more processors process the dataset if it is determined that the subset of the dataset is sorted.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventor: Ian S. Burnett
  • Patent number: 9858014
    Abstract: A method of operating a memory system includes managing program order information of the memory device based on program order stamps (POSs) indicating relative temporal relationships between program operations performed in relation to a plurality of memory groups included in the memory device, and controlling operations directed to the plurality of memory groups in response to the program order information.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyung-Ryun Kim
  • Patent number: 9836625
    Abstract: Techniques described herein generally relate to protecting information stored in a mobile communication device. In one embodiment, a mobile communication device may include a data security module, a control circuitry, a first memory unit configured to store a first information, a first battery unit configured to supply power to the mobile communication device, and a second battery unit configured to supply power to the data security module and the control circuitry in response to a trigger event. The data security module is further configured to activate the control circuitry to perform a particular action on the first information, such as at least a partial erasure of the first information.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 5, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Oscar Khesin
  • Patent number: 9798614
    Abstract: An operating method of a controller includes generating error reliability of data based on reliability information of one or more error-corrected bits of the data, wherein the data is read out from a semiconductor memory device and a hard decision ECC decoding to the data through a BCH code is determined as successful; and determining miscorrection of the data based on the error reliability.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: October 24, 2017
    Assignee: SK Hynix Inc.
    Inventor: Do-Hun Kim
  • Patent number: 9665295
    Abstract: Systems, methods and/or devices are used to enable dynamic erase block grouping. In one aspect, the method includes (1) maintaining metadata for each erase block of a plurality of erase blocks in a data storage system, wherein a respective metadata for a respective erase block includes one or more characteristics of the respective erase block, (2) allocating a set of erase blocks, of the plurality of erase blocks, as unassociated erase blocks, (3) selecting two or more unassociated erase blocks in accordance with characteristics of the unassociated erase blocks so as to select unassociated erase blocks with similar characteristics, and (4) grouping the two or more unassociated erase blocks with similar characteristics to form a super block.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: May 30, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Fitzpatrick, Mark Dancho, James M. Higgins, Robert W. Ellis, Bernardo Rub
  • Patent number: 9502650
    Abstract: Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: November 22, 2016
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Andrea Redaelli, Agostino Pirovano
  • Patent number: 9444048
    Abstract: A method of forming a circuitry includes providing a substrate comprising a plurality of die. Each die includes a plurality of resistive random access memory (RRAM) storage cells. The method further includes concurrently initializing substantially all of the RRAM storage cells on the same wafer. Initializing can include applying a voltage potential across the RRAM storage cells.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: September 13, 2016
    Assignee: Freescale Semiconductor, Inc
    Inventors: Peter J. Kuhn, Feng Zhou
  • Patent number: 9431109
    Abstract: Various aspects provide for a new combination of non-volatile memory architecture and memory processing technology. A memory cell has a gate node, a source node and a drain node. The gate node is connected to a wordline of the memory, the source node is connected to a local source line of the memory, and the drain node is connected to a local data line of the memory. A channel-based processing component programs the memory cell and inhibits programming of a second memory cell on the wordline of the memory. The channel-based processing component also grounds the local source line and the local data line in conjunction with programming the memory cell, and floats a second local source line and a second local data line connected to the second memory cell in conjunction with inhibiting programming of the second memory cell.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: August 30, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Hagop Nazarian, Richard Fastow
  • Patent number: 9430373
    Abstract: Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can include a channel control circuit coupled to logical units. The channel control circuitry can be configured to relay an erase command to a first one of the logical units and relay a particular command from the switch to a second one of the logical units while the erase command is being executed on the first one of the plurality of logical units.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: August 30, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Douglas A. Larson, Jeffrey R. Brown
  • Patent number: 9361988
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: June 7, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
  • Patent number: 9337875
    Abstract: A system that incorporates teachings of the subject disclosure may include, for example, emulating a behavior of an RF capacitive device utilizing a mirror circuit; and providing feedback signals to an input of an operational amplifier via a feedback node coupled with the mirror circuit. Other embodiments are disclosed.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: May 10, 2016
    Assignee: BLACKBERRY LIMITED
    Inventors: Matthew Russell Greene, James Oakes, Guillaume Blin
  • Patent number: 9299391
    Abstract: A three dimensional (3D) circuit includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be adjacent memory cells or bit cells coupled to different bit lines.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: March 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hao-I Yang, Yi-Tzu Chen, Cheng-Jen Chang, Geng-Cing Lin, Yu-Hao Hu
  • Patent number: 9245635
    Abstract: A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: January 26, 2016
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Katsuaki Matsui
  • Patent number: 9093161
    Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 28, 2015
    Assignee: Sillicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • Patent number: 9065044
    Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: June 23, 2015
    Assignee: SanDisk 3D LLC
    Inventor: Roy E. Scheuerlein
  • Patent number: 9043661
    Abstract: Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of such memory devices includes determining that a single cell is unprogrammable and repairing the single cell, and repairing a column containing the single cell responsive to a subsequent erase operation.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Nicholas Hendrickson
  • Patent number: 9042193
    Abstract: A sense amplifier circuit comprising a pair of cross-coupled inverters and a data line charging circuit is disclosed. The cross-coupled inverters comprise a first inverter and a second inverter. The first inverter has a first pull-up transistor with a first pull-up terminal. The second inverter has a second pull-up transistor with a second pull-up terminal. The output of the first inverter is coupled to the input of the second inverter at a first sense amp node. The output of the second inverter is coupled to the input of the first inverter at a second sense amp node. The data line charging circuit has a first node connected to a data line and the first pull-up terminal. The data line charging circuit also has a second node connected to a complementary data line and the second pull-up terminal. The first and second pull-up transistors are coupled to different voltage levels when a sense amplifier enable signal is activated.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Yuan Chen, Hau-Tai Shieh
  • Patent number: 9030885
    Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: May 12, 2015
    Assignee: Intel Corporation
    Inventors: Yogesh B Wakchaure, Kiran Pangal, Xin Guo, Qingru Meng, Hanmant P Belgal
  • Publication number: 20150117129
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit suitable for generating program and erase voltages and applying the program and erase voltages to the plurality of memory cells when program and erase operations are performed on the plurality of memory cells, and a control logic suitable for controlling the peripheral circuit unit during the program and erase operations and counting a pulse number of the program and erase voltages to store a resultant count number as status data.
    Type: Application
    Filed: March 19, 2014
    Publication date: April 30, 2015
    Applicant: SK hynix Inc.
    Inventor: Sung Hyun JUNG
  • Patent number: 9007860
    Abstract: Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Chang Wan Ha
  • Publication number: 20150078111
    Abstract: A storage device issues parallel or concurrent write and erase commands, to write data in response to a request, and to erase blocks marked for deletion to free storage space for subsequent write requests. The storage device receives a write request from a disk controller to write data to a storage array. The storage device determines that one or more blocks are marked for deletion. In response to receiving the write request and determining that blocks are marked for deletion, the storage device issues a write command on a first media access channel for a first location of the storage array, and issues an erase command on a second media access channel for a different storage location of the storage array. Thus, the commands are issued concurrently on different channels.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 19, 2015
    Applicant: NetApp, Inc.
    Inventors: MAHMOUD K. JIBBE, Gary M. Gaston
  • Patent number: 8982642
    Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Won-Teack Jung, Junghoon Park
  • Patent number: 8976602
    Abstract: A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated.
    Type: Grant
    Filed: March 3, 2013
    Date of Patent: March 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidehiro Shiga, Masanobu Shirakawa
  • Patent number: 8958249
    Abstract: A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. The erase depth is made shallower as the device is cycled more.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: February 17, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Deepanshu Dutta, Chun-Hung Lai, Shih-Chung Lee, Ken Oowada, Masaaki Higashitani
  • Patent number: 8947933
    Abstract: According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality of bit lines. The row decoder applies a voltage to the first and second select transistors. The controller detects a defect of the bit lines based on data read from the memory cells.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoya Tokiwa, Yasushi Nagadomi
  • Patent number: 8929151
    Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: January 6, 2015
    Assignee: Intel Corporation
    Inventors: Yogesh Wakchaure, Kiran Pangal, Xin Guo, Qingru Meng, Hanmant P Belgal
  • Patent number: 8924633
    Abstract: The erasing of data stored in a nonvolatile memory is performed using multiple partial erase operations. Each partial erase operation has a time duration that is shorter than the minimum time duration of an erase operation that is needed to reliably erase the data stored in the storage location. However, the sum of the time durations of the multiple partial erase operations is sufficient to reliably erase the data in the storage location. In one example, during a partial erase operation, a voltage is applied to a memory storage transistor to remove some, but not necessarily all, of the charge stored on a charge storage layer of the transistor. Following multiple partial erase operations, sufficient charge is removed from the charge storage layer to ensure reliable data erasure.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 30, 2014
    Assignee: Dust Networks, Inc.
    Inventors: Gordon Alexander Charles, Maxim Moiseev, Jonathan Simon
  • Patent number: 8918584
    Abstract: A method and apparatus for refreshing data in a flash memory device is disclosed. A counter is maintained for each memory block. When a memory block is erased, the counter for that erase block is set to a predetermined value while the remaining counters for other erase blocks are changed. When a memory block counter reaches a predetermined threshold value, the associated memory block is refreshed.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: December 23, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Shuba Swaminathan
  • Publication number: 20140369139
    Abstract: The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array. Further, erase signal generation circuitry is configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses. The erase signal generation circuitry is further configured to issue said erase signal in said asserted state if the control signal does not take the form of said pulse signal.
    Type: Application
    Filed: July 16, 2013
    Publication date: December 18, 2014
    Inventors: Nicolaas Klarinus Johannes VAN WINKELHOFF, Ali ALAOUI, Pierre LEMARCHAND, Bastien Jean Claude AGHETTI
  • Patent number: 8908460
    Abstract: An elapsed time with respect to a programming operation on a memory cell of a nonvolatile memory is determined, a read voltage is adjusted based on the determined elapsed time and a read operation is performed on the memory cell using the adjusted read voltage. Determining the elapsed time may be preceded by performing the programming operation in response to a first access request and determining the elapsed time may include determining the elapsed time in response to a second access request. Memory systems supporting such operations are also described.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: December 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kui-Yon Mun, Min-Chul Kim, Sungwoo Kim
  • Patent number: 8902670
    Abstract: According to one embodiment, a semiconductor memory device includes memory cell arrays each including blocks. The block is unit of erase and includes string-groups. Each string-group includes strings each including a first transistor, memory cell transistors, a second transistor coupled in series. The first transistor is connected to different bit line and the second transistor is connected to same source line. The memory cell arrays are provided with different respective block address signals. The memory cell arrays are provided with different respective string address signals. Each of the block address signals specifies one block. Each of the string address signals specifies one string-group.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tokumasa Hara, Hiroshi Sukegawa, Toshio Fujisawa, Shirou Fujita, Masaki Unno, Masanobu Shirakawa
  • Patent number: 8897088
    Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines. An AND gate is coupled to the m bit lines and has an output line coupled to an input of a test controller on the SoC. An OR gate is coupled to the m bit lines and has an output line coupled to an input of the test controller.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 25, 2014
    Assignee: Texas Instrument Incorporated
    Inventors: Steven Craig Bartling, Sudhanshu Khanna
  • Patent number: 8885429
    Abstract: A memory device including an array of memory cells arranged as a plurality of rows and columns. Write circuitry then controls a voltage level of the associated at least one bit line for each of the addressed memory cells to cause write data to be written into the addressed memory cells. In the presence of an asserted erase signal, a decoder circuitry's operation is modified such that it issues, independently of the clock signal, an asserted word line signal on the word line associated with each row in a predetermined erase region of the array. Further, the write circuitry's operation is modified so that it controls the voltage level of the associated at least one bit line for each memory cell in the predetermined erase region, in order to cause erase write data to be written into the memory cells of the predetermined erase region.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: November 11, 2014
    Assignee: ARM Limited
    Inventors: Nicolaas Klarinus Johannes Van Winkelhoff, Pierre Lemarchand, Bastien Jean Claude Aghetti, Virgile Javerliac