Powering Patents (Class 365/226)
  • Patent number: 12020770
    Abstract: 1. The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: June 25, 2024
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventor: Syed M. Alam
  • Patent number: 12020769
    Abstract: The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: June 25, 2024
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventor: Syed M. Alam
  • Patent number: 11996729
    Abstract: The present technology includes a power supply and a method of operating the same. The power supply includes a main power supply configured to receive external power and output a charge voltage and main power, and an auxiliary power supply including a capacitor array configured to charge auxiliary power using the charge voltage and output the auxiliary power. The auxiliary power supply is configured to periodically repeat a discharge operation and a sub charge operation on the capacitor array when the charging of the capacitor array is started.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 28, 2024
    Assignee: SK hynix Inc.
    Inventors: Tae Hoon Kim, Jae Woong Jeong, Rak Hun Choi, Eun Kyu Choi, Tae Seung Han
  • Patent number: 11955196
    Abstract: A voltage generating device includes a clock signal generator, a voltage regulator and a pump circuit. The clock signal generator generates a clock signal according to an enable signal. The voltage regulator generates and adjusts a first voltage according to a reference voltage and the enable signal. The pump circuit receives the clock signal, the first voltage and a second voltage, wherein the pump circuit performs a voltage pump operation to generate an output voltage based on the clock signal according to the first voltage and the second voltage. The output voltage equals to a summation of the first voltage and the second voltage.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: April 9, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-Jen Chen
  • Patent number: 11942176
    Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: March 26, 2024
    Assignee: Kioxia Corporation
    Inventors: Tomoya Sanuki, Xu Li, Masayuki Miura, Takayuki Miyazaki, Toshio Fujisawa, Hiroto Nakai, Hideko Mukaida, Mie Matsuo
  • Patent number: 11936293
    Abstract: A regulated charge pump includes a comparator having a first input coupled to an output of the regulated charge pump, a second input configured for receiving a reference voltage, and an output for generating an output voltage representing a difference between a charging current of the regulated charge pump and a load current of a load coupled to the output of the regulated charge pump; a first converter having an input coupled to the output of the comparator, and an output connected to a control bus configured to indicate an adjustment of the charging current in response to the comparator output; and a driving stage having a first input coupled to the control bus, and an output for providing the charging current, wherein the output of the driving stage comprises the output of the regulated charge pump.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: March 19, 2024
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Semen Syroiezhin, Andreas Baenisch, Stephan Leuschner, Andreas Wickmann
  • Patent number: 11936375
    Abstract: A buffer apparatus, a chip and an electronic device. The apparatus comprises: a voltage adjustment module (10) comprising a first P-type metal-oxide-semiconductor field-effect transistor (PMOS), wherein the voltage adjustment module (10) is used for receiving an input voltage, using a threshold voltage for the first PMOS to adjust the input voltage, and outputting a driving voltage; and a buffer module (20) electrically connected to the voltage adjustment module (10) and used for receiving an input signal, buffering the input signal under the driving voltage, and outputting a buffered signal. The driving voltage obtained by using the threshold voltage for the first PMOS to adjust the input voltage can compensate for a process corner of the buffer module (20), such that the range of a flip point voltage of the buffer module (20) becomes small and meets process requirements.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: March 19, 2024
    Assignee: Chipone Technology (Beijing) Co., LTD.
    Inventors: Wei Yang, Lei Fan
  • Patent number: 11900999
    Abstract: A memory system may include multiple memory cells to store logical data and cycle tracking circuitry to track a number of cycles associated the memory cells. The cycles may be representative of one or more past accesses of the memory cells. The memory system may also include control circuitry to access the memory cells. Accessing of the memory cell may include a read operation, a write operation, or both. During the accessing of the memory cell, the control circuitry may determine a voltage parameter of the access based at least in part on the tracked number of cycles.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Hari Giduturi
  • Patent number: 11894055
    Abstract: A semiconductor device includes: a peripheral circuit region including circuit elements on a substrate, the circuit elements of a page buffer and a row decoder; and a cell region including gate electrode layers, stacked in a first direction, perpendicular to an upper surface of the substrate, and connected to the row decoder, and channel structures extending in the first direction to penetrate through the gate electrode layers and to be connected to the page buffer. The row decoder includes high-voltage elements, operating at a first power supply voltage, and low-voltage elements operating at a second power supply voltage, lower than the first power supply voltage. Among the high-voltage elements, at least one first high-voltage device is in a first well region doped with impurities having a first conductivity-type.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: February 6, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ansoo Park, Ahreum Kim, Homoon Shin
  • Patent number: 11888307
    Abstract: Isolation circuit system and a signal isolation method thereof. The system includes: a power management unit, configured to output a first signal to a digital logic circuit when power down is detected in a first circuit area, and output a second signal to the digital logic circuit when no power down is detected in the first circuit area; the digital logic circuit, configured to perform logical processing on the first signal received from the power management unit before outputting an isolation signal to the isolation circuit, and perform logical processing on the second signal received from the power management unit before outputting a connection signal to the isolation circuit; and the isolation circuit, configured to block the interactive signal, or to output the interactive signal to a second circuit area after the interactive signal is processed through voltage stabilization.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: January 30, 2024
    Assignee: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI
    Inventor: Qiao Huang
  • Patent number: 11848050
    Abstract: The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: December 19, 2023
    Assignee: Hefei Reliance Memory Limited
    Inventor: Brent Steven Haukness
  • Patent number: 11843311
    Abstract: A switching power supply module and a memory storage device are disclosed. The switching power supply module includes a first voltage regulation circuit, a second voltage regulation circuit, a switch circuit and a control circuit. The first voltage regulation circuit is configured to regulate an original power as a first power. The second voltage regulation circuit is configured to regulate the original power as a second power. The control circuit is configured to control the switch circuit to conduct a first power supply path under a first status to provide the first power to the first power supply target. The control circuit is further configured to control the switch circuit to conduct a second power supply path under a second status to provide the second power to the second power supply target.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: December 12, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Shu-Han Chou
  • Patent number: 11830571
    Abstract: A read-write conversion circuit, a read-write conversion circuit driving method, and a memory are provided. The read-write conversion circuit includes a first precharge circuit, a positive feedback circuit, a second precharge circuit, a fourth switch unit, a sixth switch unit, a seventh switch unit, an eighth switch unit, a tenth switch unit, an eleventh switch unit, a twelfth switch unit, a thirteenth switch unit, a fourteenth switch unit, and a fifteenth switch unit. In the read-write conversion circuit, corresponding signals can be read from a third signal terminal and a fourth signal terminal by using only one of a first signal terminal or a second signal terminal in a signal read stage, and corresponding signals can be written to the first signal terminal and the second signal terminal by using only one of the third signal terminal or the fourth signal terminal in a signal write stage.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: November 28, 2023
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: WeiBing Shang
  • Patent number: 11823762
    Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second TO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.
    Type: Grant
    Filed: January 4, 2023
    Date of Patent: November 21, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Jungwon Suh, Joon Young Park, Mahalingam Nagarajan
  • Patent number: 11823980
    Abstract: A package structure is provided. The package structure includes a first semiconductor package and a second semiconductor package connected to the first semiconductor package. The first semiconductor package includes an integrated circuit. The integrated circuit includes a first semiconductor die and a plurality of second semiconductor dies, the plurality of second semiconductor dies are stacked on the first semiconductor die, wherein at least one of orthogonal projections of the plurality of second semiconductor dies is partially overlapped an orthogonal projection of the first semiconductor die. The integrated circuit further includes through vias formed aside the first semiconductor and arranged in a non-overlapped region of the at least one of the orthogonal projections of the plurality of second semiconductor dies with the orthogonal projection of the first semiconductor die. A manufacturing method of a package structure is also provided.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzuan-Horng Liu, Hao-Yi Tsai
  • Patent number: 11818897
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: November 14, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11783886
    Abstract: Disclosed herein is an apparatus that includes: a driver circuit configured to operate on a power voltage supplied from an internal power supply line; a first external power supply line supplied with a first external power voltage; a second external power supply line supplied with a second external power voltage; a plurality of first switch circuits coupled between the first external power supply line and the internal power supply line, the plurality of first switch circuits being arranged on a plurality of first circuit areas; and a plurality of second switch circuits coupled between the second external power supply line and the internal power supply line, the plurality of second switch circuits being arranged on a plurality of second circuit areas. The plurality of first circuit areas and the plurality of second circuit areas are arranged in a first direction in a predetermined order.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hiroshi Shimizu, Yuki Miura
  • Patent number: 11770936
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: September 26, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11768531
    Abstract: A storage controller includes a plurality of pipeline stages configured to process data. A system clock signal is received that has a system frequency and at least one performance metric is determined for one or more pipeline stages of the plurality of pipeline stages. A first clock signal is generated having a first frequency for operation of a first pipeline stage of the plurality of pipeline stages. Based at least in part on the at least one determined performance metric, a second clock signal is generated having a second frequency for operation of a second pipeline stage of the plurality of pipeline stages. The second frequency is less than the system frequency and may also differ from the first frequency.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: September 26, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dinesh Matta, Raghu Voleti, Sitaram Banda, Mikael Mortensen
  • Patent number: 11756595
    Abstract: A memory device includes memory cells operably connected to column signal lines and to word signal lines. The column signal lines associated with one or more memory cells to be accessed (e.g., read) are precharged to a first voltage level. The column signal lines not associated with the one or more memory cells to be accessed are precharged to a second voltage level, where the second voltage level is less than the first voltage level.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ed McCombs
  • Patent number: 11749357
    Abstract: A memory device may include a pin for receiving a direct current (DC) voltage indicating an operating configuration setting of the memory device and for communicating an alternating current (AC) voltage signal that provides feedback to a power management component. The memory device may determine that a supply voltage is outside of a target range, and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled with a capacitive component the passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: September 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Baekkyu Choi, Fuad Badrieh, Thomas H. Kinsley
  • Patent number: 11737283
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: August 22, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11733766
    Abstract: A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: August 22, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Yu Pu, Yang Du
  • Patent number: 11735263
    Abstract: A method of operating a memory circuit includes generating a first voltage by a first amplifier circuit of a first driver circuit coupled to a first column of memory cells, and generating a first current in response to the first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-I Su, Chung-Cheng Chou, Yu-Der Chih, Zheng-Jun Lin
  • Patent number: 11721386
    Abstract: Techniques, apparatus, and devices for managing power in a memory die are described. A memory die may include an array of memory cells and one or more voltage sensors. Each voltage sensor may be on the same substrate as the array of memory cells and may sense a voltage at a location associated with the array. The voltage sensors may generate one or more analog voltage signals that may be converted to one or more digital signals on the memory die. In some cases, the analog voltage signals may be converted to digital signals using an oscillator and a counter on the memory die. The digital signal may be provided to a power management integrated circuit (PMIC), which may adjust a voltage supplied to the array based on the digital signal.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Fuad Badrieh, Thomas H. Kinsley, Baekkyu Choi
  • Patent number: 11715501
    Abstract: Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Haruki Mori, Chien-Chi Tien, Chia-En Huang, Hidehiro Fujiwara, Yen-Huei Chen, Feng-Lun Chen
  • Patent number: 11703927
    Abstract: A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Oren Zonensain, Roman Rechter, Almog Reshef, Maxim Levit, Nadav Shulman, Efraim Rotem
  • Patent number: 11696450
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: July 4, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11696451
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: July 4, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11682432
    Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: June 20, 2023
    Assignee: Arm Limited
    Inventors: Supreet Jeloka, Saurabh Pijuskumar Sinha, Shidhartha Das, Mudit Bhargava, Rahul Mathur
  • Patent number: 11669278
    Abstract: Methods, systems, and devices related to page policies for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may be configured to receive a read command for data stored in the memory array and transfer the data from the memory array to the signal development cache. The memory device may be configured to sense the data using an array of sense amplifiers. The memory device may be configured to write the data from the signal development cache back to the memory array based on one or more policies.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 6, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Dmitri A. Yudanov, Shanky Kumar Jain
  • Patent number: 11670347
    Abstract: A semiconductor device includes a data input/output control block including a first power gating circuit coupled to a supply terminal of a first voltage and a second power gating circuit coupled to a supply terminal of a second voltage, the data input/output control block suitable for generating a control signal using the first and second voltages, a data input/output block including a third power gating circuit coupled to any one of the supply terminal of the first voltage and the supply terminal of the second voltage, the data input/output block suitable for inputting and outputting a data signal using the first and second voltages based on the control signal, and a memory block, coupled to the data input/output block, suitable for writing or reading the data signal.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: June 6, 2023
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Yoo-Jong Lee, A-Ram Rim
  • Patent number: 11651802
    Abstract: The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: May 16, 2023
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventor: Syed M. Alam
  • Patent number: 11640512
    Abstract: A multimedia card includes a substrate, and a main control chip, a memory chip, and an interface contacts that are disposed on the substrate. The main control chip and the memory chip are covered with a packaging layer. The interface contacts includes a power contact, configured to receive a first voltage that is input from the outside; and a transformer circuit is further disposed on the substrate, is coupled to the interface contacts, the main control chip, and the memory chip, and is configured to convert the input first voltage into a second voltage, to provide two types of power supplies with the first voltage and the second voltage for the main control chip and the memory chip. In the foregoing manner, an area of the multimedia card is reduced, and a quantity of working modes of the multimedia card increases.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: May 2, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Zhongzheng Li, Jian Zhou, Zhixiong Li, Jingyang Wang
  • Patent number: 11636907
    Abstract: An Integrated Circuit (IC) includes a non-volatile memory (NVM) and secure power-up circuitry. The NVM is configured to store an operational state of the IC. The secure power-up circuitry is configured to (i) during a power-up sequence of the IC, perform a first readout of the operational state from the NVM while a supply voltage of the IC is within a first voltage range, (ii) if the operational state read from the NVM in the first readout is a state that permits access to a sensitive resource of the IC, verify that the supply voltage is within a second voltage range, more stringent than the first voltage range, and then perform a second readout of the operational state from the NVM, and (iii) initiate a responsive action in response to a discrepancy between the operational states read from the NVM in the first readout and in the second readout.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 25, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Ziv Hershman, Yoel Hayon, Moshe Alon
  • Patent number: 11626146
    Abstract: The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: April 11, 2023
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventor: Syed M. Alam
  • Patent number: 11605405
    Abstract: Methods, systems, and devices for power switching for embedded memory are described. A system may be configured with circuitry (e.g., power supply switching circuitry) coupled with or between a power supply and a power input node of a memory device, which may support selectively coupling or isolating the memory device and the power supply based on various conditions. For example, the circuitry may be configured for a selective coupling or a selective isolation based on a voltage level of the power supply satisfying various voltage thresholds. The circuitry may also be configured to support various input or output signaling, such as transmitting an indication of an isolation from the power supply, transmitting an indication to perform a memory initialization, or receiving an indication or command to perform a power cycle.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: March 14, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Rainer Frank Bonitz
  • Patent number: 11574687
    Abstract: A memory device may include a pin for receiving a direct current (DC) voltage indicating an operating configuration setting of the memory device and for communicating an alternating current (AC) voltage signal that provides feedback to a power management component. The memory device may determine that a supply voltage is outside of a target range, and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled with a capacitive component the passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Baekkyu Choi, Fuad Badrieh, Thomas H. Kinsley
  • Patent number: 11551730
    Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: January 10, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Jungwon Suh, Joon Young Park, Mahalingam Nagarajan
  • Patent number: 11543871
    Abstract: A storage device includes a solid state drive (SSD), a field programmable gate array (FPGA), a power sensor and a global controller. The SSD stores data and receives power through a power rail connected to a host device. The FPGA processes data read from the SSD or data to be stored in the SSD and receives power through the power rail. The power sensor is connected to the power rail and generates a measured power value corresponding to a total power consumed by the SSD and the FPGA by measuring the total power. The global controller determines one of the SSD and the FPGA as a priority component operating with a fixed performance and determines the other of the SSD and the FPGA as a non-priority component operating with a variable performance in a priority mode based on power control information provided from the host device.
    Type: Grant
    Filed: April 25, 2021
    Date of Patent: January 3, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongin Lee, Hyuk Lee, Seunghyun Choi
  • Patent number: 11532348
    Abstract: A variety of applications can include multiple memory die packages configured to engage in peak power management (PPM) across the multiple packages of memory dies. A communication line coupled to each memory die in the multiple memory die packages can be used to facilitate the PPM. A global management die can start a communication sequence among the multiple memory die packages to share a current budget across the multiple memory die packages by driving a signal on the communication line. Local management dies can use the received signal having clock pulses driven by the global management die on the communication line to engage in the PPM. To engage in global PPM, each memory die can be structured, to be selected as the global management die or a local management die, with one or more controllers to interface with the multiple memory die packages and to handle current budget limits.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: December 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Liang Yu, Jeremy Wayne Butterfield, Jeremy Binfet
  • Patent number: 11527277
    Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ā€˜nā€™ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: December 13, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11500447
    Abstract: The present disclosure generally relates to power management for an external storage device. The external storage device includes a power allocation unit coupled to an array of memory devices. A single bridge is present to provide a connection to a host device. The memory devices have operational power states that utilize a first amount of power and non-operational power states that utilize a second amount of power that is less than the first amount of power. The power allocation unit changes the power state of the individual memory devices between operational and non-operational based upon need, but also ensures that the external storage device does not exceed the total power allocation. Thus, the power allocation unit may change a power state of one memory device from operational to non-operational in order to change the power state of another memory device from non-operational to operational.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: November 15, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Avichay Haim Hodes, Judah Gamliel Hahn
  • Patent number: 11495288
    Abstract: A disclosed sense circuit for a memory circuit includes sense amplifiers that detect differences in voltage levels on complementary bitlines during read operations. Instead of the sense amplifiers having built-in footer devices that lead to significant leakage, the sense circuit incorporates a common footer device for all sense amplifiers. To ensure that this footer device has sufficient drive strength to enable voltage differential detection by each sense amplifier, the sense circuit also includes a sense signal generation and boost circuit (SSG&B circuit) that generates a sense mode control signal (SEN) to control the on/off states of the footer device and that further boosts SEN, at the appropriate time, to increase the drive current. By using the common footer device and the SSG&B circuit, leakage from the sense circuit is reduced during a pre-charge operation mode without sacrificing performance during a read operation mode. Also disclosed are associated method embodiments.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: November 8, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Vivek Raj, Shivraj G. Dharne, Uttam K. Saha, Mahbub Rashed
  • Patent number: 11482272
    Abstract: An electronic device and a semiconductor package structure are provided. The device includes a plurality of semiconductor dies stacked vertically over each other and a power supply system. The semiconductor dies are stacked over the power supply system. The power supply system includes: a voltage generating circuit configured to generate at least one voltage. The at least one voltage is provided to the plurality of semiconductor dies through a power interconnecting structure. The semiconductor package structure includes a package substrate; at least one semiconductor die disposed on the package substrate; and the power supply system disposed on the package substrate. The at least one semiconductor die may include a plurality of semiconductor dies vertically stacked on the package substrate.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: October 25, 2022
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Shu-Liang Ning
  • Patent number: 11462269
    Abstract: An embodiment phase-change memory device includes a memory array provided with a plurality of phase-change memory cells, each having a body made of phase-change material and a first state, in which the phase-change material is completely in an amorphous phase, and at least one second state, in which the phase-change material is partially in the amorphous phase and partially in a crystalline phase. A programming-pulse generator applies to the memory cells rectangular dynamic-programming pulses having an amplitude and a duration calibrated for switching the memory cells from the first state to the second state.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: October 4, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Giovanni Campardo, Massimo Borghi, Paola Zuliani, Marco Barboni
  • Patent number: 11450388
    Abstract: Dynamic trim selection based on operating voltage levels for semiconductor devices and associated methods and systems are disclosed. Certain semiconductor devices are expected to operate under two or more operating voltage levels. In some embodiments, the semiconductor device can be characterized to determine optimum timing and/or voltage conditions across multiple operating voltage levels. Consequently, multiple sets of timing and/or voltage conditions can be identified depending on the operating voltage levels, which can be stored in a non-volatile memory (NVM) array of the semiconductor device. During operation, the semiconductor device can determine the operating voltage level currently supplied to the semiconductor device and select one of the timing and/or voltage conditions stored in the NVM array such that the semiconductor device can operate with the optimum timing and/or voltage conditions that has been predetermined for the semiconductor device operating under the operating voltage level.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, James S. Rehmeyer
  • Patent number: 11436169
    Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Matthew A. Prather
  • Patent number: 11424713
    Abstract: A motor drive including an inverter and control logic and a method implemented by the control logic to protect an inverter. The method includes determining a temperature value of a temperature associated with the inverter; preventing restarting of the inverter if the temperature value exceeds a first temperature threshold; and preventing restarting of the inverter if the temperature value exceeds a second temperature threshold that is smaller than the first temperature threshold and the inverter was shut down due to a high load condition.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: August 23, 2022
    Assignee: FRANKLIN ELECTRIC CO., INC.
    Inventors: Douglas C. Lynn, Shengnan Li, Richard J. Halsey
  • Patent number: 11423978
    Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sahil Preet Singh, Yen-Huei Chen, Hung-Jen Liao