Abstract: A voltage regulator dynamically adjusts the voltage distribution on a voltage rail based on multiple feedback measurements. The voltage regulator provides electrical power to a voltage rail at multiple power supply locations along the voltage rail. The voltage regulator obtains voltage measurements from multiple voltage sensing locations on the voltage rail and detects a spatially unequal voltage deviation in the voltage rail. The voltage regulator adjusts the electrical power provided to the voltage rail at each of the power supply locations to compensate for the spatially unequal voltage deviation in the voltage rail.

Abstract: A power-supply device and an electronic device including the relate to technology for a data storage device. The electronic device includes a power-supply device and a controller. The power-supply device generates a sudden power loss (SPL) detection signal in a sudden power off (SPO) state by detecting a level of an external power, generates a charging sense signal indicative of a charging capacity of an auxiliary power-supply circuit, divides the charging capacity into a plurality of charging levels, detects a level of the charging capacity, and generates a charging sense signal indicating a charging level of the auxiliary power-supply circuit in response to the detected charging level. The controller stores flushing information in at least one non-volatile memory device when the SPL detection signal is activated, and variably adjust an amount of storage in the non-volatile memory device in response to the charging sense signal.

Abstract: A solid state memory system includes: an interface circuit; a device processor configured to receive a dynamic power limit command through the interface circuit and update a metadata log based on the dynamic power limit command; a non-volatile memory array coupled to the interface circuit; and a power manager unit, coupled to the device processor, configured by the device processor, the power manager unit configured to adjust voltages for read, write, erase, and monitoring a voltage feedback in order to verify the dynamic power limit command is not exceeded; and a data error detection-and-correction unit, coupled to the power manager unit, configured to pause correction of error data, select a low power error correction code unit, enable a reduced ECC array, switch from error detection-and-correction to error detection, or a combination thereof in response to the dynamic power limit command.

Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.

Abstract: A static random-access memory (SRAM) semiconductor device including a memory unit is provided. The memory unit includes a bit array arranged in rows and columns. The columns are defined by a plurality of bit line pairs connecting to a plurality of memory cells in the column. The memory unit also includes an edge area adjacent an edge row of the bit array, wherein the edge row includes a plurality of dummy memory cells. The memory unit further includes a plurality of bit line drivers adjacent the bit array and opposite the edge area. The bit line drivers are for driving the bit lines with data to the memory cells during a write operation. The dummy memory cells include a write assist circuit for each bit line pair. The write assist circuit is used for facilitating the writing of the data on the bit line pairs to the memory cells.

Abstract: A processing system includes a memory controller that preemptively exits a dynamic random access (DRAM) integrated circuit rank from a low power mode such as power down mode based on a predicted time when the memory controller will receive a request to access the DRAM rank. The memory controller tracks how long after a DRAM rank enters the low power mode before a request to access the DRAM rank is received by the memory controller. Based on a history of the timing of access requests, the memory controller predicts for each DRAM rank a predicted time reflecting how long after entering low power mode a request to access each DRAM rank is expected to be received. The memory controller speculatively exits the DRAM rank from the low power mode based on the predicted time and prior to receiving a request to access the DRAM IC rank.

Abstract: A device includes several first switching units and several second switching units. Each of the first switching units transmits in response to a first select signal, an auxiliary signal. Each of the second switching units is coupled to a corresponding one of the first switching units and transmits in response to a second select signal, a write voltage to a corresponding one of multiple circuit cells. The second switching units are coupled with each other in a node which receives the write voltage.

Abstract: A memory device may include a pin for receiving a direct current (DC) voltage indicating an operating configuration setting of the memory device and for communicating an alternating current (AC) voltage signal that provides feedback to a power management component. The memory device may determine that a supply voltage is outside of a target range, and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled with a capacitive component the passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal.

Abstract: A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Abstract: According to one embodiment, there is provided a semiconductor device comprising a first differential amplifier circuit. The first differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The second transistor's gate and drain are connected to the first transistor. The third transistor is diode-connected through the first transistor or diode-connected without passing through the first transistor. Thea fourth transistor is diode-connected through the second transistor or diode-connected without passing through the second transistor. The fifth transistor forms a first current mirror circuit with the third transistor. The sixth transistor is connected to a drain of the first transistor in parallel with the third transistor and forms a second current mirror circuit with the fifth transistor.

Abstract: In an embodiment, a voltage regulation circuit includes a regulation circuit with a voltage regulator that provides an output voltage and a control circuit, coupled to the voltage regulator. The control circuit pulls up the output voltage to a reference voltage responsive to the control circuit detecting that a first voltage level of the output voltage is lower than a predefined voltage level. The control circuit decouples the output voltage from the reference voltage responsive to the control circuit detecting that the first voltage level of the output voltage is higher than the predefined voltage level.

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a functional device including a selection device; and a bias generator circuit coupled to the selection device and configured to detect a leakage current of the functional device and generate a bias voltage based on the detected leakage current. The bias voltage is provided to the selection device to control the selection device.

Abstract: The invention relates to the field of transmitting series of data between electronic circuits, and more specifically a method and a system for transmitting series of data, from a first electronic circuit to at least one second electronic circuit, via an electrical connection line between the first circuit and the second circuit, in reference to a ground line common to the circuits, of at least one series of data pulses. Each data pulse makes it possible to both electrically supply the second circuit and to transmit an item of data which can be interpreted by the second circuit. The supplying of the second circuit by the first circuit is cut between two successive pulses. For each data pulse and before the second circuit is switched off, because of failure in supply, the item of data transmitted by the pulse is stored on a non-volatile memory support of the second circuit.

Abstract: A power switch control circuit includes a supply rail configured to supply power to a memory array. A first header switch couples the supply rail to a first power supply that corresponds to a first power domain. A second header switch couples the supply rail to a second power supply that corresponds to a second power domain. A control circuit is configured to receive a select signal and a shutdown signal, and to output control signals to the first and second header switches to selectively couple the first and second header switches to the first and second power supplies, respectively, in response to the select signal and the shutdown signal. The control circuit is configured to output the control signals to the first and second header switches to disconnect both the first and second header switches from the first and second power supplies in response to the shutdown signal and irrespective of the select signal.

Abstract: A semiconductor storage device includes a first word line electrically connected to a first memory cell, a second word line electrically connected to a second memory cell, and a voltage generation circuit configured to supply a first voltage to a first line electrically connected to the first word line and a second voltage to a second line electrically connected to the second word line. The voltage generation circuit includes a first regulator configured to output the first voltage to the first line and output a first signal according to the first voltage, a second regulator configured to output the second voltage to the second line and output a second signal according to the second voltage, and a switch circuit configured to open or close an electrically conductive path between the first line and the second line, based on at least one of the first signal and the second signal.

Abstract: An integrated circuit including: an oscillator configured to generate an oscillating voltage with a predetermined oscillation frequency in an oscillation period; a voltage regulator configured to generate an output voltage for driving the oscillator and provide the output voltage to the oscillator; and a current injection circuit configured to provide an oscillation current to the oscillator, in response to an oscillation enable signal in the oscillation period.

Abstract: A semiconductor device has a first memory circuit comprising a first memory cell comprising a first field effect transistor, a second memory circuit comprising a second memory cell comprising a second field effect transistor, and a regulator for converting the first power supply potential to a second voltage value lower than the voltage value of the first power supply potential. The second gate length of the second field effect transistor is longer than the first gate length of the first field effect transistor, the first memory cell is supplied with a second power supply potential through regulator, and the second memory cell is supplied with a first power supply potential.

Abstract: Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.

Abstract: A method of producing an apparatus comprising an electrical circuit that has one or more characteristics that meet a design specification is presented. The method includes designing the electrical circuit with a trim circuit having a trim value that is variable, The electrical circuit is adjustable based on the trim value of the trim circuit. There is encoding of the functional circuit information and/or trim circuit information in a tag, The method has a reading of the functional circuit information and/or the trim circuit information stored in the tag and the determining of the trim value for the trim circuit that results in the characteristic of the electrical circuit meeting the design specification using the functional circuit information and/or the trim circuit information.

Abstract: A memory system may include memory circuitry and power circuitry, which may include a power storage device. The memory system may also include a controller to determine a power demand of the memory circuitry. In response to determining that the power demand is less than an incoming supply power, the controller may generate a first mode signal to induce a charging state of the power storage device. Additionally, in response to determining that the power demand is greater than the incoming supply power, the controller may generate a second mode signal to cause the power storage device to provide a secondary power to the memory circuitry.

Abstract: Memory circuits used in computer systems may have different operating modes. In a retention mode, a voltage level of an array power supply node coupled to memory cells included in the memory circuit is reduced to a level sufficient to retain data, but not to perform read and write operations to the memory cells. A power converter circuit may be configured to generate the retention voltage level, and adjust the retention voltage level using a leakage current of dummy memory cells included in the memory circuit.

Abstract: Provided herein may be a memory controller configured to control a memory device for storing data. The memory controller may include: a voltage sensor configured to detect whether a level of a power supply voltage to be applied to the memory device and the memory controller is equal to or less than a reference level, and generate detect information; and a power controller configured to receive the detect information and output, to the memory device, a power supply voltage reset command for resetting the power supply voltage to be applied to the memory device, wherein the reference level is greater than the voltage level for initiating reset of the memory device and the memory controller and less than the voltage level required for the memory device and the memory controller to perform an operation.

Abstract: A hierarchy of interconnected memory retention (MR) circuits detect a clock gating mode being entered at any level of an integrated circuit. In response, the hierarchy automatically transitions memory at the clock gated level and all levels below the clock-gated level from a normal operating state to a memory retention state. When a memory transitions from a normal operating state to a memory retention state, the memory transitions from a higher power state (corresponding to the normal operating state) to a lower power state (corresponding to the memory retention state). Thus, in addition to the dynamic power savings caused by the clock gating mode, the hierarchy of MR circuits automatically transitions the memory modules at the clock gated level and all levels below the clock gated level to a lower power state. As a result, the leakage power consumption of the corresponding memory modules is reduced relative to prior approaches.

Abstract: A signal calibration method that includes the steps outlined below is provided. A phase of an under-test signal generated by a memory controller is set to initiate a calibration process. A low-power status control command is issued by transmitting signals that include the under-test signal generated by the memory controller to a memory unit to switch the memory unit to a low power status, the low-power status control command forcing the under-test signal to toggle. A read command is issued by the memory controller to the memory unit for reading data. When the responded data does not match the predetermined data, the phase of the under-test signal is determined to be within a timing margin by the memory controller. When the responded data matches the predetermined data, the phase of the under-test signal is determined to be not within the timing margin by the memory controller.

Abstract: Circuits and methods for controlling the startup of multiple parallel power converters that avoid in-rush current and/or switch over-stress in an added power converter or a power converter having one or more fault conditions. Embodiments include node status detectors coupled to selected nodes within parallel-connected power converters to monitor voltage and/or current, and configured in some embodiments to work in parallel with an output status detector measuring the output voltage of an associated power converter during startup. With charge pump-based power converters, the node status detectors ensure that the pump capacitors of each power converter are adequately charged while the output capacitor is charged as well. For such embodiments, a soft-start period of startup may be considered finished if both the shared output capacitors and the pump capacitors of each power converter are charged to selected target values. Embodiments may also be used for fault detection during steady-state operation.

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

Abstract: An integrated circuit and an operating method thereof are provided. The integrated circuit includes memory cells, at least one first word line, second word lines, bit lines and write-assist bit lines. The at least one first word line is electrically connected to at least one row of the memory cells. The second word lines are electrically connected to other rows of the memory cells. Two bit lines are located between a column of the memory cells and two write-assist bit lines. The bit lines and the write-assist bit lines are configured to be electrically disconnected with each other when at least one of the memory cells electrically connected with the at least one first word line is configured to be written, and electrically connected with each other when at least one of the memory cells electrically connected to the second word lines is configured to be written.

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Abstract: A memory device is provided including physical block circuitry including a first lateral network arrangement and a second lateral network arrangement. Each of the first and second lateral network arrangements includes a single generator configured to output both a sense amplifier voltage VHSA and a data latch voltage VDDSA, in each of a first mode and a second mode. In the first mode, during which read and program verify and other operations may occur, the generator receives VHSA as a feedback signal and in the second mode, during which programming, POR, and EVFY operations may occur, the generator receives VDDSA as a feedback signal.

Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

Abstract: A semiconductor device includes a data input/output control block including a first power gating circuit coupled to a supply terminal of a first voltage and a second power gating circuit coupled to a supply terminal of a second voltage, the data input/output control block suitable for generating a control signal using the first and second voltages, a data input/output block including a third power gating circuit coupled to any one of the supply terminal of the first voltage and the supply terminal of the second voltage, the data input/output block suitable for inputting and outputting a data signal using the first and second voltages based on the control signal, and a memory block, coupled to the data input/output block, suitable for writing or reading the data signal.

Abstract: Aspects of the present invention provide a memory system comprising a plurality of stacked memory layers, each memory layer divided into memory sections, wherein each memory section connects to a neighboring memory section in an adjacent memory layer, and a logic layer stacked among the plurality of memory layers, the logic layer divided into logic sections, each logic section including a memory processing core, wherein each logic section connects to a neighboring memory section in an adjacent memory layer to form a memory vault of connected logic and memory sections, and wherein each logic section is configured to communicate directly or indirectly with a host processor. Accordingly, each memory processing core may be configured to respond to a procedure call from the host processor by processing data stored in its respective memory vault and providing a result to the host processor. As a result, increased performance may be provided.

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract: An apparatus for erasing non-volatile storage elements in a non-volatile memory system is disclosed. The apparatus has consistent speed in gate induced drain leakage (GIDL) erase across the operating temperature of the memory system. In one aspect, a voltage source outputs an erase voltage to NAND strings. The NAND strings may draw a GIDL erase current in response to the erase voltage. The amount of GIDL erase current for a given erase voltage is highly temperature dependent. The GIDL erase current may be sampled, and the erase voltage regulated based on the GIDL erase current. Therefore, the GIDL erase current, as well as erase speed, may be kept uniform across operating temperatures.

Abstract: The present subject matter relates to charge pump devices, systems, and methods in which a first plurality of series-connected charge-pump stages is connected between a supply voltage node and a first circuit node, wherein the first plurality of charge-pump stages are operable to produce a first electrical charge at the first circuit node, the first electrical charge having a first polarity; and a second plurality of series-connected charge-pump stages is connected between the supply voltage node and a second circuit node, wherein the second plurality of charge-pump stages are operable to produce a second electrical charge at the second circuit node, the second electrical charge having a second polarity.

Abstract: Disclosed herein is an apparatus that includes a first wiring layer including a first power line extending in a first direction, a second wiring layer including second and third power lines extending in a second direction, a third wiring layer including power electrode patterns arranged in the second direction, and a fourth wiring layer including a fourth power line extending in the second direction. The first and second power lines are connected by a first via electrode. The first and third power lines are connected by a second via electrode. The second power line and each of the power electrode patterns are connected by a third via electrode. The third power line and each of the power electrode patterns are connected by a fourth via electrode. The fourth power line and each of the power electrode patterns are connected by a fifth via electrode.

Abstract: Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.

Abstract: A semiconductor memory device comprises: a memory transistor; a first wiring connected to a gate electrode of the memory transistor; and a control device that executes a read operation to read data of the memory transistor and a write operation to write data in the memory transistor. In the read operation or the write operation, the control device: increases a voltage of the first wiring to a first voltage from a first timing to a second timing; and adjusts a length from the first timing to the second timing corresponding to at least one of a voltage of the first wiring, a current of the first wiring, and an amount of charge flowed through the first wiring.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for an on-die capacitor. A memory chip comprises an array of memory cells. A capacitor is electrically coupled to an array of memory cells. A capacitor receives at least a portion of discharged electricity from an operation for an array of memory cells. A capacitor supplies electricity back to an array of memory cells during a subsequent operation for an array of memory cells.

Abstract: A method and system for dynamically allocating power resources. The system includes a central controller connected to automatic transfer switches. The system also includes power zones. Each of the power zones includes server devices. Each of the automatic transfer switches are connected to at least one of the power zones. The system also includes a power pool connected to a power source. The power pool is connected to the central controller configured to dynamically allocate power of the power pool to the power zones.

Abstract: A memory device includes a controller connected to first, second, third and fourth switches and configured to selectively operate the switches to connect first and second source voltage input terminals to a memory based on a desired current level required for the memory array.

Abstract: A stacked three dimensional semiconductor device includes multiple thin substrates stacked over one another and over a base substrate. The thin substrates may include a thickness of about 0.1 ?m. In some embodiments, a noise suppression tier is vertically interposed between active device tiers. In some embodiments, each tier includes active device portions and noise suppression portions and the tiers are arranged such that noise suppression portions are vertically interposed between active device portions. The noise suppression portions include decoupling capacitors in a power/ground mesh and alleviate vertical noise.

Abstract: Aspects of the present disclosure generally relate to multi-mode voltage regulators. For example, the regulator may include a first voltage regulator configured to operate in a first power mode. The first voltage regulator is further configured to selectively adjust an output voltage using one of a voltage output of a replica pass transistor of the first voltage regulator or a voltage output of the pass transistor of the first voltage regulator based on a transition from a second power mode to the first power mode.

Abstract: In one embodiment, a computing device detects a module that is inserted into a first slot. The computing device includes a first slot to operate with a first type of module and a second slot to operate with a second type of module. The first slot and the second slot include a same pin position for receiving a power supply pin from the first type of module and the second type of module. The module is communicated with to determine whether the module is the first type of module or the second type of module. The first type of module receives a first type of signal that is combined with a second type of signal from the second type of module. The computing device adjusts a power supply voltage to the power supply pin of the first slot from a first value to a second value when the first type of module is detected.

Abstract: A system is provided to manage on-chip memory access for multiple threads. The system comprises multiple parallel processing units to execute the threads, and an on-chip memory including multiple memory units and each memory unit includes a first region and a second region. The first region and the second region have different memory addressing schemes for parallel access by the threads. The system further comprises an address decoder coupled to the parallel processing units and the on-chip memory. The address decoder is operative to activate access by the threads to memory locations in the first region or the second region according to decoded address signals from the parallel processing units.

Abstract: Techniques for negative voltage generation for a computer memory are described herein. An aspect includes enabling a first negative word line voltage (VWL) clock generator. Another aspect includes providing, by the first VWL clock generator, based on a clock signal, a first pump clock signal to a first VWL pump, and a second pump clock signal to a second VWL pump. Another aspect includes generating a VWL based on the first VWL pump and the second VWL pump, wherein the VWL is provided to a word line driver of a computer memory module. Another aspect includes comparing the VWL to a VWL reference voltage. Another aspect includes, based on the VWL being below the VWL reference voltage, disabling the first VWL clock generator, wherein the first VWL pump and the second VWL pump are disabled based on disabling the first VWL clock generator.

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract: A power-supply device and an electronic device including the relate to technology for a data storage device. The electronic device includes a power-supply device and a controller. The power-supply device generates a sudden power loss (SPL) detection signal in a sudden power off (SPO) state by detecting a level of an external power, generates a charging sense signal indicative of a charging capacity of an auxiliary power-supply circuit, divides the charging capacity into a plurality of charging levels, detects a level of the charging capacity, and generates a charging sense signal indicating a charging level of the auxiliary power-supply circuit in response to the detected charging level. The controller stores flushing information in at least one non-volatile memory device when the SPL detection signal is activated, and variably adjust an amount of storage in the non-volatile memory device in response to the charging sense signal.

Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.