Abstract: An SRAM facility adapted to power an address path using a first developed supply voltage and to power a data path using a second developed supply voltage, the first and second developed power supplies being separate, distinct, and different. The SRAM facility includes a power supply facility or a voltage supply facility adapted to develop the first and second supply voltages.

Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.

Abstract: The disclosure describes approaches for generating a physically unclonable function (PUF) value. Power is applied to a power control circuit, an SRAM, and a PUF control circuit. After initially powering-up the SRAM, the PUF control circuit signals the power control circuit to disable power to the SRAM. The power control circuit disables power to the SRAM, and then re-enables power to the SRAM after having power to the SRAM disabled for a waiting period. The PUF control circuit reads a PUF value from the SRAM by the PUF control circuit after the enabling of power.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a memory controller, and a plurality of memory devices coupled to the memory controller through a plurality of channels. The memory controller may include a power consumption measurement unit configured to measure power consumption of a memory system at intervals of a predetermined time period and to generate a first signal based on the measured power consumption, and a performance throttling control unit configured to perform an operation of changing performance of the memory system in response to the first signal. The performance throttling control unit may be configured to perform the operation of changing the performance of the memory system a plurality of times within the predetermined time period.

Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.

Abstract: A memory macro includes a first set of memory cells, a second set of memory cells and a set of conductive lines. The first set of memory cells is arranged in columns and rows. Each memory cell of the first set of memory cells includes a voltage supply node configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage. The second set of memory cells includes a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode. The set of conductive lines is coupled to the set of retention circuits and the voltage supply node of each memory cell of the first set of memory cells.

Abstract: A power supply includes an LLC resonant power converter to provide a first reference signal having a first voltage. The power supply also includes a DC-DC power converter to provide a second reference signal having a second voltage. The DC-DC converter receives power from the first reference signal. The power supply further includes a switch circuit including a first input to receive the first reference signal, a second input to receive the second reference signal, an input to receive a switch control message, and an output coupled to a power rail. The switch circuit is configured to connect the first reference signal and the second reference signal to the power rail based on the switch control message.

Abstract: Provided is an input buffer circuit comprising a high-voltage protection unit coupled to a pad and comprising a low-voltage pass unit and a high-voltage pass unit that are coupled in common to an output signal node. The low-voltage pass unit may transfer the first voltage to the output signal node, when a first voltage falling within a first voltage range is applied through the pad. The high-voltage pass unit may transfer a third voltage lower than the second voltage to the output signal node, when a second voltage falling within a second voltage range higher than the first voltage range is applied through the pad.

Abstract: A semiconductor device may include a trimming circuit suitable for generating a reference voltage that is adjusted based on a code value, and an internal voltage generation circuit suitable for generating an internal voltage based on the reference voltage, wherein the internal voltage generation circuit is suitable for dividing the internal voltage in a division ratio that varies depending on an operation mode and for generating the internal voltage based on comparison of the divided internal voltage with the reference voltage.

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract: A semiconductor device includes: a first power source line for supplying a first voltage; a second power source line for supplying a second voltage; a memory circuit coupled with the first and second power source lines; a first switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to a control signal; a second switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to the control signal, wherein a memory circuit includes a memory cell array and a peripheral circuit, wherein a memory cell array includes a plurality of memory cells, the memory cells coupled with the second power source line.

Abstract: A charge pump circuit includes a voltage input port, a voltage output port, a plurality of charge pump units cascaded between the voltage input port and the voltage output port, a clock signal source, and N clock delay elements. The clock signal source generates a main clock signal and the N clock delay elements generate clock signals received by the charge pump units by delaying the main clock signal. The main clock signal received by the first charge pump unit has a rising edge leading a rising edge of the last clock signal received by the last charge pump unit, and a falling edge lagging the rising edge of the last clock signal. Each of the charge pump units includes two sets of inverters with delay elements for generating two complementary clock signals.

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

Abstract: A method and apparatus of performing a memory operation includes receiving a memory operation request at a first memory controller that is in communication with a second memory controller. The first memory controller forwards the memory operation request to the second memory controller. Upon receipt of the memory operation request, the second memory controller provides first information or second information depending on a condition of a pseudo-bank of the second memory controller and a type of the memory operation request.

Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.

Abstract: A semiconductor apparatus includes a sense amplifier configured to sense data transmitted through a data line and a sense amplifier control circuit configured to detect whether a level of an external voltage is equal to or larger than an reference voltage level and control a power voltage of the sense amplifier according to a detection result.

Abstract: Apparatuses and methods for compensating for source voltage are described. An example apparatus includes a source cooled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node or the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source.

Abstract: In one form, a data processing system includes a memory channel having a plurality of ranks, and a data processor. The data processor is coupled to the memory channel and is adapted to access each of the plurality of ranks. In response to detecting a predetermined event, the data processor selects an active rank of the plurality of ranks and places other ranks besides the active rank in a low power state, wherein the other ranks include at least one rank with a pending request at a time of detection of the predetermined event. The data processor subsequently processes a memory access request to the active rank.

Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.

Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.

Abstract: As may be consistent with one or more embodiments, an apparatus and or method involves a switching power supply circuit and a control circuit therefor. The switching power supply circuit operates in high and low-power modes. In the high power mode, high and low power rails of a first circuit and of a second circuit are coupled to a power source circuit (e.g. a battery). In the low-power mode, the first circuit is operated in a high power domain and the second circuit is operated in a low power domain using recycled charge from the high power domain. The control circuit operates the switching circuit in the high-power mode and low-power mode (for power conservation) in response to a control signal.

Abstract: A power supply device includes: a first transformer including a primary winding and a secondary winding; a first control circuit controlling a switching operation of a switch element, and cause the primary winding to generate a first AC voltage; an application circuit receiving a second AC voltage generated in the secondary winding by mutual induction with the primary winding, and apply an output voltage according to the second AC voltage to a load; a voltage detection circuit detecting a magnitude of a DC voltage obtained by rectifying the first AC voltage or the second AC voltage; and an output circuit outputting a stop signal indicating stop of the power supply device, when a result of comparison between the magnitude of the DC voltage and a threshold value set according to a magnitude of the load satisfies a predetermined condition, after reception of an instruction to stop voltage supply.

Abstract: The present disclosure provides a dynamic random access memory (DRAM). The DRAM includes a plurality of banks, a power source and a control device. Each of the banks includes a plurality of subarrays. The control device derives information on a quantity of operated subarrays among the subarrays, and determines how much electrical energy to provide based on the information. The power source provides the resultant amount of electrical energy based on the determination from the control device.

Abstract: To reduce power consumption of a processing device including a processor and a main memory in the processor. The main memory includes not only a volatile memory such as a DRAM but also a nonvolatile memory. The processor monitors access requirements to the main memory. The processor determines on the basis of the monitoring results whether the volatile memory or the nonvolatile memory operates mainly. In the case where the main memory changes from the volatile memory to the nonvolatile memory, part or all of data stored in the volatile memory is backed up to the nonvolatile memory. While the nonvolatile memory operates mainly, supply of power supply voltage to the volatile memory is stopped or power supply voltage to be supplied is lowered.

Abstract: The present disclosure generally relates to a memory cell and methods for generating a pulse within the memory cell. As such, a geometric arrangement of transistors is disclosed that allows the transistor pulse signal generator circuit to precharge both sides of the memory cell and, subsequently, bring opposite sides of the memory cell quickly to different voltages. The circuit and wiring fabrication provided, when combined with a related transistor manufacturing process, yields pulse generating logic at the memory cell to enable the formation of a well-defined pulse while fitting within the 4F2 footprint of the memory cell. As such, the speed and pulse shape requirements of PCM, MRAM, other such cross-point memory technologies, sensor arrays, and/or pixel displays may take advantage of the reduced RC circuitry delays.

Abstract: A data storage device includes a nonvolatile memory device; a control unit configured to generate a descriptor in which works for controlling the nonvolatile memory device are written; a memory control unit configured to provide control signals and write data to the nonvolatile memory device based on the descriptor; and a voltage detector configured to provide a voltage drop signal to the memory control unit in the case where a first operating voltage provided to the memory control unit or a second operating voltage provided to the nonvolatile memory device, drops.

Abstract: An analytical device including a main circuit, a main power supply switch and a control unit which acquires measurement data from main circuit and exchanges data with another device. Said analytical device further includes a hard switch and a relay switch which assumes either an ON state in which electric power is supplied to the main circuit or an OFF state in which electric power is not supplied to the main circuit, wherein the control unit, upon receiving input of a first input signal for setting the main power supply switch to an OFF state, if the main circuit is causing the device main body unit to operate, provides notification of the fact that the device main body unit is operating, and upon receiving input of a second input signal for setting the main power supply switch to an OFF state, sets the relay switch to an OFF state.

Abstract: A memory system and method are provided for adaptive auto-sleep and background operations. In one embodiment, a controller of a memory system measures an amount of time between when the memory completes an operation and when the controller receives a command to perform another operation in the memory. The controller adjusts a time period after which the controller enters an auto-sleep mode and/or starts a background operation based on the measured amount of time. Other embodiments are disclosed.

Abstract: A random number generator (RNG) is disclosed. The RNG comprises a memory bit array having a plurality of bits, wherein each bit is configured to present an initial logic state when the memory bit array is powered on; and a first folding circuit coupled to the memory bit array, wherein the first folding circuit is configured to: read initial logic states of a first bit and a second bit of the memory bit array, perform a first logic function on the initial logic state of the first bit, and perform a second logic function on the initial logic state of the second bit to contaminate the initial logic state of the second bit so as to provide an altered initial logic state of the second bit.

Abstract: A memory device and a method for rescheduling memory operations is disclosed. The method includes receiving memory operations for memory arrays of a memory device; storing the memory operations in queues associated with the memory array; estimating power consumption for each of the memory operations queued in the queues based on a power model; determining that a memory operation causes an estimated power consumption of the memory device to be exceeded over an allowable power budget within a first time window; determining a candidate memory operation in the queues that is scheduled to operate in a second time window after the first time window, wherein the candidate memory operation has less power consumption than the memory operation according to the power model; and dynamically reordering the memory operations in the queues and generating rescheduled memory operations by reordering the memory operation out of the first time window and reordering the candidate memory operation into the first time window.

Abstract: Techniques are described that includes using a memory to store data within a system. The techniques include lowering a supply voltage applied to said memory and ceasing use of the memory to store data within the system. The techniques further include reading values from the memory with the supply voltage being lowered. The techniques further include determining a radiation level from an amount of corrupted ones of the values.

Abstract: A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window.

Abstract: A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

Abstract: Devices and methods for non-volatile analog data storage are described herein. In an exemplary embodiment, an analog memory device comprises a potential-carrier source layer, a barrier layer deposited on the source layer, and at least two storage layers deposited on the barrier layer. The memory device can be prepared to write and read data via application of a biasing voltage between the source layer and the storage layers, wherein the biasing voltage causes potential-carriers to migrate into the storage layers. After initialization, data can be written to the memory device by application of a voltage pulse between two storage layers that causes potential-carriers to migrate from one storage layer to another. A difference in concentration of potential carriers caused by migration of potential-carriers between the storage layers results in a voltage that can be measured in order to read the written data.

Abstract: A mass data storage system includes a plurality of communicatively coupled storage resources arranged within a power grid. Responsive to receipt of a data transfer request, a compute node of the mass data storage system selectively powers from an off state one or more of the storage resources to receive incoming data or act as a data source for a read operation.

Abstract: Methods and systems for reducing the settling time of a voltage regulator are described. In some cases, the settling time of the voltage regulator may be reduced by detecting that the voltage regulator is transitioning from a standby mode to an active mode and drawing additional current from the output of the voltage regulator during a current boosting phase. The current boosting phase may correspond with a current boosting pulse that is initiated when an enable signal is received from a controller and then is ended when the output voltage of the voltage regulator is within a first voltage of the desired regulation voltage or has overshot the desired regulation voltage by a second voltage (e.g., has overshot the desired regulation voltage by 150 mV).

Abstract: A method for synchronizing files and an electronic device using the same are described. The method includes receiving a first instruction; executing the application installed on the electronic device according to the first instruction, a first file among a plurality of files for the application converts into a second state from the first state during a process for executing the application; writing the first file with the second state into a network storage by a first file system, in order to enable the application installed on another electronic device to be executed based on the first file with the second state in the network storage. An application progress may be shared and synchronized conveniently without a user's interaction or participation by writing the first file with the converted state into the network storage.

Abstract: A memory system, a semiconductor memory device and methods of operating the same may perform a read operation on the basis of flag data stored in a flag register, without reading the flag data stored in a memory array, when performing the read operation, so that a time taken for the read operation may be reduced.

Abstract: A memory device includes a memory system and an energy storage device including a capacitor. Additionally, the memory storage device includes power delivery circuitry that delivers to the memory system a first power from the energy storage device and a second power from an external power supply coupled to the memory device.

Abstract: A semiconductor integrated circuit device has a memory array including SRAM cells, a plurality of sense amplifiers for reading out data stored in the SRAM cells and a plurality of MOSFETS. The MOSFETs are controlled by a control signal to be in one of an active state or a standby state. Part of the MOSFETs are arranged along one end of the memory array and the other parts of the MOSFETs are arranged along another end of the memory array. The other end of the memory array is opposite to the one end of the memory array. The MOSFETs are controlled by the control signal to be turned ON in the active state and to be turned OFF in the standby mode.

Abstract: Supply of power to a plurality of circuits is controlled efficiently depending on usage conditions and the like of the circuits. An address monitoring circuit monitors whether a cache memory and an input/output interface are in an access state or not, and performs power gating in accordance with the state of the cache memory and the input/output interface. The address monitoring circuit acquires and monitors an address signal between a signal processing circuit and the cache memory or the input/output interface periodically. When one of the cache memory and the input/output interface is in a standby state and the other is in the access state, power gating is performed on the circuit that is in the standby state.

Abstract: A selection circuit and related access circuitry that can be used for column selection in spin-torque magnetic memory is disclosed. The selection circuit can be implemented with three transistors, all of which can be NMOS transistors, thereby reducing area requirements. The selection circuit includes drive transistor that can be autobooted based on the drive voltage applied across the drive transistor. A single control signal controls the state of the selection circuit, and the selection circuits can be nested to provide multiple levels of decoding or selection.

Abstract: A storage device includes a memory cell array, a voltage detector disposed to detect a voltage of power supplied to the memory cell array, and a controller. The controller is configured to carry out reading of data from a target memory cell and then rewriting of the data in the target memory cell, if the detected voltage is above a threshold when a prompt of a read operation with respect to the target memory cell occurs, and prohibit the reading operation from being started, if the detected voltage is below the threshold when the prompt occurs.

Abstract: Systems and methods for low voltage secure digital (SD) interfaces are disclosed. Embodiments of the present disclosure relate to systems and voltage for a lower voltage SD or SD Input/Output (SDIO) interface such as two integrated circuits. In particular, a SD or SDIO interface may be established between two SD compliant devices. While the SD compliant devices may otherwise comply with the SD standard, the voltage levels for signals passed between the SD compliant devices may be below 1.8 volts that the standard mandates. This reduced voltage is possible because the distances involved for interchip communication or the short distances involved for mobile terminal to peripheral connection are short enough that the reduced voltage is sufficient to still provide the desired signal strength at the receiver.

Abstract: A mass data storage system includes a plurality of communicatively coupled storage drives powered by one or more power supplies. A power map defines the relationships between the storage drives and the power supplies and power rules/policies define the maximum permissible power load on each power supply at any point in time.

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

Abstract: An energization range of a laptop PC is controlled for safety component replacement. An EC can communicate with a battery unit to control a FET of the battery unit. In a power-off state, a PWC receives electricity from the battery unit or an AC/DC adapter. In the power-off state, a system of the EC stops. When a housing cover of the laptop PC is opened, a cover switch turns ON. When a logic circuit detects the operation of the cover switch, the PWC controls a DC/DC converter group to activate the system. The EC receiving electricity turns the FET OFF. Then the PWC turns the FET OFF.

Abstract: A voltage supply circuit for a memory cell including a first circuit coupled between a first voltage supply and a first voltage supply terminal of the memory cell, and a second circuit coupled between the first voltage supply and a second voltage supply terminal of the memory cell. The first circuit is controlled by a first bit line of the memory cell, and the second circuit is controlled by a second bit line of the memory cell. The first and second circuits provide the first supply voltage to the first and second voltage supply terminals of the memory cell, respectively, during a pre-charge phase. During a write operation, only one of the first circuit and the second circuit provides the first supply voltage to the memory cell, and the other one of the first circuit and the second circuit provides an adjusted voltage (e.g., a collapsed voltage) to the memory cell.

Abstract: An implantable medical device have an associated memory device is disclosed. The implantable medical device utilizes techniques for optimizing one or more embedded operations of the memory device, such operations including programming, reading or erasing data. The techniques for optimizing the embedded operations include controlling the operations as a function of an energy source of the implantable medical device.

Abstract: A semiconductor memory apparatus performs a selection in a normal readout/write-in mode and an automatic refreshing mode and includes a sense amplifier reading out data from a memory device, a first switching device connecting a first power supply voltage acting as an overdrive voltage to a first power supply intermediate node during a first period and then connecting a second power supply voltage acting as an array voltage to the first power supply intermediate node, a second switching device connecting the fourth power supply voltage to a second power supply intermediate node of the sense amplifier when the sense amplifier is driven, a first capacitor connected to the overdrive voltage and charging it, a third switching device switched on in the automatic refreshing mode, and a voltage generator generating a third power supply voltage and applying it and the first power supply voltage in parallel through the third switching device.