Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump.

Abstract: A power management controller controls a power mode associated with a memory device and includes a logic element operative to provide a power mode control signal. The logic element is responsive to first and second control signals, the second control signal being a delayed version of the first control signal. The first control signal is provided by a processing device, and the power mode control signal transitions (i) inactive before a chip select signal transitions active and/or (ii) active after the chip select signal transitions inactive. The chip select signal controls the memory device, and the power mode control signal controls the power mode associated with the memory device. A corresponding method, computer-readable medium, and electronic system are also disclosed. A method that selects a power control mode associated with the power management controller, which controls a power mode associated with the memory device, is also disclosed.

Abstract: One power management method of a communication interface includes: when receiving a command transmitted via the communication interface, checking if a predetermined criterion is met; and when the predetermined criterion is met, controlling the communication interface to enter a power-saving mode before an end of the received command. Another power management method of a communication interface includes: when the communication interface is operated under a power-saving mode, checking if a predetermined criterion of an executed command is met; and when the predetermined criterion is met, controlling the communication interface to leave the power-saving mode.

Abstract: To provide a nonvolatile memory circuit having a novel structure. A first memory circuit, a second memory circuit, a first switch, a second switch, and a phase inverter circuit are included. The first memory circuit includes a first transistor formed using an oxide semiconductor film, a second transistor, a third transistor, and a capacitor. The first transistor formed using an oxide semiconductor film and the capacitor are used to form the nonvolatile memory circuit. Reductions in number of power supply lines and signal lines which are connected to the memory circuit and transistors used in the memory circuit allow a reduction in circuit scale of the nonvolatile memory circuit.

Abstract: This invention improves the access efficiency of each of a plurality of memory devices mounted on a semiconductor chip. The invention provides a memory control circuit including a queue buffer unit, a management unit to set the CKE signal at High for a memory device to which a determination target access command is to be issued when it is determined that the determination target access command has shifted to the head position of the queue buffer unit, a command generating unit to issue an access command, and a data interface unit to execute processing specified by an access command. The management unit performs control to set the CKE signal to Low for the memory device to which the determination target access command is to be issued based on the state of the queue buffer unit when it is determined that the processing by the data interface unit is complete.

Abstract: The present invention discloses a power supply. The power supply may comprise an input power terminal, a capacitor module, a first converter module and a second converter module. The first converter module may have a first terminal and a second terminal, wherein the first terminal is coupled to the input power terminal and the second terminal is coupled to the capacitor module. The second converter module may comprise an input and an output, wherein the input of the second converter module is coupled to the input power terminal, and the output of the second converter module is configured to supply a load.

Abstract: A communications system includes a communications device having a plurality of access modules each having a port and connected to a communications line and a plurality of transmitters with the respective transmitter associated in one-to-one correspondence with the communications line of an access module. Each transmitter has a line driver and is configured to couple communications signals to a respective communications line. A voltage source is connected to the line drivers and configured to provide a bias voltage to the line drivers that varies depending on a selected minimum power level. A controller is connected to the voltage source and has logic configured to change the bias voltage to the line drivers. The controller is responsive to a minimum data rate for each bias voltage.

Abstract: A semiconductor memory device pertaining to the present invention includes a plurality of memory macros having memory cells and memory peripheral circuits which drive the memory cells; first power supply switches which control power supply to the memory cells; and a second power supply switch which controls power supply to the memory peripheral circuits. The first power supply switches are located within the memory macros, respectively, and provided between a power supply line feeding power to the memory cells and the memory cells. The second power supply switch is located outside the memory macros and provided between the power supply line and a common power supply wiring for the memory peripheral circuits in the plurality of memory macros.

Abstract: A method for operating a memory module device. The method can include transferring a chip select, command, and address information from a host memory controller. The host memory controller can be coupled to a memory interface device, which can be coupled to a memory module. The memory module can comprise a plurality of memory devices. The chip select, command and address information can be received at the memory interface using a command-and-address-latency (CAL) mode. Control logic can be used to initiate a power state transition from a first power state to a second power state of an input termination circuit in the memory interface device.

Abstract: A heterogeneous cache structure provides several memory cells into different ways each associated with different minimum voltages below which the memory cells produce substantial state errors. Reduced voltage operation of the cache may be accompanied by deactivating different ways according to the voltage reduction. The differentiation between the memory cells in the ways may be implemented by devoting different amounts of integrated circuit area to each memory cell either by changing the size of the transistors comprising the memory cell or devoting additional transistors to each memory cell in the form of shared error correcting codes or backup memory cells.

Abstract: A microcontroller system is determining to exit a power saving mode and, in response, enable a reference current source to begin providing a reference current for a memory module. The microcontroller system determines that the reference current has reached a substantial fraction of a target reference current, and, in response to determining that the reference current has reached a substantial fraction of the target reference current, enables the memory module to begin performing one or more memory operations.

Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.

Abstract: Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.

Abstract: Systems, methods, and devices are provided for performing audio processing operations, such as crossfading between two audio streams, by storing information on multiple memories. In one example, such a method may include storing a first portion of information associated with an audio processing operation on a first memory. A second memory may be activated, upon which a second portion of the information associated with the audio processing operation may be stored. The audio processing operation may be performed using a processor with the information stored on the first memory and the second memory. When the audio processing operation has completed, the second memory may be deactivated.

Abstract: An access detection section detects access to an access object circuit and outputs a signal which restricts switching the access object circuit from a first operation state to a second operation state (low power consumption operation state) in which power consumption is lower than power consumption in the first operation state (normal operation state) until no-access period which lasts from last access to next access reaches a first period. An operation control section controls operation of the access object circuit according to the output of the access detection section.

Abstract: In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ?V.

Abstract: Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory.

Abstract: Techniques described herein generally relate to optimizing energy consumption in a computer system. In some examples an energy usage benchmark can be determined for a system component of the computer system by measuring performance levels and energy usages of the system component under a range of energy settings and utilization rates of the system component. A utilization rate of the system component can be determined based on prediction factors including the execution of a first set of instructions on the computer system. The system component can be configured to execute a second set of instructions after the first set of instructions by selecting an energy setting from the range of energy settings for operating the system component. The energy setting can be selected based on the energy usage benchmark and the determined utilization rate.

Abstract: Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.

Abstract: A memory cell is accessed by determining an off-current of a set of memory cells, accessing a memory cell of the set of memory cells during an access period, and compensating for the off-current of the set of memory cells.

Abstract: A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.

Abstract: A semiconductor storage device includes plural bit lines and plural word lines. The memory cell array has plural memory cells that are connected with the bit lines and word lines, and can store data. Plural sense amplifiers detect the data stored in the memory cells. Plural write drivers write data in the memory cells. A comparison buffer temporarily stores the write data to be written in the memory cells by the write driver. In a series of write sequences, the comparison buffer stores the read data from the memory cells selected as the write object and the write data to be written in the selected memory cells. After a series of write sequences, when the pre-charge command for resetting the voltage of the bit lines is received, the write execution command is executed so that the comparison buffer executes write in the selected memory cells.

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Abstract: A circuit for controlling leakage current in random access memory devices comprises a pre-charge equalization circuit. The pre-charge equalization circuit provides a pre-charge voltage to a pair of complementary bit lines of a memory cell of a random access memory device in accordance with a pre-charge signal. When the memory cell is in a self-refresh mode, the pre-charge signal is activated by a periodically triggered pre-charge request and also activated before and after the memory cell is self-refreshed.

Abstract: A semiconductor integrated circuit includes first and second bank groups, a first internal voltage control unit configured to generate a first enable pulse which is enabled when a first read operation or a first write operation is performed for banks included in the first bank group, and a first internal voltage generation unit configured to generate and supply a first internal voltage to the first bank group in response to the first enable pulse, wherein an enable period of the first enable pulse is set to be longer in the first write operation than in the first read operation.

Abstract: A memory device having an array of memory cells and BTI-independent bias circuitry for controlling the bias voltage level of a source node of the array. The bias circuitry has an n-type transistor and a p-type transistor connected in parallel between ground and the source node. The bias circuitry also has circuitry for controlling the n-type and p-type transistors such that the memory device can be selectively configured in any of an active mode (where the source node is driven towards ground such that the array can be accessed), a low-leakage-current light sleep mode (where the source node is driven towards an intermediate, data-retention voltage level such that the array cannot be accessed but will retain data), and an even-lower-leakage-current shutdown mode (where the source node is driven towards the power supply voltage level such that the array cannot be accessed and cannot retain data).

Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.

Abstract: Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and a second power domain coupled to different components of the memory device. One or more distributed power domain coupling circuits may be coupled to the first and second power domains. The power domain coupling circuit includes a controller configured to generate an enable signal responsive to control signals, data signals, or any combination thereof. The power domain coupling circuit also includes coupling circuitry coupled to the first and second power domains and coupled to the controller. The coupling circuitry is configured to couple the first and second power domains together responsive to the enable signal.

Abstract: A device includes a backup power supply configured to provide power to an external system upon loss of primary system power, the backup power provided by at least one capacitor; logic to create, while the capacitor is available as the backup power supply to the external system, a transient elevation of the capacitor's stored potential above a upper predetermined operating potential of the capacitor; logic to obtain measurements of the capacitor's output voltage during the transient elevation of the capacitor's stored potential; and logic to determine a capacitance of the capacitor from the measurements; the device comprising multiple capacitors in series; logic to discharge each capacitor in series individually from the others; and logic to monitor for overcharging of any of the capacitors in series, and, during charging of the capacitors in series, to operate the discharge logic for any capacitor in the series that is in danger of overcharging.

Abstract: A semiconductor device capable of stabilizing power supply by suppressing power consumption as much as possible. The semiconductor device of the invention includes a central processing unit having a plurality of units and a control circuit, and an antenna. The control circuit includes a means for outputting, based on a power supply signal including data on power supply from an antenna (through an antenna) or a load signal obtained by an event signal supplied from each of the units, one or more of a first control signal for stopping power supply to one or more of the units, a second control signal for varying a power supply potential supplied to one or more of the units, and a third control signal for stopping supplying a clock signal to one or more of the units.

Abstract: A memory circuit includes a transistor having a channel in an oxide semiconductor layer, a capacitor, a first arithmetic circuit, a second arithmetic circuit, a third arithmetic circuit, and a switch. An output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit. The input terminal of the second arithmetic circuit is electrically connected to an output terminal of the third arithmetic circuit via the switch. An output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit. An input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor. The other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit.

Abstract: A memory system includes first to third memory devices each having an input terminal for receiving a token signal and an output terminal for transmitting the token signal, wherein the input terminal of each of the first to third memory devices are connected to the output terminal of another memory device through a ring topology, and the first to third memory devices substantially simultaneously perform an operation of consuming a peak current in response to any one of a plurality of token signals.

Abstract: A semiconductor storage device includes a plurality of memory macros including a plurality of memory cell arrays; a low-potential power supply boosting circuit coupling the low-potential power supply to the ground in a normal mode and coupling the low-potential power supply to a voltage higher than a ground voltage in a sleep mode; a virtual power control circuits including a plurality of switches which is turned on when switching from the sleep mode to the normal mode and is turned off when switching from the normal mode to the sleep mode; and a sleep cancellation detecting circuit outputting, when the mode control signal supplied to the plurality of switches in one of the plurality of memory macros indicates to switch form the sleep mode to the normal mode, the mode control signal to a subsequent memory macro subsequent to the one of the plurality of memory macros.

Abstract: An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference voltage level, an internal voltage generator configured to receive a supply voltage as power source and generate the internal voltage in response to an output signal of the voltage detector, and an under-driving unit configured to under-drive an internal voltage terminal to a supply voltage in an under-driving operation region that is determined in response to the operation mode control signal.

Abstract: Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page of the apparatus to reduce power consumed through activation of the disabled ones of the number of segment wordlines. Other embodiments may be disclosed.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: Power management of an embedded dynamic random access memory (eDRAM) using collected performance counter statistics to generating a set of one or more eDRAM effectiveness predictions. Using a set of one or more eDRAM effectiveness thresholds, each corresponding to one of the set of eDRAM effectiveness predictions, to determine whether at least one eDRAM effectiveness prediction has crossed over threshold. In the case that at least one eDRAM effectiveness prediction has crossed over its threshold, transitioning the eDRAM to a new power state. Power management is achieved by transitioning to a power-off state or self-refresh state and reducing the amount of power consumed by the eDRAM as compared to a power-on state.

Abstract: A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array.

Abstract: Semiconductor modules are provided. The semiconductor module includes a first semiconductor chip configured for storing an information signal that is set in response to a command/address signal and which determines reception of an on-die termination (ODT) signal in a power down mode in response to the information signal to control activation of a first ODT circuit; and a second semiconductor chip configured for sharing and utilizing the first ODT circuit included in the first semiconductor chip.

Abstract: An approach for providing fine granularity power gating of a memory array is described. In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, wherein each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied a half-power voltage value, while the power supply lines of the remaining rows in the memory array are supplied a power-gated voltage value.

Abstract: Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory.

Abstract: A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor.

Abstract: A memory device includes memory cells, each of the memory cells having corresponding bit and word lines connected thereto for accessing the memory cells, a word line circuit coupled with at least one word line, and a bit line circuit coupled with at least one bit line. The memory device further includes at least one control circuit coupled with the bit and word line circuits. The control circuit is operative to cause state information to be stored in the memory cells. At least one switching element selectively connects the memory cells, the bit and word line circuits, and the control circuit to at least one power supply as a function of at least one control signal. The control circuit generates the control signal for disconnecting at least portions of the word line and bit line circuits from the power supply while state information is retained in the memory cells.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: Memory devices, connectors and methods for terminating an operation are provided, including a memory device configured to terminate an internal operation such as a programming or erase operation responsive to receiving a signal during removal of the memory device from a connector, such as a socket. The memory device may be configured to generate the removal signal, such as by including a dedicated removal terminal. The memory card may respond to the signal by terminating a programming or erase operation before power is lost. The removal terminal may have a dimension that is different from a dimension of a power terminal. Alternatively, the connector may be configured to generate a signal that causes a host to terminate programming or erase operations prior to memory card removal, such as by including a switch that is actuated when the memory device moves to a pre-power loss position.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.