Associative Memories (content Addressable Memory-cam) Patents (Class 365/49.1)
  • Patent number: 11404424
    Abstract: Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ping-Wei Wang, Jui-Lin Chen, Yu-Kuan Lin
  • Patent number: 11386946
    Abstract: Apparatuses and methods for tracking all row accesses in a memory device over time may be used to identify rows which are being hammered so that ‘victim’ rows may be identified and refreshed. A register stack may include a number of count values, each of which may track a number of accesses to a portion of the word lines of the memory device. Anytime a row within a given portion is accessed, the associated count value may be incremented. When a count value exceeds a first threshold, a second stack with a second number of count values may be used to track numbers of accesses to sub-portions of the given portion. When a second count value exceeds a second threshold, victim addresses may be provided to refresh the victim word lines associated with any of the word lines within the sub-portion.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: July 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sujeet Ayyapureddi, Donald M. Morgan
  • Patent number: 11366763
    Abstract: A controller, a memory system and an operating method thereof are disclosed. The controller controls a nonvolatile memory device and the nonvolatile memory includes a first memory module configured to store a plurality of pieces of map data read from the nonvolatile memory device; and a second memory module configured to cache map data having locality among map data received from the first memory module.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Do Hun Kim
  • Patent number: 11354237
    Abstract: A multiport memory in which one of the ports is analog rather than digital is described. In one embodiment, the analog port functions as a read-only port and the digital port functions as a write only port. This allows the data in the core memory to be applied to an analog signal, while retaining a digital port having access to the core memory for rapid storage of data. One potential use of such a multiport memory is as a bridge between a digital computer and an analog computer; for example, this allows a digitally programmed two-port memory to derive a sum-of-products signal from a plurality of analog input signals, and a plurality of such multiport memories to be used in an analog neural network such as a programmable neural net implementing analog artificial intelligence (AI).
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: June 7, 2022
    Assignee: SiliconIntervention Inc.
    Inventors: A. Martin Mallinson, Christian Leth Petersen
  • Patent number: 11334363
    Abstract: A matrix-multiplying-matrix operation method and a processing device for performing the same are provided. The matrix-multiplying-matrix method includes distributing, by a main processing circuit, basic data blocks of one matrix and broadcasting the other matrix to a plurality of the basic processing circuits. That way, the basic processing circuits can perform inner-product operations between the basic data blocks and the broadcasted matrix in parallel. The results are then provided back to main processing circuit for combining. The technical solutions proposed by the present disclosure provide short operation time and low energy consumption.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: May 17, 2022
    Assignee: CAMBRICON TECHNOLOGIES CORPORATION LIMITED
    Inventors: Shaoli Liu, Tianshi Chen, Bingrui Wang, Yao Zhang
  • Patent number: 11309029
    Abstract: A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventors: Han Soo Joo, Bong Yeol Park, Ji Hyun Seo, Hee Youl Lee
  • Patent number: 11262913
    Abstract: Technologies for stochastic associative search operations in memory (e.g., a three-dimensional cross-point memory) using error correction codes include a compute device. The compute device has a memory including a matrix that stores individually addressable bit data and is formed by rows and columns. The compute device receives a request to retrieve a subset of the bit data stored in the matrix. The compute device identifies, based on a search performed on the columns in the matrix, one or more candidate data sets. Each candidate data set corresponds to one of the rows in the matrix. The compute device performs an error correction operation on the identified one or more candidate data sets to determine whether the identified one or more candidate data sets is an exact match with the subset of the bit data.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Richard Coulson
  • Patent number: 11133065
    Abstract: A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a representation of the input search word and a representation of an inverse of the input search word. The search pattern is provided as input to search lines of a ternary content-addressable memory (TCAM) block. A subset of the search lines is set to a logical high state based on a first portion of the input search word being designated as don't-care bits. The search pattern causes at least one string in the CAM block to be conductive and provide a signal in response to a data entry stored on the string comprising a second portion of the input search word that excludes the don't-care bits. A location of the data entry is determined and output.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Manik Advani, Tomoko Ogura Iwasaki
  • Patent number: 11106596
    Abstract: Methods, devices, and systems for determining an address in a physical memory which corresponds to a virtual address using a skewed-associative translation lookaside buffer (TLB) are described. A virtual address and a configuration indication are received using receiver circuitry. A physical address corresponding to the virtual address is output if a TLB hit occurs. A first subset of a plurality of ways of the TLB is configured to hold a first page size. The first subset includes a number of the ways based on the configuration indication. A physical address corresponding to the virtual address is retrieved from a page table if a TLB miss occurs, and at least a portion of the physical address is installed in a least recently used way of a subset of a plurality of ways the TLB, determined according to a replacement policy based on the configuration indication.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: August 31, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John M. King, Michael T. Clark
  • Patent number: 11048758
    Abstract: A system for storing and looking up values via hash table is disclosed. The system comprises multiple hash tables, each hash table being associated with a different hashing function and a content addressable memory (CAM). One or more processors receive a request to store a value; generate hashes of the value via each of the hashing functions; determine whether there exists at least one hash table that has a vacancy for the value; and if the determination is positive, insert the value in one of the at least one hash tables having the vacancy, and if the determination is negative, insert the value in the CAM. The processors also receive a request to look up a value; determine whether any of the hash tables or the CAM contain the value; and return the determination of whether the any of the plurality of hash tables or the CAM contain the value.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: June 29, 2021
    Assignee: Morgan Stanley Services Group Inc.
    Inventors: Changhoan Kim, Sunghyun Park
  • Patent number: 11037617
    Abstract: A method of operating a memory device is provided, comprising determining a number of operations corresponding to a memory location during a first timing period; and scheduling an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold. A memory device is provided, comprising a memory including a memory location; and circuitry configured to: determine a number of operations corresponding to the memory location during a first timing period; and schedule an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Patent number: 11024375
    Abstract: According to one embodiment, there is provided a semiconductor storage device including N word lines, M bit lines, multiple memory cells, and a read circuit. N is an integer of four or greater. M is an integer of two or greater. The M bit lines intersect with the word lines. The multiple memory cells are placed at positions where the word lines and the bit lines intersect. The memory cell stores binary data. The read circuit is connected to the M bit lines. The read circuit is able to detect levels of a multi-ary signal.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Takeshi Sugimoto
  • Patent number: 10950288
    Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Bill Nale, Christopher E. Cox
  • Patent number: 10916277
    Abstract: A memory device includes a memory cell array including a plurality of memory blocks and a storage block storing a plurality of pieces of option parameter information; a parameter determining circuit outputting a parameter information signal by measuring a skew of the memory device; a peripheral circuit performing a read operation on the storage block; and a control logic controlling the peripheral circuit to perform the read operation on a selected piece of option parameter information, among the plurality of pieces of option parameter information, in response to the parameter information signal, and setting an option parameter according to the selected piece of option parameter information.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: February 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Sang Oh Lim
  • Patent number: 10910055
    Abstract: The present invention provides a semiconductor device that can reduce the power consumption, including: a plurality of search memory cells arranged in a matrix; a plurality of match lines provided corresponding to each memory cell row to determine match/mismatch between data stored in the search memory cell and search data; a plurality of match line retention circuits provided corresponding to each of the match lines; a storage unit for storing information relating to the state of each of the match lines; and a selection circuit for selectively activating the match line retention circuits based on the information stored in the storage unit.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: February 2, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Futoshi Igaue
  • Patent number: 10877836
    Abstract: A fault tolerant data processing network includes a number of nodes intercoupled through an interconnect circuit. The micro-architectures of the nodes are configured for sending and receiving messages via the interconnect circuit. In operation, a first Request Node sends a read request to a Home Node. In response, the Home Node initiates transmission of the requested data to the first Request Node. When the first Request Node detects that a fault has occurred, it sends a negative-acknowledgement message to the first Home Node. In response, the Home Node again initiates transmission of the requested data to the first Request Node. The requested data may be transmitted from a local cache of a second Request Node or transmitted by a Slave Node after being retrieved from a memory. The data may be transmitted to the first Request Node via the Home Node or directly via the interconnect.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: December 29, 2020
    Assignee: Arm Limited
    Inventors: Zheng Xu, Jamshed Jalal
  • Patent number: 10866897
    Abstract: A method of storing data in a memory module including an in-module prefetcher, an in-module prefetch buffer, memory, and a memory controller, the method including sending address information from the in-module prefetcher to the memory controller and to the prefetch buffer, determining prefetch accuracy based on a comparison of the address information sent to the memory controller and the address information sent to the prefetch buffer, determining a prefetch mode based on the prefetch accuracy, and storing the data in the memory based on the prefetch mode.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mu-Tien Chang, Dimin Niu, Dongyan Jiang, Hongzhong Zheng
  • Patent number: 10852972
    Abstract: There is provided a retrieval memory that can easily manage address information. A retrieval memory which retrieves whether or not inputted retrieval data matches entry data stored in a memory cell array and outputs address information corresponding to matched entry data includes a plurality of retrieval blocks and an output control unit for outputting the address information. The address information includes a block address for specifying at least one of the retrieval blocks and a logical address corresponding to entry data in the specified retrieval block. The output control unit outputs address information that is reset so that the address information corresponding to the entry data becomes continuous in an address space based on a size of the entry data.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: December 1, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takeo Miki
  • Patent number: 10825521
    Abstract: To use larger capacity TCAMs while avoiding various packaging and power management issues of TCAMs, pre-processing can be performed on TCAM lookup requests to intelligently pipeline lookup requests according to a defined power budget that is based on TCAM and power supply specifications. Dividing lookup requests based on a power budget smooths the instantaneous current demand and dynamic power demand. This intelligent pre-processing of lookup requests allows lookup requests that satisfy a power budget based threshold to still complete within a single clock cycle while nominally reducing performance for those lookup requests that would not satisfy the power budget based threshold. When a lookup request will not satisfy the power budget based threshold, the lookup request is split into searches targeting different memory blocks of the TCAM.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 3, 2020
    Assignee: PALO ALTO NETWORKS, INC.
    Inventors: De Bao Vu, Matthew Robert Rohm, Subramani Ganesh, Savitha Raghunath, William Alan Roberson
  • Patent number: 10759384
    Abstract: The disclosure relates to pattern detection unit and associated method. The unit comprises a shift register configured to over-sample a multi-bit input signal such that each bit of the input signal is represented by a plurality of samples in the shift register; and a correlator configured to compare a target pattern with two or more sample-sets, each sample-set comprising a corresponding sample from each of the plurality of samples of each bit, and classify each compared sample-set as one of: an exact match; an inexact match; or a non-match to the target pattern in order to determine whether or not the input signal matches the target pattern.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 1, 2020
    Assignee: NXP B.V.
    Inventors: Stylianos Perissakis, Martin Posch
  • Patent number: 10763267
    Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with a two-bitcell layout and a four cell poly pitch. The two-bitcell layout includes a first bitcell and a second bitcell with structural contours that are joined together in a coupling arrangement. The first bitcell and the second bitcell have multiple transistors that are arranged to store data during write operations and allow access of data during read operations.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: September 1, 2020
    Assignee: Arm Limited
    Inventors: Yew Keong Chong, Sriram Thyagarajan, Munish Kumar
  • Patent number: 10748607
    Abstract: A non-volatile memory device includes a memory cell array, a Y decoder, a program register, a sense amplifier, a verification circuit and a path control circuit. The memory cell array includes a first memory cell. The first memory cell is connected with a bit line. The Y decoder includes a first decoding element. The first decoding element is connected between the bit line and a data line. The program register is connected with the data line, and generates a control voltage to the first memory cell. The sense amplifier is connected with the data line, and generates a read data. The verification circuit is connected between the sense amplifier and the data line, and generates a rewrite data. The path control circuit is connected with the data line, and receives a write data and the rewrite data.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 18, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Yu-Shan Chien
  • Patent number: 10725887
    Abstract: A method for operating a monitoring entity (ME) for a distributed system includes receiving, by the ME, an action message from a computing device which has information about an action it performed. The ME, generates, deletes and/or updates a node of a data structure stored in a memory of the ME to provide an updated state of the data structure, by: processing the information of the received message, and storing the processed information into the data structure. The data structure represents knowledge about behavior of the distributed system. Each node specifies a policy by a formula, a node is linked by a trigger to one other node only to specify dependencies between nodes except for nodes with a formula, monitored by the ME, and nodes with a same formula are mutually linked by triggers. Verdict information indicating an action violating a policy is computed based on the updated state.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: July 28, 2020
    Assignee: NEC CORPORATION
    Inventor: Felix Klaedtke
  • Patent number: 10672445
    Abstract: A memory device can include a plurality of memory banks coupled to an input/output bus and a memory controller coupled to the plurality of memory banks. The memory controller can be configured to control operations of the plurality of memory banks, where each of the plurality of memory banks can include a bank array including a plurality of memory cells configured to store data, a latch circuit coupled to the input/output bus, where the latch circuit can be configured to store target data received via the input/output bus to provide stored target data, and a comparison circuit coupled to the latch circuit, where the comparison circuit can be configured to compare stored data output by the bank array with the stored target data to provide result data to the memory controller.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong Il O, Jun Hyung Kim, Kyo Min Sohn
  • Patent number: 10614250
    Abstract: The present disclosure relates to systems and methods for information security, specifically for automatically detecting theft of personal data. In one implementation, a computer-implemented method for automatically detecting theft of personal data on the Internet may include at least one processor configured to execute instructions, the instructions including receiving from a user, an electronic communication containing a first search term, extracting via pattern recognition one or more patterns corresponding with the first search term, and comparing the one or more patterns with a subset of data scraped from the Internet, with the subset of data scraped from the Internet being indexed by pattern for the first search term. The instructions may also include flagging matches of the one or more patterns with the subset of data based on the comparison and transmitting information associated with the matches in a report that indicates a possible theft of personal data.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: April 7, 2020
    Assignee: GROUPSENSE, INC.
    Inventors: Thomas Stephen Richards, Collin Cameron Meadows, Kyle Allen Gochenour
  • Patent number: 10586594
    Abstract: Examples disclosed herein relate, in one aspect, to an electronic device including a processor, a lookup engine, and a content addressable memory (CAM) including a plurality of data tables. The lookup engine may obtain from the processor a search word and a table identifier identifying a selected data table from the plurality of data tables, and using a lookup table, determine table parameters associated with the selected data table. The lookup engine may also generate search parameters based on the search word and the table parameters and provide the search parameters to the CAM. The search parameters may cause the CAM to determine whether the selected data table comprises a word corresponding to the search word, and if the selected data table comprises the word, to output an entry address of an entry of the CAM that comprises the word.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: March 10, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: John A. Wickeraad
  • Patent number: 10572440
    Abstract: Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 25, 2020
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Tejinder Kumar, Rathod Ronak Kishorbhai, Apurva Sen, Rakesh Malik
  • Patent number: 10528488
    Abstract: A method for efficient name coding in a storage system is provided. The method includes identifying common prefixes, common suffixes, and midsections of a plurality of strings in the storage system, and writing the common prefixes, midsections and common suffixes to a string table in the storage system. The method includes encoding each string of the plurality of strings as to position in the string table of prefix, midsection and suffix of the string, and writing the encoding of each string to memory in the storage system for the plurality of strings, in the storage system.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: January 7, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Robert Lee, Cary A. Sandvig
  • Patent number: 10521118
    Abstract: A method for write aggregation using a host memory buffer includes fetching write commands and data specified by the write commands from a host over a bus to a non-volatile memory system coupled to the host. Writing the data specified by the write commands from the non-volatile memory system over the bus to the host. The method further includes aggregating the data specified by the write commands in a host memory buffer maintained in memory of the host. The method further includes determining whether the data in the host memory buffer has aggregated to a threshold amount. The method further includes, in response to determining that the data has aggregated to the threshold amount, reading the data from the host memory buffer to the non-volatile memory system and writing the data to non-volatile memory in the non-volatile memory system.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: December 31, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shay Benisty, Tal Sharifie
  • Patent number: 10504595
    Abstract: To use larger capacity TCAMs while avoiding various packaging and power management issues of TCAMs, pre-processing can be performed on TCAM lookup requests to intelligently pipeline lookup requests according to a defined power budget that is based on TCAM and power supply specifications. Dividing lookup requests based on a power budget smooths the instantaneous current demand and dynamic power demand. This intelligent pre-processing of lookup requests allows lookup requests that satisfy a power budget based threshold to still complete within a single clock cycle while nominally reducing performance for those lookup requests that would not satisfy the power budget based threshold. When a lookup request will not satisfy the power budget based threshold, the lookup request is split into searches targeting different memory blocks of the TCAM.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: December 10, 2019
    Assignee: Palo Alto Networks, Inc.
    Inventors: De Bao Vu, Matthew Robert Rohm, Subramani Ganesh, Savitha Raghunath, William Alan Roberson
  • Patent number: 10438659
    Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Balaji Srinivasan, Daniel Chu, Lark-Hoon Leem, John Gorman, Mase Taub, Sandeep Guliani, Kiran Pangal
  • Patent number: 10430181
    Abstract: Systems and methods are provided for updating expansion read-only memory (ROM) code to execute for device-specific initialization. An exemplary method comprises first accessing one or more copies of a ROM code in at least one of a plurality of repositories. The ROM code can be configured to execute an initialization process for a specific device in the computer system. The method can then select one of the one or more copies of the ROM code based on a selection criterion to yield a selected ROM code. The method can then copy the selected ROM code to a system memory of the computer system. The method can then execute the selected ROM code in the system memory to initialize the specific device.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: October 1, 2019
    Assignee: QUANTA COMPUTER INC.
    Inventor: Mei-Lin Su
  • Patent number: 10403357
    Abstract: An integrated circuit includes an array of resistive non-volatile memory cells having a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The integrated circuit includes a sense amplifier coupled to a first bit line of the plurality of bit lines and a corresponding first source line of the plurality of source lines. When a memory cell coupled to the first bit line is selected for a read operation, the sense amplifier is configured to, during a calibration phase of the read operation, store a first voltage representative of a leakage current on the first source line. The sense amplifier is also configured to, during a sense phase of the read operation, apply the stored first voltage to the first bit line and provide a first sense amplifier output indicative of a logic state of the selected memory cell.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: September 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Anirban Roy, Perry Pelley
  • Patent number: 10397263
    Abstract: A method comprising receiving, by a network element, a data packet, searching, by the network element, the received data packet at a first hierarchical level to determine whether a substring of a string of a regular expression exists in the received data packet, searching, by the network element when the search of the received data packet at the first hierarchical level finds a match, the received data packet at a second hierarchical level to determine whether the string of the regular expression exists in the received data packet, and transmitting, by the network element, the received data packet to a next network element along an original path of the received data packet without searching the received data packet at a third hierarchical level when the search of the received data packet at the first or second hierarchical level does not find a match.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: August 27, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Yan Sun, Wei Xu
  • Patent number: 10394742
    Abstract: A method for determining a type of a device connected to an inter-integrated circuit (I2C) includes steps of: a) transmitting requests to bus addresses of the I2C, respectively; b) upon receipt of a response message transmitted by a device in response to receipt of one of the requests from one of the bus addresses, determining that the device is connected to said one of the bus addresses; and c) according to a lookup table that includes plural of entries, each of which has a corresponding device type and respective address set consisting of at least one reference address conforming with one of the bus addresses, determining a type of the device as one of the device types in the lookup table with reference to said one of the bus addresses.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: August 27, 2019
    Assignee: Mitac Computing Technology Corporation
    Inventor: Chi-Yuan Yen
  • Patent number: 10374954
    Abstract: The disclosed apparatus may include a processing unit that (1) identifies an initial forwarding key that corresponds to a forwarding feature of a network device, (2) identifies an initial hash value that represents the initial forwarding key and is derived from the initial forwarding key, (3) identifies an additional forwarding key that corresponds to the forwarding feature of the network device, (4) determines that the initial forwarding key and the additional forwarding key exceed a threshold level of similarity relative to one another, (5) derives an additional hash value that represents the additional forwarding key by applying the initial forwarding key and the initial hash value as inputs to a hash function, and then (6) implements the additional hash value in connection with the forwarding feature of the network device and the forwarding information stored in the storage device. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: August 6, 2019
    Assignee: Juniper Networks, Inc
    Inventor: Meher Aditya Kumar Addepalli
  • Patent number: 10318588
    Abstract: In one embodiment, a content-addressable memory has multiple blocks of content-addressable memory entries, including different first and second sets of content-addressable memory blocks. One embodiment determines the first set of content-addressable memory blocks based on a content-addressable memory profile identifier and a search key and then performs a first content-addressable memory lookup operation in each of the first set of content-addressable memory blocks, but not in the second set of content-addressable memory blocks, based on the search key. If at least one entry is match, a corresponding result is identified. Otherwise, in one embodiment, the second set of content-addressable memory blocks is determined based on the content-addressable memory profile identifier but not based on the search key, and a search is made therein to identify a matching result or that no match was determined. In one embodiment, a matching result determines how a packet is processed.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: June 11, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Doron Shoham, Sivan Avraham, Aravinth Nagamani Manickam
  • Patent number: 10297318
    Abstract: A method for readout of a gated memristor array, a memristor array readout circuit and method of fabrication thereof are provided. In the context of the method, the method includes selecting a row of a memristor array associated with a desired cell, measuring the value of the selected memristor row, and selecting a column of a memristor array associated with the desired cell. The selection of the column and selection of the row selects the desired cell. The method also includes measuring the value of the memristor selected row with the selected desired cell and determining the value of the desired cell based on the value of the selected memristor row and the value of the selected memristor row with the selected desired cell.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: May 21, 2019
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Mohammed Affan Zidan, Hesham Omran, Ahmed Sultan Salem, Khaled Nabil Salama
  • Patent number: 10282436
    Abstract: A method of searching for data stored in a memory, the method including receiving a regex search request, generating a parse tree including fundamental regex operations corresponding to the regex search request, individually analyzing each of the fundamental regex operations of the generated parse tree in a respective time-step, determining a memory address location of data corresponding to the analyzed fundamental regex operations by using a translation table to determine whether the data exists, and using a reverse translation table to determine the memory address location of the data, and outputting data matching the regex search request after analyzing all of the fundamental regex operations of the generated parse tree.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: May 7, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Krishna T. Malladi, Hongzhong Zheng
  • Patent number: 10216720
    Abstract: Comparators may be associated with dictionary entries. In one aspect, a dictionary entry may store a dictionary word. A register may store an input word. A comparator associated with the dictionary entry may compare the dictionary word and the input word. The comparison may be a bit by bit comparison. The comparator may output a signal indicating if the dictionary word is less than the input word, equal to the input word, or greater than the input word. The output may indicate indeterminate when the comparison is not yet complete.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: February 26, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent Buchanan, Le Zheng, John Paul Strachan
  • Patent number: 10203892
    Abstract: A semiconductor device that includes a memory system is configured to accept input of search data and to search in parallel respective rows of a memory cell array such as a CAM and so forth for data held in a memory. The memory system detects whether an inflow amount of the search data that is input is at least a fixed amount by monitoring a packing ratio of an FIFO buffer that a search command is held. The memory system controls a speed of search processing by dividing the memory cell array into blocks and setting each block as a search processing object in accordance with a result of detection.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: February 12, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takeo Miki
  • Patent number: 10203955
    Abstract: Instructions and logic provide SIMD vector packed tuple cross-comparison functionality. Some processor embodiments include first and second registers with a variable plurality of data fields, each of the data fields to store an element of a first data type. The processor executes a SIMD instruction for vector packed tuple cross-comparison in some embodiments, which for each data field of a portion of data fields in a tuple of the first register, compares its corresponding element with every element of a corresponding portion of data fields in a tuple of the second register and sets a mask bit corresponding to each element of the second register portion, in a bit-mask corresponding to each unmasked element of the corresponding first register portion, according to the corresponding comparison. In some embodiments bit-masks are shifted by corresponding elements in data fields of a third register. The comparison type is indicated by an immediate operand.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Robert Valentine, Christopher J. Hughes, Mark J. Charney, Zeev Sperber, Amit Gradstein, Simon Rubanovich, Elmoustapha Ould-Ahmed-Vall, Yuri Gebil
  • Patent number: 10176099
    Abstract: An apparatus includes a cache controller, the cache controller to receive, from a requestor, a memory access request referencing a memory address of a memory. The cache controller may identify a cache entry associated with the memory address, and responsive to determining that a first data item stored in the cache entry matches a data pattern indicating cache entry invalidity, read a second data item from a memory location identified by the memory address. The cache controller may then return, to the requestor, a response comprising the second data item.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Jayesh Gaur, Supratik Majumder, Zvika Greenfield, Israel Diamand
  • Patent number: 10169278
    Abstract: One aspect of the invention relates to a network node for connecting to a Local Interconnect Network (LIN). In accordance with one example of the present invention, the network node includes a bus terminal which is operably coupled to a data line for receiving a data signal, which represents serial data, via that data line. The data signal is a binary signal having high and low signal levels. The network node further includes a receiver circuit which employs a comparator to compare the data signal with a reference signal. The comparator generates a binary output signal representing the result of the comparison. The network node also includes a measurement circuit that receives the data signal and provides a first voltage signal such that it represents the high signal level of the data signal.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: January 1, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Alexander Mori, Christoph Seidl
  • Patent number: 10141055
    Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: November 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Vishal Sarin
  • Patent number: 10133676
    Abstract: Embodiments related to a cache memory that supports tagless addressing are disclosed. Some embodiments receive a request to perform a memory access, wherein the request includes a virtual address. In response, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: November 20, 2018
    Assignee: Rambus Inc.
    Inventors: Hongzhong Zheng, Trung A. Diep
  • Patent number: 10043578
    Abstract: A sense amplifier circuit includes a single-ended sense amplifier and an isolation switch. The isolation switch is coupled between a bias node and a first line of a memory device, receives an output of the single-ended sense amplifier and selectively isolates the bias node and the first line in response to the output of the single-ended sense amplifier. The first line is coupled to a plurality of memory cells of the memory device.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: August 7, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shu-Lin Lai, Shu-Hsuan Lin, Shih-Huang Huang
  • Patent number: 10042764
    Abstract: A method for processing commands in a directory-based computer memory management system includes receiving a command to perform an operation on data stored in a set of one or more computer memory locations associated with an entry in a directory of a computer memory, the entry is associated with an indicator for indicating whether the set of one or more computer memory locations is busy, a head tag, and a tail tag. The command is associated with a command tag and a predecessor tag, and checking the indicator to determine whether the set of one or more computer memory locations is busy.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Bar-Joshua, Yiftach Benjamini, Yaakov Gendel, Eyal Gonen, Alexander Mesh
  • Patent number: 10037283
    Abstract: Techniques for improving translation lookaside buffer (TLB) operation are disclosed. A particular entry of the TLB is to be updated with data associated with a large page size. The TLB updates replacement policy data for that TLB entry for that large page size to indicate that the TLB entry is not the least-recently-used. To prevent smaller pages from evicting the TLB entry for the large page size, the TLB also updates replacement policy data for that TLB entry for the smaller page size to indicate that the TLB entry is not the least-recently-used.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: July 31, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony J. Bybell, John M. King
  • Patent number: 10007572
    Abstract: A method of operating a memory system includes receiving information data corresponding to a second program unit that is a part of a first program unit and a write request for the information data from a host; generating a codeword by performing error correction code (ECC) encoding on the received information data such that a partial parity bit corresponding to the information data among all parity bits of the codeword is updated; and providing a memory device with the generated codeword and a write command regarding the codeword.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Min Shin, Jun-Jin Kong, Beom-Kyu Shin, Eun-Chu Oh, Pil-Sang Yoon