Associative Memories (content Addressable Memory-cam) Patents (Class 365/49.1)
  • Patent number: 11024375
    Abstract: According to one embodiment, there is provided a semiconductor storage device including N word lines, M bit lines, multiple memory cells, and a read circuit. N is an integer of four or greater. M is an integer of two or greater. The M bit lines intersect with the word lines. The multiple memory cells are placed at positions where the word lines and the bit lines intersect. The memory cell stores binary data. The read circuit is connected to the M bit lines. The read circuit is able to detect levels of a multi-ary signal.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Takeshi Sugimoto
  • Patent number: 10950288
    Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Bill Nale, Christopher E. Cox
  • Patent number: 10916277
    Abstract: A memory device includes a memory cell array including a plurality of memory blocks and a storage block storing a plurality of pieces of option parameter information; a parameter determining circuit outputting a parameter information signal by measuring a skew of the memory device; a peripheral circuit performing a read operation on the storage block; and a control logic controlling the peripheral circuit to perform the read operation on a selected piece of option parameter information, among the plurality of pieces of option parameter information, in response to the parameter information signal, and setting an option parameter according to the selected piece of option parameter information.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: February 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Sang Oh Lim
  • Patent number: 10910055
    Abstract: The present invention provides a semiconductor device that can reduce the power consumption, including: a plurality of search memory cells arranged in a matrix; a plurality of match lines provided corresponding to each memory cell row to determine match/mismatch between data stored in the search memory cell and search data; a plurality of match line retention circuits provided corresponding to each of the match lines; a storage unit for storing information relating to the state of each of the match lines; and a selection circuit for selectively activating the match line retention circuits based on the information stored in the storage unit.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: February 2, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Futoshi Igaue
  • Patent number: 10877836
    Abstract: A fault tolerant data processing network includes a number of nodes intercoupled through an interconnect circuit. The micro-architectures of the nodes are configured for sending and receiving messages via the interconnect circuit. In operation, a first Request Node sends a read request to a Home Node. In response, the Home Node initiates transmission of the requested data to the first Request Node. When the first Request Node detects that a fault has occurred, it sends a negative-acknowledgement message to the first Home Node. In response, the Home Node again initiates transmission of the requested data to the first Request Node. The requested data may be transmitted from a local cache of a second Request Node or transmitted by a Slave Node after being retrieved from a memory. The data may be transmitted to the first Request Node via the Home Node or directly via the interconnect.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: December 29, 2020
    Assignee: Arm Limited
    Inventors: Zheng Xu, Jamshed Jalal
  • Patent number: 10866897
    Abstract: A method of storing data in a memory module including an in-module prefetcher, an in-module prefetch buffer, memory, and a memory controller, the method including sending address information from the in-module prefetcher to the memory controller and to the prefetch buffer, determining prefetch accuracy based on a comparison of the address information sent to the memory controller and the address information sent to the prefetch buffer, determining a prefetch mode based on the prefetch accuracy, and storing the data in the memory based on the prefetch mode.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mu-Tien Chang, Dimin Niu, Dongyan Jiang, Hongzhong Zheng
  • Patent number: 10852972
    Abstract: There is provided a retrieval memory that can easily manage address information. A retrieval memory which retrieves whether or not inputted retrieval data matches entry data stored in a memory cell array and outputs address information corresponding to matched entry data includes a plurality of retrieval blocks and an output control unit for outputting the address information. The address information includes a block address for specifying at least one of the retrieval blocks and a logical address corresponding to entry data in the specified retrieval block. The output control unit outputs address information that is reset so that the address information corresponding to the entry data becomes continuous in an address space based on a size of the entry data.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: December 1, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takeo Miki
  • Patent number: 10825521
    Abstract: To use larger capacity TCAMs while avoiding various packaging and power management issues of TCAMs, pre-processing can be performed on TCAM lookup requests to intelligently pipeline lookup requests according to a defined power budget that is based on TCAM and power supply specifications. Dividing lookup requests based on a power budget smooths the instantaneous current demand and dynamic power demand. This intelligent pre-processing of lookup requests allows lookup requests that satisfy a power budget based threshold to still complete within a single clock cycle while nominally reducing performance for those lookup requests that would not satisfy the power budget based threshold. When a lookup request will not satisfy the power budget based threshold, the lookup request is split into searches targeting different memory blocks of the TCAM.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 3, 2020
    Assignee: PALO ALTO NETWORKS, INC.
    Inventors: De Bao Vu, Matthew Robert Rohm, Subramani Ganesh, Savitha Raghunath, William Alan Roberson
  • Patent number: 10759384
    Abstract: The disclosure relates to pattern detection unit and associated method. The unit comprises a shift register configured to over-sample a multi-bit input signal such that each bit of the input signal is represented by a plurality of samples in the shift register; and a correlator configured to compare a target pattern with two or more sample-sets, each sample-set comprising a corresponding sample from each of the plurality of samples of each bit, and classify each compared sample-set as one of: an exact match; an inexact match; or a non-match to the target pattern in order to determine whether or not the input signal matches the target pattern.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 1, 2020
    Assignee: NXP B.V.
    Inventors: Stylianos Perissakis, Martin Posch
  • Patent number: 10763267
    Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with a two-bitcell layout and a four cell poly pitch. The two-bitcell layout includes a first bitcell and a second bitcell with structural contours that are joined together in a coupling arrangement. The first bitcell and the second bitcell have multiple transistors that are arranged to store data during write operations and allow access of data during read operations.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: September 1, 2020
    Assignee: Arm Limited
    Inventors: Yew Keong Chong, Sriram Thyagarajan, Munish Kumar
  • Patent number: 10748607
    Abstract: A non-volatile memory device includes a memory cell array, a Y decoder, a program register, a sense amplifier, a verification circuit and a path control circuit. The memory cell array includes a first memory cell. The first memory cell is connected with a bit line. The Y decoder includes a first decoding element. The first decoding element is connected between the bit line and a data line. The program register is connected with the data line, and generates a control voltage to the first memory cell. The sense amplifier is connected with the data line, and generates a read data. The verification circuit is connected between the sense amplifier and the data line, and generates a rewrite data. The path control circuit is connected with the data line, and receives a write data and the rewrite data.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 18, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Yu-Shan Chien
  • Patent number: 10725887
    Abstract: A method for operating a monitoring entity (ME) for a distributed system includes receiving, by the ME, an action message from a computing device which has information about an action it performed. The ME, generates, deletes and/or updates a node of a data structure stored in a memory of the ME to provide an updated state of the data structure, by: processing the information of the received message, and storing the processed information into the data structure. The data structure represents knowledge about behavior of the distributed system. Each node specifies a policy by a formula, a node is linked by a trigger to one other node only to specify dependencies between nodes except for nodes with a formula, monitored by the ME, and nodes with a same formula are mutually linked by triggers. Verdict information indicating an action violating a policy is computed based on the updated state.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: July 28, 2020
    Assignee: NEC CORPORATION
    Inventor: Felix Klaedtke
  • Patent number: 10672445
    Abstract: A memory device can include a plurality of memory banks coupled to an input/output bus and a memory controller coupled to the plurality of memory banks. The memory controller can be configured to control operations of the plurality of memory banks, where each of the plurality of memory banks can include a bank array including a plurality of memory cells configured to store data, a latch circuit coupled to the input/output bus, where the latch circuit can be configured to store target data received via the input/output bus to provide stored target data, and a comparison circuit coupled to the latch circuit, where the comparison circuit can be configured to compare stored data output by the bank array with the stored target data to provide result data to the memory controller.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong Il O, Jun Hyung Kim, Kyo Min Sohn
  • Patent number: 10614250
    Abstract: The present disclosure relates to systems and methods for information security, specifically for automatically detecting theft of personal data. In one implementation, a computer-implemented method for automatically detecting theft of personal data on the Internet may include at least one processor configured to execute instructions, the instructions including receiving from a user, an electronic communication containing a first search term, extracting via pattern recognition one or more patterns corresponding with the first search term, and comparing the one or more patterns with a subset of data scraped from the Internet, with the subset of data scraped from the Internet being indexed by pattern for the first search term. The instructions may also include flagging matches of the one or more patterns with the subset of data based on the comparison and transmitting information associated with the matches in a report that indicates a possible theft of personal data.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: April 7, 2020
    Assignee: GROUPSENSE, INC.
    Inventors: Thomas Stephen Richards, Collin Cameron Meadows, Kyle Allen Gochenour
  • Patent number: 10586594
    Abstract: Examples disclosed herein relate, in one aspect, to an electronic device including a processor, a lookup engine, and a content addressable memory (CAM) including a plurality of data tables. The lookup engine may obtain from the processor a search word and a table identifier identifying a selected data table from the plurality of data tables, and using a lookup table, determine table parameters associated with the selected data table. The lookup engine may also generate search parameters based on the search word and the table parameters and provide the search parameters to the CAM. The search parameters may cause the CAM to determine whether the selected data table comprises a word corresponding to the search word, and if the selected data table comprises the word, to output an entry address of an entry of the CAM that comprises the word.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: March 10, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: John A. Wickeraad
  • Patent number: 10572440
    Abstract: Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 25, 2020
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Tejinder Kumar, Rathod Ronak Kishorbhai, Apurva Sen, Rakesh Malik
  • Patent number: 10528488
    Abstract: A method for efficient name coding in a storage system is provided. The method includes identifying common prefixes, common suffixes, and midsections of a plurality of strings in the storage system, and writing the common prefixes, midsections and common suffixes to a string table in the storage system. The method includes encoding each string of the plurality of strings as to position in the string table of prefix, midsection and suffix of the string, and writing the encoding of each string to memory in the storage system for the plurality of strings, in the storage system.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: January 7, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Robert Lee, Cary A. Sandvig
  • Patent number: 10521118
    Abstract: A method for write aggregation using a host memory buffer includes fetching write commands and data specified by the write commands from a host over a bus to a non-volatile memory system coupled to the host. Writing the data specified by the write commands from the non-volatile memory system over the bus to the host. The method further includes aggregating the data specified by the write commands in a host memory buffer maintained in memory of the host. The method further includes determining whether the data in the host memory buffer has aggregated to a threshold amount. The method further includes, in response to determining that the data has aggregated to the threshold amount, reading the data from the host memory buffer to the non-volatile memory system and writing the data to non-volatile memory in the non-volatile memory system.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: December 31, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shay Benisty, Tal Sharifie
  • Patent number: 10504595
    Abstract: To use larger capacity TCAMs while avoiding various packaging and power management issues of TCAMs, pre-processing can be performed on TCAM lookup requests to intelligently pipeline lookup requests according to a defined power budget that is based on TCAM and power supply specifications. Dividing lookup requests based on a power budget smooths the instantaneous current demand and dynamic power demand. This intelligent pre-processing of lookup requests allows lookup requests that satisfy a power budget based threshold to still complete within a single clock cycle while nominally reducing performance for those lookup requests that would not satisfy the power budget based threshold. When a lookup request will not satisfy the power budget based threshold, the lookup request is split into searches targeting different memory blocks of the TCAM.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: December 10, 2019
    Assignee: Palo Alto Networks, Inc.
    Inventors: De Bao Vu, Matthew Robert Rohm, Subramani Ganesh, Savitha Raghunath, William Alan Roberson
  • Patent number: 10438659
    Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Balaji Srinivasan, Daniel Chu, Lark-Hoon Leem, John Gorman, Mase Taub, Sandeep Guliani, Kiran Pangal
  • Patent number: 10430181
    Abstract: Systems and methods are provided for updating expansion read-only memory (ROM) code to execute for device-specific initialization. An exemplary method comprises first accessing one or more copies of a ROM code in at least one of a plurality of repositories. The ROM code can be configured to execute an initialization process for a specific device in the computer system. The method can then select one of the one or more copies of the ROM code based on a selection criterion to yield a selected ROM code. The method can then copy the selected ROM code to a system memory of the computer system. The method can then execute the selected ROM code in the system memory to initialize the specific device.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: October 1, 2019
    Assignee: QUANTA COMPUTER INC.
    Inventor: Mei-Lin Su
  • Patent number: 10403357
    Abstract: An integrated circuit includes an array of resistive non-volatile memory cells having a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The integrated circuit includes a sense amplifier coupled to a first bit line of the plurality of bit lines and a corresponding first source line of the plurality of source lines. When a memory cell coupled to the first bit line is selected for a read operation, the sense amplifier is configured to, during a calibration phase of the read operation, store a first voltage representative of a leakage current on the first source line. The sense amplifier is also configured to, during a sense phase of the read operation, apply the stored first voltage to the first bit line and provide a first sense amplifier output indicative of a logic state of the selected memory cell.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: September 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Anirban Roy, Perry Pelley
  • Patent number: 10397263
    Abstract: A method comprising receiving, by a network element, a data packet, searching, by the network element, the received data packet at a first hierarchical level to determine whether a substring of a string of a regular expression exists in the received data packet, searching, by the network element when the search of the received data packet at the first hierarchical level finds a match, the received data packet at a second hierarchical level to determine whether the string of the regular expression exists in the received data packet, and transmitting, by the network element, the received data packet to a next network element along an original path of the received data packet without searching the received data packet at a third hierarchical level when the search of the received data packet at the first or second hierarchical level does not find a match.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: August 27, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Yan Sun, Wei Xu
  • Patent number: 10394742
    Abstract: A method for determining a type of a device connected to an inter-integrated circuit (I2C) includes steps of: a) transmitting requests to bus addresses of the I2C, respectively; b) upon receipt of a response message transmitted by a device in response to receipt of one of the requests from one of the bus addresses, determining that the device is connected to said one of the bus addresses; and c) according to a lookup table that includes plural of entries, each of which has a corresponding device type and respective address set consisting of at least one reference address conforming with one of the bus addresses, determining a type of the device as one of the device types in the lookup table with reference to said one of the bus addresses.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: August 27, 2019
    Assignee: Mitac Computing Technology Corporation
    Inventor: Chi-Yuan Yen
  • Patent number: 10374954
    Abstract: The disclosed apparatus may include a processing unit that (1) identifies an initial forwarding key that corresponds to a forwarding feature of a network device, (2) identifies an initial hash value that represents the initial forwarding key and is derived from the initial forwarding key, (3) identifies an additional forwarding key that corresponds to the forwarding feature of the network device, (4) determines that the initial forwarding key and the additional forwarding key exceed a threshold level of similarity relative to one another, (5) derives an additional hash value that represents the additional forwarding key by applying the initial forwarding key and the initial hash value as inputs to a hash function, and then (6) implements the additional hash value in connection with the forwarding feature of the network device and the forwarding information stored in the storage device. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: August 6, 2019
    Assignee: Juniper Networks, Inc
    Inventor: Meher Aditya Kumar Addepalli
  • Patent number: 10318588
    Abstract: In one embodiment, a content-addressable memory has multiple blocks of content-addressable memory entries, including different first and second sets of content-addressable memory blocks. One embodiment determines the first set of content-addressable memory blocks based on a content-addressable memory profile identifier and a search key and then performs a first content-addressable memory lookup operation in each of the first set of content-addressable memory blocks, but not in the second set of content-addressable memory blocks, based on the search key. If at least one entry is match, a corresponding result is identified. Otherwise, in one embodiment, the second set of content-addressable memory blocks is determined based on the content-addressable memory profile identifier but not based on the search key, and a search is made therein to identify a matching result or that no match was determined. In one embodiment, a matching result determines how a packet is processed.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: June 11, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Doron Shoham, Sivan Avraham, Aravinth Nagamani Manickam
  • Patent number: 10297318
    Abstract: A method for readout of a gated memristor array, a memristor array readout circuit and method of fabrication thereof are provided. In the context of the method, the method includes selecting a row of a memristor array associated with a desired cell, measuring the value of the selected memristor row, and selecting a column of a memristor array associated with the desired cell. The selection of the column and selection of the row selects the desired cell. The method also includes measuring the value of the memristor selected row with the selected desired cell and determining the value of the desired cell based on the value of the selected memristor row and the value of the selected memristor row with the selected desired cell.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: May 21, 2019
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Mohammed Affan Zidan, Hesham Omran, Ahmed Sultan Salem, Khaled Nabil Salama
  • Patent number: 10282436
    Abstract: A method of searching for data stored in a memory, the method including receiving a regex search request, generating a parse tree including fundamental regex operations corresponding to the regex search request, individually analyzing each of the fundamental regex operations of the generated parse tree in a respective time-step, determining a memory address location of data corresponding to the analyzed fundamental regex operations by using a translation table to determine whether the data exists, and using a reverse translation table to determine the memory address location of the data, and outputting data matching the regex search request after analyzing all of the fundamental regex operations of the generated parse tree.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: May 7, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Krishna T. Malladi, Hongzhong Zheng
  • Patent number: 10216720
    Abstract: Comparators may be associated with dictionary entries. In one aspect, a dictionary entry may store a dictionary word. A register may store an input word. A comparator associated with the dictionary entry may compare the dictionary word and the input word. The comparison may be a bit by bit comparison. The comparator may output a signal indicating if the dictionary word is less than the input word, equal to the input word, or greater than the input word. The output may indicate indeterminate when the comparison is not yet complete.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: February 26, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent Buchanan, Le Zheng, John Paul Strachan
  • Patent number: 10203955
    Abstract: Instructions and logic provide SIMD vector packed tuple cross-comparison functionality. Some processor embodiments include first and second registers with a variable plurality of data fields, each of the data fields to store an element of a first data type. The processor executes a SIMD instruction for vector packed tuple cross-comparison in some embodiments, which for each data field of a portion of data fields in a tuple of the first register, compares its corresponding element with every element of a corresponding portion of data fields in a tuple of the second register and sets a mask bit corresponding to each element of the second register portion, in a bit-mask corresponding to each unmasked element of the corresponding first register portion, according to the corresponding comparison. In some embodiments bit-masks are shifted by corresponding elements in data fields of a third register. The comparison type is indicated by an immediate operand.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Robert Valentine, Christopher J. Hughes, Mark J. Charney, Zeev Sperber, Amit Gradstein, Simon Rubanovich, Elmoustapha Ould-Ahmed-Vall, Yuri Gebil
  • Patent number: 10203892
    Abstract: A semiconductor device that includes a memory system is configured to accept input of search data and to search in parallel respective rows of a memory cell array such as a CAM and so forth for data held in a memory. The memory system detects whether an inflow amount of the search data that is input is at least a fixed amount by monitoring a packing ratio of an FIFO buffer that a search command is held. The memory system controls a speed of search processing by dividing the memory cell array into blocks and setting each block as a search processing object in accordance with a result of detection.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: February 12, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takeo Miki
  • Patent number: 10176099
    Abstract: An apparatus includes a cache controller, the cache controller to receive, from a requestor, a memory access request referencing a memory address of a memory. The cache controller may identify a cache entry associated with the memory address, and responsive to determining that a first data item stored in the cache entry matches a data pattern indicating cache entry invalidity, read a second data item from a memory location identified by the memory address. The cache controller may then return, to the requestor, a response comprising the second data item.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Jayesh Gaur, Supratik Majumder, Zvika Greenfield, Israel Diamand
  • Patent number: 10169278
    Abstract: One aspect of the invention relates to a network node for connecting to a Local Interconnect Network (LIN). In accordance with one example of the present invention, the network node includes a bus terminal which is operably coupled to a data line for receiving a data signal, which represents serial data, via that data line. The data signal is a binary signal having high and low signal levels. The network node further includes a receiver circuit which employs a comparator to compare the data signal with a reference signal. The comparator generates a binary output signal representing the result of the comparison. The network node also includes a measurement circuit that receives the data signal and provides a first voltage signal such that it represents the high signal level of the data signal.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: January 1, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Alexander Mori, Christoph Seidl
  • Patent number: 10141055
    Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: November 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Vishal Sarin
  • Patent number: 10133676
    Abstract: Embodiments related to a cache memory that supports tagless addressing are disclosed. Some embodiments receive a request to perform a memory access, wherein the request includes a virtual address. In response, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: November 20, 2018
    Assignee: Rambus Inc.
    Inventors: Hongzhong Zheng, Trung A. Diep
  • Patent number: 10043578
    Abstract: A sense amplifier circuit includes a single-ended sense amplifier and an isolation switch. The isolation switch is coupled between a bias node and a first line of a memory device, receives an output of the single-ended sense amplifier and selectively isolates the bias node and the first line in response to the output of the single-ended sense amplifier. The first line is coupled to a plurality of memory cells of the memory device.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: August 7, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shu-Lin Lai, Shu-Hsuan Lin, Shih-Huang Huang
  • Patent number: 10042764
    Abstract: A method for processing commands in a directory-based computer memory management system includes receiving a command to perform an operation on data stored in a set of one or more computer memory locations associated with an entry in a directory of a computer memory, the entry is associated with an indicator for indicating whether the set of one or more computer memory locations is busy, a head tag, and a tail tag. The command is associated with a command tag and a predecessor tag, and checking the indicator to determine whether the set of one or more computer memory locations is busy.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Bar-Joshua, Yiftach Benjamini, Yaakov Gendel, Eyal Gonen, Alexander Mesh
  • Patent number: 10037283
    Abstract: Techniques for improving translation lookaside buffer (TLB) operation are disclosed. A particular entry of the TLB is to be updated with data associated with a large page size. The TLB updates replacement policy data for that TLB entry for that large page size to indicate that the TLB entry is not the least-recently-used. To prevent smaller pages from evicting the TLB entry for the large page size, the TLB also updates replacement policy data for that TLB entry for the smaller page size to indicate that the TLB entry is not the least-recently-used.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: July 31, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony J. Bybell, John M. King
  • Patent number: 10007572
    Abstract: A method of operating a memory system includes receiving information data corresponding to a second program unit that is a part of a first program unit and a write request for the information data from a host; generating a codeword by performing error correction code (ECC) encoding on the received information data such that a partial parity bit corresponding to the information data among all parity bits of the codeword is updated; and providing a memory device with the generated codeword and a write command regarding the codeword.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Min Shin, Jun-Jin Kong, Beom-Kyu Shin, Eun-Chu Oh, Pil-Sang Yoon
  • Patent number: 9978451
    Abstract: The presented connection processes a stream data by a computer. The data is split into blocks called packets and the task is to search for a match of the data in packets with specified patterns—regular expressions, useful in the field of telecommunication technology and services. The connection may be formed within a semiconductor circuit, which serves for receiving, processing, and sending packets. This semiconductor circuit may be implemented by an FPGA-type circuit. In this way, instead of one circuit implementing the automaton with a total data width Sc, a set of simultaneously operating circuits is implemented forming several identical automata at a smaller data width Sn. This eliminates the exponential rise in the number of symbols in the automaton and at the same time it allows achieving a high throughput of the entire connection.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 22, 2018
    Assignees: CESNET, zajmove sdruzeni pravnickych osob, NETCOPE TECHNOLOGIES, a.s.
    Inventors: Viktor Pus, Vlastimil Kosar, Jan Korenek, Denis Matousek
  • Patent number: 9971686
    Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a vector cache line write back instruction. The vector cache line write back instruction is to indicate a source packed memory indices operand that is to include a plurality of memory indices. The processor also includes a cache coherency system coupled with the packed data registers and the decode unit. The cache coherency system, in response to the vector cache line write back instruction, to cause, any dirty cache lines, in any caches in a coherency domain, which are to have stored therein data for any of a plurality of memory addresses that are to be indicated by any of the memory indices of the source packed memory indices operand, to be written back toward one or more memories. Other processors, methods, and systems are also disclosed.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Kshitij A. Doshi, Thomas Willhalm
  • Patent number: 9940132
    Abstract: Techniques are disclosed relating to suspending execution of a processor thread while monitoring for a write to a specified memory location. An execution subsystem may be configured to perform a load instruction that causes the processor to retrieve data from a specified memory location and atomically begin monitoring for a write to the specified location. The load instruction may be a load-monitor instruction. The execution subsystem may be further configured to perform a wait instruction that causes the processor to suspend execution of a processor thread during at least a portion of an interval specified by the wait instruction and to resume execution of the processor thread at the end of the interval. The wait instruction may be a monitor-wait instruction. The processor may be further configured to resume execution of the processor thread in response to detecting a write to a memory location specified by a previous monitor instruction.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: April 10, 2018
    Assignee: Oracle International Corporation
    Inventors: Paul N. Loewenstein, Mark A. Luttrell, Paul J. Jordan
  • Patent number: 9941008
    Abstract: The present disclosure illustrates a ternary content addressable memory (TCAM) device for software defined networking and method thereof. In the TCAM device, M bits of each forwarding rule is stored as a first part into a NAND-Type TCAM, and N bits of the same forwarding rule is stored as a second part into a NOR-Type TCAM. M bits of searching data is compared with the first part to generate a first matching result, N bits of the searching data is compared with the second part to generate a second matching result when the first matching result indicates match, and comparing process for the second part is disabled when the first matching result indicates mismatch. The mechanism is help to improve flexibility of the TCAM in words length and to reduce power consumption.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: April 10, 2018
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: An-Yeu Wu, Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu
  • Patent number: 9904625
    Abstract: A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: February 27, 2018
    Assignee: Intel Corporation
    Inventors: Mohammad Abdallah, Ravishankar Rao, Karthikeyan Avudaiyappan
  • Patent number: 9898431
    Abstract: Aspects of the disclosure provide a circuit that includes a plurality of memory access circuits configured to access a memory to read or write data of a first width. The memory includes a plurality of memory banks that are organized in hierarchy. Further, the circuit includes a plurality of interface circuits respectively associated with the plurality of memory access circuits. Each interface circuit is configured to receive memory access requests to first level memory banks from an associated memory access circuit, segment the memory access requests into sub-requests to corresponding second level memory banks, buffer the sub-requests into buffers associated with the second level memory banks. In addition, the circuit includes arbitration circuitry configured to control multiplexing paths from the buffers to the second level memory banks to enable, in a same memory access clock, memory accesses by the memory access circuits.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: February 20, 2018
    Assignee: MARVELL ISRAEL (M.I.S.L) LTD.
    Inventors: Amir Bishara, Lior Valency, Rami Zemach
  • Patent number: 9728259
    Abstract: Non-volatile (NV)-content addressable memory (CAM) (NV-CAM) cells employing differential magnetic tunnel junction (MTJ) sensing for increased sense margin are disclosed. By the NV-CAM cells employing MTJ differential sensing, differential cell voltages can be generated for match and mismatch conditions in response to search operations. The differential cell voltages are amplified to provide a larger match line voltage differential for match and mismatch conditions, thus providing a larger sense margin between match and mismatch conditions. For example, a cross-coupled transistor sense amplifier employing positive feedback may be employed to amplify the differential cell voltages to provide a larger match line voltage differential for match and mismatch conditions. Providing NV-CAM cells that have a larger sense margin can mitigate sensing issues for increased search operation reliability.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: August 8, 2017
    Assignees: QUALCOMM Technologies, Inc., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Seong-Ook Jung, Byung Kyu Song, Taehui Na, Jung Pill Kim, Seung Hyuk Kang
  • Patent number: 9704576
    Abstract: A ternary content addressable memory (TCAM) cell may include a first resistive memory element, a second resistive memory element, a third resistive memory element, and a first switching element. The first resistive memory element may be disposed between a true data bit line node and a common node. The second resistive memory element may be disposed between a complement data bit line node and the common node. The third resistive element may be coupled to the common node and a word line node. The first switching element may have a control terminal coupled to the common node.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: July 11, 2017
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Brent Steven Haukness
  • Patent number: 9666278
    Abstract: A memory apparatus includes a content addressable memory, CAM, cell block including CAM cells and a random access memory (RAM), cell block including RAM cells. A geometric footprint of each of the CAM cells has a side bigger than a side of a geometric footprint of each of the RAM cells, where the sides of the CAM cells and the RAM cells are parallel to each other. The apparatus is configured to translate an input keyword at an input of the CAM cell block to an output word at an output of the RAM cell block when the keyword at the input of the CAM cell block is stored in the CAM cell block. The CAM cell block is split into a first part and a second part of the CAM cells.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventors: Alexander Fritsch, Werner Juchmes, Shankar Kalyanasundaram, Rolf Sautter
  • Patent number: 9665486
    Abstract: A hierarchical cache structure comprises at least one higher level cache comprising a unified cache array for data and instructions and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache and a data cache of a split second level cache are connected to a third level cache; and an instruction cache of a split first level cache is connected to the instruction cache of the split second level cache, and a data cache of the split first level cache is connected to the instruction cache and the data cache of the split second level cache.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventors: Christian Habermann, Christian Jacobi, Martin Recktenwald, Hans-Werner Tast
  • Patent number: 9646695
    Abstract: A memory cell includes a set of storage switch units, a set of memory units, a set of comparison switch units and a discharge switch unit. The storage switch units are turned on by a turn-on signal transmitted by a word line. The memory units receive and store write data transmitted by a bit line or a source line when the storage switch units are on under a write mode. The comparison switch units are turned on by comparison data transmitted by comparison lines under a search mode. The discharge switch unit is turned on by a detection voltage under the search mode when the comparison data transmitted by the comparison lines is different from the write data stored in the memory units, so that the reference signal transmitted to the comparator is redirected to a reference voltage. A content addressable memory using the memory cell is also provided.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 9, 2017
    Assignee: National Cheng Kung University
    Inventors: Lih-Yih Chiou, Tsai-Kan Chien