Associative Memories (content Addressable Memory-cam) Patents (Class 365/49.1)
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Patent number: 8619451Abstract: A CAM device for comparing a search key with a plurality of ternary words stored in a CAM array includes one or more population counters, a pre-compare memory, and a pre-compare circuit. The present embodiments reduce the power consumption of CAM devices during compare operations between a search key and ternary words stored in a CAM array by selectively enabling the match lines in the CAM array in response to pre-compare operations between a set of population counts corresponding to the masked search key and a set of population counts corresponding to the ternary words stored in the CAM array.Type: GrantFiled: January 6, 2012Date of Patent: December 31, 2013Assignee: NetLogic Microsystems, Inc.Inventor: Dimitri Argyres
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Patent number: 8614907Abstract: A controller, includes a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data, at least one external terminal among the plurality of external terminals being configured to be capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.Type: GrantFiled: September 15, 2012Date of Patent: December 24, 2013Assignee: Elpida Memory, Inc.Inventor: Atsuo Koshizuka
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Patent number: 8612673Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.Type: GrantFiled: June 26, 2012Date of Patent: December 17, 2013Assignee: Hicamp Systems, Inc.Inventor: David R. Cheriton
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Patent number: 8605474Abstract: A semiconductor memory device, includes a clock terminal provided to receive a clock signal, a data terminal provided to transfer a data therethrough in synchronization with the clock signal, a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough, a command terminal provided to receive a command that communicates the data with an outside thereof, and an address terminal provided to be supplied an information specifying a length of a preamble of the strobe signal from an outside of the semiconductor memory device, prior to communicating the data.Type: GrantFiled: September 15, 2012Date of Patent: December 10, 2013Assignee: Elpida Memory, Inc.Inventor: Atsuo Koshizuka
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Patent number: 8605475Abstract: A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.Type: GrantFiled: September 15, 2012Date of Patent: December 10, 2013Assignee: Elpida Memory, Inc.Inventor: Atsuo Koshizuka
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Patent number: 8605473Abstract: A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information.Type: GrantFiled: September 15, 2012Date of Patent: December 10, 2013Assignee: Elpida Memory, Inc.Inventor: Atsuo Koshizuka
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Publication number: 20130322145Abstract: A control signal generator to generate control signals for a readout integrated circuit (ROIC) includes a content addressable memory (CAM) and a random access memory (RAM). The CAM may have data stored within it that is indicative of times at which control signal switching events are to occur during generation of the control signals. The RAM may have data stored within it that is indicative of particular control signals that are to be toggled at the times indicated within the CAM.Type: ApplicationFiled: June 4, 2012Publication date: December 5, 2013Applicant: Raytheon CompanyInventors: Jeong-Gyun Shin, Micky Harris
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Patent number: 8599594Abstract: A nonvolatile memory device includes at least a memory cell block including memory cells that are coupled to a plurality of word lines, respectively, and store data; a content addressable memory (CAM) block including CAM cells that are coupled to the word lines, respectively, and store chip information for operations of the nonvolatile memory device; and a block switching circuit configured to couple the word lines with global word lines; and a voltage supply circuit coupled to the global word lines, for supplying a first read voltage to a selected global word line while supplying a first pass voltage to unselected global word lines in reading the memory cell block, and supplying a second read voltage to a selected global word line while supplying a second pass voltage to unselected global word lines in reading the CAM block, wherein the second pass voltage is lower than the first pass voltage.Type: GrantFiled: November 21, 2012Date of Patent: December 3, 2013Assignee: Hynix Semiconductor Inc.Inventor: Jin Su Park
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Patent number: 8599593Abstract: A memory system includes a memory device configured to read control data for operating conditions from a content addressed memory (CAM) block by performing a CAM read operation and to perform a data input/output operation based on the control data and a memory controller configured to store the control data of the memory device and to determine whether the memory device is to perform the CAM read operation by comparing the stored control data with the control data of the memory device when an operating mode of the memory device or the memory controller changes.Type: GrantFiled: July 12, 2011Date of Patent: December 3, 2013Assignee: Hynix Semiconductor Inc.Inventor: Seung Han Ryu
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Patent number: 8587978Abstract: A nonvolatile memory apparatus includes: a memory cell array including a plurality of planes and configured to store a plurality of code addressable memory (CAM) data in independent planes. A redundancy cell array is configured to replace the memory cell array and a CAM data read unit is configured to read the plurality of CAM data from the respective planes in parallel, in response to a CAM data read command, and store the read data.Type: GrantFiled: December 31, 2010Date of Patent: November 19, 2013Assignee: SK Hynix Inc.Inventor: Sang Kyu Lee
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Patent number: 8587980Abstract: An associative memory capable of reducing erroneous searches is provided. A storage memory in the associative memory stores reference data. A comparator circuit receives externally applied search data and obtains the distance (for example, the Hamming distance) between the reference data and the search data. An oscillating circuit outputs a pulse signal with an oscillating frequency corresponding to the distance obtained by the comparator circuit. Similarly, the oscillating circuits output pulse signals with oscillating frequencies according to the distance between the reference data in corresponding storage circuits and the search data. A WTA circuit receives the pulse signals. Reference data stored in a storage circuit corresponding to an oscillating circuit that outputs a pulse signal with the highest frequency is determined as the most similar reference data (Winner) to the search data.Type: GrantFiled: September 24, 2010Date of Patent: November 19, 2013Assignee: Hiroshima UniversityInventors: Hans Juergen Mattausch, Tetsushi Koide, Tania Ansari, Wataru Imafuku, Akihiro Kaya
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Patent number: 8582338Abstract: Ternary CAM cells are disclosed that include a compare circuit that includes a discharge path having a single pull-down transistor coupled between the match line and ground potential.Type: GrantFiled: May 31, 2011Date of Patent: November 12, 2013Assignee: NetLogic Microsystems, Inc.Inventor: Dimitri Argyres
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Patent number: 8582337Abstract: A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.Type: GrantFiled: March 15, 2013Date of Patent: November 12, 2013Assignee: Elpida Memory, Inc.Inventor: Atsuo Koshizuka
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Patent number: 8576599Abstract: A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.Type: GrantFiled: February 2, 2012Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Jagreet S. Atwal, Joseph S. Barnes, Kerry Bernstein, Robert J. Bucki, Jason A. Cox
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Patent number: 8570791Abstract: A word line driver circuit for providing a suppressed word line voltage includes a switch configured to selectively load a word line to a suppressed word line voltage node and a word line charging circuit coupled between a high power supply node and the suppressed word line voltage node. The word line charging circuit includes a first transistor device responsive to a control pulse for charging the suppressed word line voltage node to a suppressed word line voltage and a second transistor device for maintaining the suppressed word line voltage.Type: GrantFiled: October 5, 2011Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Jack Liu
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Patent number: 8572313Abstract: Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.Type: GrantFiled: October 10, 2011Date of Patent: October 29, 2013Assignee: QUALCOMM IncorporatedInventors: Manju Rathna Varma, David Paul Hoff, Jason Philip Martzloff
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Patent number: 8570827Abstract: Controllable arrays in a memory may be activated and deactivated independently. In one embodiment, a processor may include a memory. The memory may be a de-interleaved memory with independently selectable arrays. Based on an address bit of an address used to access data from the memory, a wordline and downstream components may be activated while another wordline and downstream components may be deactivated.Type: GrantFiled: June 20, 2011Date of Patent: October 29, 2013Assignee: Apple Inc.Inventors: Steven C. Sullivan, Abhijeet R. Tanpure, William V. Miller, Ben D. Jarrett
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Patent number: 8570783Abstract: Content-Addressable Memory (CAM) arrays and related circuitry for integrated circuits and CAM array comparison methods are provided such that relatively low power is used in the operation of the CAM circuitry. A binary value pair is stored in a pair of CAM memory elements. A comparison signal is provided to comparator circuitry that uniquely represents the stored binary values. A match signal is input to the comparator circuitry that uniquely represents a binary value pair to be compared with the stored binary value pair. In one example, a transistor is operated to output a positive match result signal only on a condition that the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent the same binary value pair. In that example, no transistor of the comparator circuitry is operated when the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent different binary value pairs.Type: GrantFiled: October 28, 2010Date of Patent: October 29, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Ganesh Venkataramanan, Kyle S. Viau, James Vinh
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Patent number: 8564998Abstract: Array area and power consumption are reduced in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.Type: GrantFiled: April 27, 2012Date of Patent: October 22, 2013Assignee: Renesas Electronic CorporationInventor: Kazunari Inoue
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Patent number: 8553441Abstract: Ternary CAM cells include a compare circuit including a discharge path having only two pull-down transistors coupled between the match line and ground potential.Type: GrantFiled: May 31, 2011Date of Patent: October 8, 2013Assignee: NetLogic Microsystems, Inc.Inventor: Dimitri Argyres
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Patent number: 8549218Abstract: A content-addressable memory (CAM) for managing the reallocation of erasable objects within a non-volatile memory is conceptually separated into two tables: a first table provides verification of whether or not a logical address has been reallocated and, if so, a second table provides the physical address of the reallocated erasable object.Type: GrantFiled: November 10, 2008Date of Patent: October 1, 2013Assignee: Inside SecureInventors: Yves Fusella, Stephane Godzinski
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Patent number: 8531860Abstract: A controller, includes a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data, at least one external terminal among the plurality of external terminals being configured to be capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.Type: GrantFiled: March 15, 2013Date of Patent: September 10, 2013Assignee: Elpida Memory, Inc.Inventor: Atsuo Koshizuka
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Patent number: 8520421Abstract: According to one embodiment, a semiconductor associative memory device comprises a retrieval block having retrieval word strings arranged in a column direction, each of the retrieval word strings includes memory cells arranged in a row direction between a word input terminal and a word output terminal, each of the memory cells having a first input terminal, a second input terminal, and an output terminal, wherein in each retrieval word string, the second input terminal of one of the memory cells is used as the word input terminal, and each of other memory cells is connected to the output terminal of adjacent memory cell by the second input terminal, wherein the first input terminals of the memory cells in the same column are connected.Type: GrantFiled: March 16, 2012Date of Patent: August 27, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Atsuhiro Kinoshita
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Patent number: 8503210Abstract: A conditionally precharged content addressable memory (CAM) includes forcing a mismatch on a matchline of the CAM if a data entry in the CAM is invalid. The matchline of the CAM is precharged only if the data entry is valid.Type: GrantFiled: December 22, 2010Date of Patent: August 6, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Mandeep Singh, David Hugh McIntyre, Hung Phuong Ngo
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Patent number: 8498171Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.Type: GrantFiled: August 6, 2012Date of Patent: July 30, 2013Assignee: Micron Technology, Inc.Inventors: Paul A. Farrar, Hussein I Hanafi
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Publication number: 20130188409Abstract: An energy-efficient CAM architecture provides increased speed of searching, reduced power consumption, or a tuned combination of increased speed of searching and reduced power consumption. The CAM comprises a plurality of CAM banks, a plurality of Bloom filters, each Bloom filter associated with a content addressable memory bank, each Bloom filter recording elements inserted into an associated content addressable memory bank, wherein the size of each Bloom filter is configured to reduce energy or power consumption of the content addressable memory apparatus. The size of each Bloom filter may be configured to reduce energy or power consumption of the content addressable memory apparatus.Type: ApplicationFiled: January 22, 2013Publication date: July 25, 2013Applicant: University o Rochester, Office of Technology TransferInventor: University of Rochester, Office of Technology Transfer
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Patent number: 8493763Abstract: A CAM array includes a plurality of regular rows and a reference row. Each regular row is partitioned into a plurality of row segments, with each row segment including a number of CAM cells coupled to a corresponding match line segment. The reference row generates self-timed control signals for corresponding segments of the regular rows. Control circuits selectively enable a respective row segment in response to a logical combination of match results in a previous row segment and an associated one of the self-timed control signals.Type: GrantFiled: October 27, 2011Date of Patent: July 23, 2013Assignee: NetLogic Microsystems, Inc.Inventor: Dimitri Argyres
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Patent number: 8493764Abstract: An integrated circuit having a CAM array includes a plurality of CAM cells organized in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and a match line for each row connected to be shared by CAM cells in that row. The CAM array also includes a feedback circuit for each row connected to limit a discharge voltage for a corresponding match line in that row. In another aspect, a method of operating an integrated circuit having a CAM array includes organizing a plurality of CAM cells in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and sharing a match line with CAM cells in each row. The method also includes limiting a discharge voltage for the match line.Type: GrantFiled: February 10, 2011Date of Patent: July 23, 2013Assignee: LSI CorporationInventors: Vinod Rachamadugu, Uddip Roy, Setti Shanmukheswara Rao, Nikhil Lad
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Patent number: 8488369Abstract: A method is provided for altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device. The method comprises identifying a subset of the memory cells whose value of the chosen characteristic is within a predetermined end region of the distribution, and then performing a burn-in process during which one or more operating parameters of the memory device are set to induce aging of the memory cells. During the burn-in process, for each memory cell in the subset, the value stored in that memory cell is fixed to a selected value which exposes that memory cell to a stress condition. In contrast, for each memory cell not in the subset, the value stored in that memory cell is alternated during the burn-in process in order to alleviate exposure of that memory cell to the stress condition. Such an approach allows a tightening of the distribution of the chosen characteristic, thus improving the worst case memory cells.Type: GrantFiled: March 10, 2011Date of Patent: July 16, 2013Assignee: ARM LimitedInventors: Vikas Chandra, Robert Campbell Aitken
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Publication number: 20130155749Abstract: A memory includes a plurality of content-addressable memory (CAM) cells and a summary circuit associated with the plurality of CAM cells. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates.Type: ApplicationFiled: February 19, 2013Publication date: June 20, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Young Seog KIM, Kuoyuan HSU, Jacklyn CHANG
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Patent number: 8467213Abstract: A content search system including a CAM device having a plurality of CAM blocks and a governor logic receives a search request and compares the number of CAM blocks required to perform the requested search to a limit number, the limit number being the maximum number of CAM blocks permitted to be used in a requested search operation. If the number of CAM blocks required to perform the requested search exceeds the maximum number of CAM blocks permitted to be used in a requested search operation, then the search operation is rejected. The governing operation can be performed on each requested search, thus limiting power dissipation. The relationship between a maximum number of CAM blocks and power dissipation can be characterized, and a corresponding block limit value can be stored into a memory accessible by governor logic.Type: GrantFiled: March 22, 2011Date of Patent: June 18, 2013Assignee: NetLogic Microsystems, Inc.Inventor: Shankar Channabasappa
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Patent number: 8468296Abstract: Aspects of the disclosure provide a method for encoding ranges in a ternary content addressable memory (TCAM). The method includes determining first positive ranges and first negative ranges corresponding to a first encoding range to be encoded in the TCAM. The first encoding range is in association with a first action. The first positive ranges include the first encoding range. The first negative ranges exclude the first encoding range. At least a first positive range and a first negative range are overlapping. Further, the method includes encoding the first positive ranges in first TCAM entries, and encoding the first negative ranges in second TCAM entries. At least one of the second TCAM entries has a higher priority than one of the first TCAM entries. Then, the method includes associating the first TCAM entries to the first action, and associating the second TCAM entries to a reject action.Type: GrantFiled: March 1, 2010Date of Patent: June 18, 2013Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventor: Rami Cohen
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Patent number: 8462532Abstract: Quaternary CAM cells are provided that include one or more compare circuits that each has a minimal number of pull-down transistors coupled between the match line and ground potential. For some embodiments, the compare circuit includes two parallel paths between the match line and ground potential, with each parallel path consisting of a single pull-down transistor having a gate selectively coupled to the stored data value in response to a comparand value.Type: GrantFiled: January 27, 2011Date of Patent: June 11, 2013Assignee: Netlogic Microsystems, Inc.Inventor: Dimitri Argyres
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Patent number: 8462552Abstract: Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array.Type: GrantFiled: September 13, 2012Date of Patent: June 11, 2013Assignee: Micron Technology, Inc.Inventor: Ramin Ghodsi
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Patent number: 8451640Abstract: A content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.Type: GrantFiled: January 10, 2011Date of Patent: May 28, 2013Assignee: Broadcom CorporationInventors: Christopher Gronlund, Mark Winter
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Publication number: 20130127493Abstract: A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs.Type: ApplicationFiled: January 11, 2013Publication date: May 23, 2013Inventor: Laurence H. Cooke
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Patent number: 8446748Abstract: What is disclosed is a novel memory array and process for creating a memory array to reduce wireline variability. The method includes accessing a routing design of a memory array with a plurality of memory cells. Each memory cell in the array includes one or more access devices, and a group of wires electrically connected between one or more of the memory cells and peripheral circuitry (PC). The group of the group of wires is divided into at least one subgroup (N). Next, a capacitance (C1, C2 . . . CN) of each wire in the subgroup (N) is calculated. Continuing further, a maximum capacitance (CMAX) of wires in the subgroup (N) is determined. An add-on capacitance to be added to a number (NA) of the wires in the subgroup (N) is calculated.Type: GrantFiled: August 4, 2011Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Chung Hon Lam, Jing Li, Robert Montoye
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Patent number: 8441829Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.Type: GrantFiled: March 19, 2010Date of Patent: May 14, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huai-Ying Huang, Yu-Kuan Lin, Sheng Chiang Hung, Feng-Ming Chang, Jui-Lin Chen, Ping-Wei Wang
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Patent number: 8441828Abstract: The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers.Type: GrantFiled: June 28, 2012Date of Patent: May 14, 2013Assignee: Renesas Electronics CorporationInventor: Naoya Watanabe
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Patent number: 8432764Abstract: A method of increasing a drain to source voltage measured at an access pass-gate to a SRAM circuit in a SRAM memory array, including increasing a low voltage from a low voltage source powering said SRAM circuit, and increasing a high voltage from a high voltage source powering the SRAM circuit.Type: GrantFiled: May 12, 2010Date of Patent: April 30, 2013Assignee: International Business Machines CorporationInventors: Omer Heymann, Dana Bar-Niv, Noam Jungmann, Elazar Kachir, Udi Nir, Limor Plotkin, Amira Rozenfeld, Robert C. Wong, Haining S. Yang
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Patent number: 8427854Abstract: Searching for patterns stored on a hardware storage device. A method includes, as part of a memory refresh operation, performing a read to read contents of a portion of a memory. The method further includes writing the read contents of the portion of memory back to the portion of memory. The read contents are provided to data comparison logic. Using the data comparison logic; the read contents are compared to predetermined data patterns. A determination is made as to whether or not the contents match at least one of the predetermined data patterns. When the read contents match at least one of the predetermined data patterns, a software readable indicator is provided indicating that the read contents match at least one of the predetermined data patterns. Similar embodiments may be implemented using hard drive head wear leveling operations.Type: GrantFiled: April 15, 2010Date of Patent: April 23, 2013Assignee: Microsoft CorporationInventors: Yaron Weinsberg, John Joseph Richardson
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Publication number: 20130077373Abstract: In a method of operating a nonvolatile memory device, at least one among memory cell blocks of the nonvolatile memory device is designated as a content addressable memory (CAM) block which includes a plurality of CAM cells coupled to respective word lines of the nonvolatile memory device. Chip information for operations of the nonvolatile memory device is stored in the CAM cells which are coupled to a selected word line, whereas the remaining CAM cells of the CAM block are in an erased state.Type: ApplicationFiled: November 21, 2012Publication date: March 28, 2013Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Hynix Semiconductor Inc.
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Patent number: 8400803Abstract: A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage of a match line MLA. A match amplifier B determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array B, according to a voltage of a match line MLB. A block-B control circuit directs to start searching in the memory array B after two cycles after searching has been started in the memory array A. A block-B activation control circuit directs to stop searching in the memory array B according to a voltage of the match line MLA after searching in the memory array A.Type: GrantFiled: March 2, 2011Date of Patent: March 19, 2013Assignee: Renesas Electronics CorporationInventor: Mihoko Akiyama
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Patent number: 8395920Abstract: A static CAM includes a plurality of entries E each including a number of CAM cells B and a summary S. Each CAM cell B is associated with a memory cell M and a comparator C. Generally, the CAM receives as input i number of lookup data lines. When data is received, memory cells M provide compared data for corresponding comparators C in CAM cells B to compare the compared data to the received data. If all compared data match all received data lines for an entry, then there is a hit for that entry. But if any compared data does not match the corresponding data line, then there is a miss for that line and therefore a miss for that entry. Depending on applications, the CAM returns an address if there is a hit for one or a plurality of entries.Type: GrantFiled: May 27, 2010Date of Patent: March 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Young Seog Kim, Kuoyuan Hsu, Jacklyn Chang
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Publication number: 20130033915Abstract: What is disclosed is a novel memory array and process for creating a memory array to reduce wireline variability. The method includes accessing a routing design of a memory array with a plurality of memory cells. Each memory cell in the array includes one or more access devices, and a group of wires electrically connected between one or more of the memory cells and peripheral circuitry (PC). The group of the group of wires is divided into at least one subgroup (N). Next, a capacitance (C1,C2 . . . CN) of each wire in the subgroup (N) is calculated. Continuing further, a maximum capacitance (CMAX) of wires in the subgroup (N) is determined. An add-on capacitance to be added to a number (NA) of the wires in the subgroup (N) is calculated.Type: ApplicationFiled: August 4, 2011Publication date: February 7, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chung Hon LAM, Jing LI, Robert MONTOYE
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Patent number: 8369175Abstract: Integrated circuits may include memory elements that are provided with voltage overstress protection. One suitable arrangement of a memory cell may include a latch with two cross-coupled inverters. Each of the two cross-coupled inverters may be coupled between first and second power supply lines and may include a transistor with a gate that is connected to a separate power supply line. Another suitable memory cell arrangement may include three cross-coupled circuits. Two of the three circuits may be powered by a first positive power supply line, while the remaining circuit may be powered by a second positive power supply line. These memory cells may be used to provide an elevated positive static control signal and a lowered ground static control signal to a corresponding pass gate. These memory cells may include access transistors and read buffer circuits that are used during read/write operations.Type: GrantFiled: September 1, 2010Date of Patent: February 5, 2013Assignee: Altera CorporationInventors: Lin-Shih Liu, Andy L. Lee, Ping-Chen Liu, Irfan Rahim, Srinivas Perisetty
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Patent number: 8369120Abstract: Techniques are described for sum address compare (A+B=K) operation for use in translation lookaside buffers and content addressable memory devices, for example. Address input signals A and B are supplied as input to the A+B=K operation and K is a previous value stored in a plurality of memory cells. In each memory cell, a single logic gate circuit output and its inversion are generated in response to updating the memory cells, wherein each single logic gate circuit has as input an associated memory cell output and a next lowest significant bit adjacent memory cell output. In each of the memory cells, a portion of the A+B=K operation associated with each memory cell is generated in a partial lookup compare circuit wherein the corresponding address input signals A and B are combined with the associated memory cell output and the generated single logic gate circuit output and its inversion during a read lookup compare operation.Type: GrantFiled: March 19, 2010Date of Patent: February 5, 2013Assignee: QUALCOMM IncorporatedInventor: Timothy Edward Ozimek
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Patent number: 8369121Abstract: The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating the number of active states and number of compare operations performed during each sampling period. The sampling signals are accumulated to generate an estimated device power profile, which is compared with reference values corresponding to predetermined power levels to generate a dynamic power control signal indicating predicted increases in the device's operating temperature resulting from its power consumption. The dynamic power control signal is then used to selectively reduce the input data rate of the CAM device, thereby reducing power consumption and allowing the device to cool.Type: GrantFiled: January 17, 2012Date of Patent: February 5, 2013Assignee: NetLogic Microsystems, Inc.Inventors: Carl Gyllenhammer, Greg Watson, Venkat Gaddam, Varadarajan Srinivasan, Sandeep Khanna, Chetan Deshpande
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Patent number: 8358524Abstract: A content addressable memory (CAM) device can include a number of bit line. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell can include compare circuits that compare a stored value one or more compare data values. An isolation circuit can have a controllable impedance path connected between the bit line and a precharge voltage node and can be controlled by application of a potential at a control node. A control circuit can be coupled to the control node and can switch the isolation circuit from a high impedance state to a low impedance state in response to, and no later than the start of, an access operation.Type: GrantFiled: June 27, 2008Date of Patent: January 22, 2013Assignee: Netlogic Microsystems, Inc.Inventor: Martin Fabry
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Patent number: 8345478Abstract: Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array.Type: GrantFiled: February 22, 2011Date of Patent: January 1, 2013Assignee: Micron Technology, Inc.Inventor: Ramin Ghodsi