Abstract: A memory cell includes a first transistor controlling writing of the first date by being in an on state, and holding of the first data by being in an off state, a second transistor in which a potential of one of a source and a drain is a potential of the second data and a potential of a gate is a potential of the first data, and a third transistor which has a conductivity type opposite to that of the second transistor, which has one of a source and a drain electrically connected to the other of the source and the drain of the second transistor, and in which a potential of a gate is a potential of the first data.

Abstract: A memory array includes a first memory column having a first bit line, a first word line and a second bit line. The memory array also includes a second memory column having the second bit line, a second word line and a third bit line. The first memory column and the second memory column are configured to share the second bit line. The sharing of the second bit line facilitates sharing one or more memory array components between the first memory column and the second memory column.

Abstract: Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements.

Abstract: Integrated electronic memory devices include control logic and one or more cross point information storage arrays. The cross point storage array(s) include a non-linear conductor proximate to at least one cross point storage location, and the control logic comprises (i) an NMOS type transistor and a PNP type transistor, but not a PMOS type transistor, or (ii) a PMOS type transistor and an NPN type transistor, but not an NMOS type transistor.

Abstract: A semiconductor integrated circuit includes a transistor with a source region, a drain region, and a control gate electrode. The integrated circuit additionally includes a controller that selectively applies voltages to the control gate of the transistor. The controller may apply a first voltage that forms a permanent conductive path between the source and drain of the transistor.

Abstract: To provide a semiconductor device with high reliability in operation, in which data in a volatile memory can be saved to a non-volatile memory. For example, the semiconductor device includes an SRAM provided with first and second data storage portions and a non-volatile memory provided with third and fourth data storage portions. The first data storage portion is electrically connected to the fourth data storage portion through a transistor, and the second data storage portion is electrically connected to the third data storage portion through a transistor. The transistors are turned off when the SRAM operates, and the transistors are turned on when the SRAM does not operate, so that data in the SRAM is saved to the non-volatile memory. Precharge is performed when the SRAM is restored.

Abstract: A nonvolatile memory device includes: a channel layer extending in a vertical direction from a substrate; a plurality of interlayer dielectric layers and word lines alternately stacked along the channel layer over the substrate; a bit line formed under plurality of interlayer dielectric layers and word lines, coupled to the channel layer, and extending in a direction crossing the word lines; and a common source layer coupled to the channel layer and formed over the plurality of interlayer dielectric layers and word lines.

Abstract: Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, an asymmetrically doped transistor, and a gated diode device. The capacitor, transistor, and gated diode device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The gated diode device allows for erasure of an entire NVM memory more efficiently and using less substrate space than a similar device that uses a transistor. The asymmetric transistor, in conjunction with the capacitor, is used to both program and read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read and write operations.

Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.

Abstract: A radiation-hardened memory storage unit that is resistant to total ionizing done effects, the unit including PMOS transistors.

Abstract: A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.

Abstract: The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3D orientation such that macro cells that are in the middle of the 3D arrangement can be addressed without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. An individual macro cell within a memory cell can be addressed by applying three separate currents to the macro cell. A first current is applied to the memory cell directly. A second current is applied to the source electrode of the MESFET, and a third current is applied to the gate electrode of the MESFET to permit the current to travel through the channel of the MESFET to the drain electrode which is coupled to the memory element.

Abstract: In a method for boosting a word line signal, the word line signal is transitioned from a first voltage value of the word line signal to a second voltage value of the word line signal, thereby turning on a first transistor. The first transistor and a second transistor turn on a third transistor. The third transistor causes the word line signal at a first terminal of the third transistor to reach a voltage value at a second terminal of the third transistor, thereby causing the word line signal to reach the voltage value faster than without the third transistor. The first transistor and the second transistor are coupled in series.

Abstract: A radiation-hardened storage unit, including a basic storage unit, a redundant storage unit, and a two-way feedback unit. The basic storage unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The first PMOS transistor and the second PMOS transistor are read-out access transistors. The third PMOS transistor and the fourth PMOS transistor are write-in access transistors. The redundant storage unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The fifth PMOS transistor and the sixth PMOS transistor are read-out access transistors. The seventh PMOS transistor and the eighth PMOS transistor are write-in access transistors. The two-way feedback unit is configured to form a feedback path between the storage node and the redundant storage node.

Abstract: A semiconductor memory device according to an embodiment comprises: a plurality of memory cells arranged in a first direction and a second direction; local bit lines connected to group of the memory cells; a global bit line to be commonly connected to a plurality of the local bit lines; and switch circuits connected between the local bit lines and the global bit line. The switch circuits connect the global bit line to one of the local bit lines, the one of the local bit lines being electrically connected to the memory cells of the group located at a position specified by select information of the first direction and the second direction.

Abstract: Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.

Abstract: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.

Abstract: To provide a memory device with short overhead time and a semiconductor device including the memory device. A memory device includes a first circuit that can retain data and a second circuit by the supply of power supply voltage. The second circuit includes a third circuit that selects a first potential corresponding to the data or a second potential supplied to a first wiring; a first transistor having a channel formation region in an oxide semiconductor film; a capacitor that hold the first potential or the second potential that is selected by the third circuit and supplied through the first transistor; and a second transistor controlling a conduction state between the first circuit and a second wiring that can supply a third potential in accordance with the potential retained in the capacitor.

Abstract: A static random access memory structure is provided. The static random access memory structure includes a storage region having a first storage node and a second storage node which is complementary to the first storage node. The static random access memory structure also includes a reading region having a first reading transfer gate and a second reading transfer gate, and a reading word line electrically connecting with the gate of the first reading transfer gate and the gate of the second reading transfer gate. Further, the static random access memory structure includes a writing region independent of the reading region having a first writing transfer gate and a second writing transfer gate and a writing word line electrically connecting with the gate of the first writing transfer gate and the gate of the second transfer gate.

Abstract: In a memory device having a hierarchical bit line architecture, a main memory array is divided into two sub-memory arrays. The number of sub bit lines is twice the number of main bit lines, and global data lines are formed in the same metal interconnect layer as the main bit lines, thereby reducing an increase in the number of interconnects used in a memory macro. Furthermore, after charge sharing of the bit lines, the global data lines are kept in a pre-charge state at the time of amplification using sense amplifiers so that the global data lines function as shields of the main bit lines. This largely reduces interference noise between adjacent main bit lines to improve operating characteristics.

Abstract: A radiation-hardened memory storage unit that is resistant to total ionizing done effects, the unit including PMOS transistors.

Abstract: A radiation-hardened storage unit, including a basic storage unit, a redundant storage unit, and a two-way feedback unit. The basic storage unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The first PMOS transistor and the second PMOS transistor are read-out access transistors. The third PMOS transistor and the fourth PMOS transistor are write-in access transistors. The redundant storage unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The fifth PMOS transistor and the sixth PMOS transistor are read-out access transistors. The seventh PMOS transistor and the eighth PMOS transistor are write-in access transistors. The two-way feedback unit is configured to form a feedback path between the storage node and the redundant storage node.

Abstract: A semiconductor device comprises a semiconductor substrate including first and second regions that have different conductivity types from each other; an isolation region extending continuously over the first and second regions and having a shallow trench covered by a field insulator; first and second active regions placed in respective first and second regions and being each surrounded by the isolation region; a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region via the isolation region, the gate groove being shallower than the shallow trench; a cap insulating film disposed in an upper portion of the gate groove so as to cover an upper surface of the gate electrode; first and second transistors placed in respective first and second active regions and sharing the gate electrode; and a logic circuit including the first and second transistors connected in series.

Abstract: A memory cell includes a first transistor controlling writing of the first date by being in an on state, and holding of the first data by being in an off state, a second transistor in which a potential of one of a source and a drain is a potential of the second data and a potential of a gate is a potential of the first data, and a third transistor which has a conductivity type opposite to that of the second transistor, which has one of a source and a drain electrically connected to the other of the source and the drain of the second transistor, and in which a potential of a gate is a potential of the first data.

Abstract: A semiconductor device includes a cell region including memory cells that have a selection element and a data storage element, and a driving circuit region including a driving transistor configured to operate the selection element. The driving transistor includes active portions defined by a device isolation pattern in a substrate and a gate electrode running across the active portion along a first direction, the gate electrode including channel portions of a ring-shaped structure. The driving transistor further includes first impurity doped regions disposed in the active portions that are surrounded by channel portions, and second impurity doped regions disposed in the active portion that are separated from the first impurity doped regions by the channel portions.

Abstract: A memory includes a first and second cell storing first data and second or reference-data. A first and second bit-lines connected to the first and second cells respectively correspond to a first and second sense-nodes. A first transfer-gate is inserted/connected between the first bit-line and the first sense-node. A second transfer-gate is inserted/connected between the second bit-line and the second sense-node. A sense-amplifier is inserted or connected between the first and second sense-nodes. A preamplifier includes a first and second common-transistors. The first common-transistor applies a first power-supply voltage to either the first or the second sense-node according to the first and second data or according to the first and reference-data during a data-read-operation. The second common-transistor applies a second power-supply voltage to the other sense-node out of the first and second sense-nodes according to the first and second data or according to the first and reference data.

Abstract: A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).

Abstract: A semiconductor memory includes a memory cell array having a plurality of memory cells, a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array, and a sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for amplifying a potential difference between the bit line pair, in which the sense amplifier has precharging transistors each having a diffusion layer and precharging the bit line pair, and switching transistors having a diffusion layer formed integrally with the diffusion layer of the precharging transistors for selectively connecting the plurality of bit line pairs to a common bus line.

Abstract: A mutltiport memory cell having improved density area is disclosed. The memory cell includes a data storing component, a first memory access component coupled to a first side of the data storing component, a second memory access component coupled to a second side of the data storing component, first and second bit lines coupled to the first memory access component, first and second bit lines coupled to the second memory access component, first and second write lines coupled to the first memory access component and first and second write lines coupled to the second memory access component. The multiport memory cell also includes a read/write assist transistor, coupled to load transistors of the data storing component, that during read operations is activated for the duration of the read operation and during write operations is activated to impress the desired voltage level before or after one or more memory access components activated as a part of the write operation are deactivated.

Abstract: An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure.

Abstract: A method for providing a SRAM cell having a dedicated read port separated from a write port includes providing a first and a second bit-line placed in parallel forming a complementary bit-line pair for the dedicated read port, and providing a third and a fourth bit-line placed in parallel forming a complementary bit-line pair for the write port. The method further includes providing a positive voltage supply line disposed between a first and a second ground line placed in parallel, providing a first and a second metal line adjacently flanking and in parallel to the first bit-line, and providing a third and a fourth metal line adjacently flanking and in parallel to the second bit-line to provide a new SRAM cell structure having a balanced read and write operation speed and an improved noise margin.

Abstract: Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements.

Abstract: A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell.

Abstract: A nonvolatile memory device is provided. The device may include a plurality of cell strings that are configured to share a bit line, word lines, and selection lines. Each of the cell strings may include a plurality of memory cells connected in series to each other and a string selection device controlling connections between the memory cells and the bit line, and the string selection device may include a first string selection element with a first threshold voltage and a second string selection element connected in series to the first string selection element and having a second threshold voltage different from the first threshold voltage. At least one of the first and second string selection elements may include a plurality of switching elements connected in series to each other.

Abstract: Dynamic/static random access memory (D/SRAM) cell, block shift static random access memory (BS-SRAM) and method using the same employ dynamic storage mode and dynamic storage mode switching to shift data. The D/SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, and a dynamic/static (D/S) mode selector to selectably switch the D/SRAM cell between the dynamic storage mode and a static storage mode. The BS-SRAM includes a plurality of D/SRAM cells arranged in an array and a controller to shift data from an adjacent D/SRAM cell in a second row of the array to a D/SRAM cell in a first row. The method includes switching the mode of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected D/SRAM cell.

Abstract: A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

Abstract: A storage circuit includes a volatile storage portion in which storage of a data signal is controlled by a clock signal and an inverted clock signal, and a nonvolatile storage portion in which a data signal supplied to the volatile storage portion can be held even after supply of power supply voltage is stopped. A wiring which supplies a power supply voltage and is connected to a protective circuit provided for a wiring for supplying the clock signal is provided separately from a wiring which supplies a power supply voltage and which is connected to the storage circuit. The timing of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the protective circuit is different from that of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the storage circuit.

Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.

Abstract: Methods and apparatus for providing single finFET and multiple finFET SRAM arrays on a single integrated circuit are provided. A first single port SRAM array of a plurality of first bit cells is described, each first bit cell having a y pitch Y1 and an X pitch X1, the ratio of X1 to Y1 being greater than or equal to 2, each bit cell further having single fin finFET transistors to form a 6T SRAM cell and a first voltage control circuit; and a second single port SRAM array of a plurality of second bit cells, each second bit cell having a y pitch Y2 and an X pitch X2, the ratio of X2 to Y2 being greater than or equal to 3, each of the plurality of second bit cells comprising a 6T SRAM cell wherein the ratio of X2 to X1 is greater than about 1.1.

Abstract: A semiconductor cell comprises a plurality of metal layers. A first layer comprises a VDD conductor, a bit-line, and a complimentary bit-line. Each of the VDD conductor, the bit-line, and the complementary bit-line extend in a first direction. A second layer comprises a first VSS conductor and a first word-line. The VSS conductor and the first word-line extend in a second direction different than the first direction. A third layer comprises a second VSS conductor. The second VSS conductor extends in the first direction. A fourth layer comprises a second word-line. The second word-line extends in the second direction. The first word-line is electrically coupled to the second word-line.

Abstract: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.

Abstract: A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements in accordance with the configuration data stored in the configuration memory. The memory element is formed using a storage element including a transistor whose channel is formed in an oxide semiconductor layer and a node set in a floating state when the transistor is turned off.

Abstract: Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and second set of data lines. Other embodiments including additional apparatuses and methods are described.

Abstract: A phase change memory apparatus is provided that includes a first electrode that is longer than it is wide, the first electrode having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode.

Abstract: A flash memory is disclosed. A core array stores data. A peripheral circuit accesses the data stored in the core array to generate read data. A off-chip driver (OCD) processes the read data to generate output data. An interconnect structure is electrically connected to the core array, the peripheral circuit, and the OCD and includes three conductive layers. The conductive layers are electrically connected to each other. An uppermost conductive layer is formed over the interconnect structure, electrically connected to the interconnect structure, and includes a first power pad and first power tracks. The first power pad is electrically connected to a power pin via a first bonding wire to receive an operation voltage. The first power tracks are electrically connected between the first power pad and the interconnect structure to transmit the operation voltage to at least one of the core array, the peripheral circuit and the OCD.

Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

Abstract: An embodiment of a nonvolatile-memory device includes: a body accommodating at least a first semiconductor well and a second semiconductor well; an insulating structure; and at least one nonvolatile memory cell. The cell includes: at least one first control region in the first well; conduction regions in the second well; and a floating gate region, which extends over portions of the first well and of the second well, is capacitively coupled to the first control region and forms a floating-gate memory transistor with the conduction regions. The insulating structure includes: first insulating regions, which separate the floating gate region from the first control region and from the second well outside the conduction regions and have a first thickness; and second insulating regions, which separate the floating gate region from the first well outside the first control region and have a second thickness greater than the first thickness.

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract: A memory array includes segmented global and local digit lines in which the global digit line segments are switchably coupled to one of a plurality of local digit line segments at a time. A sense circuit coupled to a global digit line segment can be switched to sense memory cells coupled to one of the plurality of local digit lines at a first time and memory cells coupled to a second one of the plurality of local digit lines at a second time. Neither the global digit line segments nor the local digit line segments extend through the entire memory array.