Abstract: Methods and systems for the analysis of genotyping data are presented. According to various embodiments of methods and systems, an angle configuration search may be performed. In various embodiments, an exhaustive search over the entirety of an angle configuration space may be performed to provide a fit to a plurality of angles determined for a plurality of points in a data set generated from a plurality of biological samples. For various embodiments, the angle configuration space may be defined to ensure that a global fit may be determined. According to various methods and systems, a data base of possible angle configurations may be searched, in which each angle configuration may include three angles. According to various methods and systems, a data base of possible angle configurations may include for each angle configuration a probability that the angle configuration may occur.

Abstract: A low-pin-count non-volatile memory (NVM) embedded an integrated circuit can be accessed without any additional pins. The NVM has one or more memory cells and at least one of the NVM cells can have at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector can be coupled to a second supply voltage line and has a selecting signal. The integrated circuit can include at least one test mode detection circuit to activate a test mode upon detecting an abnormal (or out of normal) operation condition(s). Once a test mode is activated, at least one I/O or supply voltage of the integrated circuit can be used as the I/O or supply voltage of the NVM to select at least one NVM cell for read, program into nonvolatile, or volatile state. At least one NVM cell can be read during ramping of at least one supply voltage line.

Abstract: Methods and apparatus for the encoding of an input sequence of digit data into a sequence of storage cells of a ROM device are disclosed. The input sequence is divided into a first kind of groups and a second kind of groups. A first kind of group comprises a plurality of consecutive first digits, two first kind of groups are separated by a second kind of group, the second kind of group comprises consecutive digits without any consecutive first digits, and the second kind of group has a starting digit which is the second digit. A starting storage cell is programmed to the active state to store the starting digit of the second kind of group. The rest digits of the second kind of group are programmed one digit at a time, based on a shared terminal which has been programmed for the proceeding storage cell.

Abstract: Disclosed are a method of and system for detecting a consensus motif in a data sequence. The method comprises the steps of obtaining the data sequence, identifying potential signal (PS) segments of interest in the data sequence, and carrying out comparison and alignment processes amongst the PS segments to extract the consensus motif. Preferably, an unsupervised motif discovery process is used to identify the PS segments. More specifically, this may be done by extracting all common motifs across the sequence using the unsupervised motif discovery process; and for each of at least selected positions in the sequence, computing the weighted sum of the common motifs that cover said position. The PS segments that cover the positions where said number is above a given threshold may then be identified as the PS segments.

Abstract: An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line.

Abstract: A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.

Abstract: The programming of a read-only memory formed of MOS transistors is set by a mask for forming an insulating layer prior to the forming of contacts of active regions of the transistors. The programming of the read-only memory cannot be determined by visible inspection of the memory.

Abstract: An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate.

Abstract: In some embodiments, a non-transitory processor-readable medium includes code to cause a processor to receive a set of variants identified by a comparison of a test DNA sequence with a reference DNA sequence and associate at least one of the set of variants with at least one of a set of annotations each indicative of at least one criterion. The code includes code to cause the processor to filter, based on the set of annotations, the set of variants to identify a subset of variants from the set of variants. Each variant from the subset of variants is associated with at least one common annotation from the set of annotations. The code further includes code to cause the processor to present the subset of variants such that the subset of variants can be used to render a clinical diagnosis.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement.

Abstract: A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications.

Abstract: The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data.

Abstract: A reprogrammable memory, which can be, programmed a limited number of times. A plurality of one-time programmable elements are combined by a logic arrangement such that the output of that logic arrangement may be reprogrammed a limited number of times.

Abstract: An embodiment of the invention discloses an electronic device for reducing degradation in NMOS circuits in a tracking circuit. A first multiplexer selects, based on N bits from a row address in a memory array, which tracking circuit from a group of 2N tracking circuits will be used to provide a signal develop time for a memory cell in the memory array using a dummy word line signal. A second multiplexer selects, based on the N bits from the row address for a memory array, which output from the tracking circuits is used to enable the sense amp enable signal.

Abstract: A method for counting microorganisms present in a biological sample in contact with a culture medium adapted to the growth of said microorganisms, Number NSA of microorganisms present in the sample is determined at a prior stage, Number NSU of microorganisms present at a subsequent stage is calculated according to number NSA. The calculation is based on a model of microorganism growth in the culture medium according to: log(NSU)=?×log(NSA)??×log(CSA)+?, where log is the decimal logarithm, NSU is the calculated number of microorganisms, NSA is the number of microorganisms at the prior stage, CSA is the number of microorganisms at the prior stage divided by the volume of the sample, and ?, ?, and ? are determined parameters depending on the microorganisms, the culture medium, and the time period separating the subsequent stage from the prior stage, ? and ? being positive.

Abstract: A one time programmable (OPT) and multiple time programmable (MTP) structure is constructed in a back end of line (BEOL) process using only one, two or three masks. The OTP/MTP structure can be programmed in one of three states, a pre-programmed high resistance state, and a programmable low resistance state and a programmable very high resistance state. In the programmable low resistance state, a barrier layer is broken down during an anti-fuse programming so that the OTP/MTP structure exhibits resistance in the hundred ohm order of magnitude. In the very high resistance state a conductive fuse is blown open during programming so that the OTP/MTP structure exhibits resistance in the mega-ohm order of magnitude. The OTP/MTP structure may include a magnetic tunnel junction (MTJ) structure or a metal-insulator-metal (MIM) capacitor structure.

Abstract: A semiconductor integrated circuit for selecting one from a plurality of external storage devices and loading an execution program that includes a fuse part having a plurality of internal fuse circuits, and a processing unit that loads the execution program from the external storage device selected according to a value indicated by the internal fuse circuit.

Abstract: A method of obtaining a more accurate estimate of a signal correction parameter(s) in sequencing-by-synthesis operations, such as incomplete extension rates, carry forward rates, and/or signal droop rates. The sequencing operation produces signal data. A model is constructed to simulate a population of template strands as it undergoes the sequencing process and becomes divided into different phase-states as the sequencing-by-synthesis progresses. For example, the model may be a phase-state model. The output from the model is used to adjust the signal correction parameter(s). For example, the model may be fitted to the signal data. This fitting results in a more accurate estimate of the signal correction parameter(s). In another embodiment, the signal droop rate is modeled as a decaying function and this decaying function is fitted to the signal data to obtain an improved estimate of the signal droop rate.

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

Abstract: Nonvolatile memory apparatuses and methods of operating the same. A nonvolatile memory apparatus includes a nonvolatile memory cell array including a plurality of memory cells; an address decoder configured to receive computation data that indicates a computation from among a plurality of computations and an input data for computation, and the address decoder configured to output an address of the nonvolatile memory cell array corresponding to the indicated computation and input data, the nonvolatile memory cell array being configured to output result data stored at the output address, the result data corresponding to a previous computation performed before receipt of the computation data; and a reading unit configured to read the result data output from the nonvolatile memory cell array.

Abstract: A display driver IC with a built-in memory device having a one-time programmable function is provided. The memory device includes: a cell array comprising a plurality of one-time programmable unit cells and configured to receive a writing voltage generated from an internal voltage generating unit to operate upon writing operation; a detecting unit configured to detect a change of the writing voltage; and a controlling unit configured to control the internal voltage generating unit and the unit cells according to an output signal of the detecting unit.

Abstract: A writing circuit includes storage to store writing data to be written to an OTP macro; a controller to apply a first signal that causes the OTP macro to execute writing of the writing data, and apply a second signal that causes the OTP macro to execute reading of data the OTP macro stores; and a comparator to compare the data read from the OTP macro in response to the second signal with the data stored in the storage and output a comparison result, wherein the controller ends a process associated with the writing data if the comparison result indicates a match, and applies the first and second signals again if the comparison result indicates a mismatch.

Abstract: A method of recovering a nucleic acid sequence using a probe map includes: aligning a probe onto a target sequence based on a result in which the probe is hybridized to the target sequence; determining a representative value representing each aligned position of the probe; and recovering a base sequence of the target sequence by using a probe map to which the determined representative values and base sequence information of the probe are mapped.

Abstract: The present invention provides a highly-safe information processing system that is capable of effectively using nucleotide sequence information differences between individual organisms to offer semantic information useful for each individual organism while properly preventing leakage and illegal use of nucleotide sequence information. Further, the present invention includes steps a and b. Step a is performed to acquire either encrypted nucleotide sequence-related information or cryptographic key that corresponds to positional information indicating a position within a nucleotide sequence.

Abstract: Memory programming methods and memory systems are described. One example memory programming method includes programming a plurality of main cells of a main memory and erasing a plurality of second main cells of the main memory. The memory programming method further includes first re-writing one-time programmed data within a plurality of first one-time programmed cells of a one-time programmed memory during the programming and second re-writing one-time programmed data within a plurality of second one-time programmed cells of a one-time programmed memory during the erasing. Additional method and apparatus are described.

Abstract: Systems, methods, and apparatuses for performing a prenatal diagnosis of a sequence imbalance are provided. A shift (e.g. to a smaller size distribution) can signify an imbalance in certain circumstances. For example, a size distribution of fragments of nucleic acids from an at-risk chromosome can be used to determine a fetal chromosomal aneuploidy. A size ranking of different chromosomes can be used to determine changes of a rank of an at-risk chromosome from an expected ranking. Also, a difference between a statistical size value for one chromosome can be compared to a statistical size value of another chromosome to identify a significant shift in size. A genotype and haplotype of the fetus may also be determined using a size distribution to determine whether a sequence imbalance occurs in a maternal sample relative to a genotypes or haplotype of the mother, thereby providing a genotype or haplotype of the fetus.

Abstract: An integrated circuit, that may be a part of an electronic system, may include a first set of storage cells to store settings and a second set of storage cells to store alternate settings. At least one control cell may also be included in the integrated circuit. The at least one control cell may indicate whether to use the settings stored in the first set of storage cells, or the alternate settings stored in the second set of storage cells, to control one or more operating parameters of the integrated circuit. Methods for using the alternate setting are also described.

Abstract: Power management of an embedded dynamic random access memory (eDRAM) using collected performance counter statistics to generating a set of one or more eDRAM effectiveness predictions. Using a set of one or more eDRAM effectiveness thresholds, each corresponding to one of the set of eDRAM effectiveness predictions, to determine whether at least one eDRAM effectiveness prediction has crossed over threshold. In the case that at least one eDRAM effectiveness prediction has crossed over its threshold, transitioning the eDRAM to a new power state. Power management is achieved by transitioning to a power-off state or self-refresh state and reducing the amount of power consumed by the eDRAM as compared to a power-on state.

Abstract: A memory device includes a plurality of read only memory cells, a precharge circuit, and a sense amplifier. A read only memory (ROM) cell of the plurality of ROM cells is coupled to a word line and a bit line. The ROM cell comprises a transistor having a first current electrode coupled to receive a reference voltage, a second current electrode selectively coupled to the bit line based on the programmed state of the ROM cell, and a control electrode coupled to the word line. The precharge circuit is coupled to the bit line. The precharge circuit precharges the bit line to a precharge voltage, wherein the precharge voltage is less than the reference voltage. The sense amplifier is coupled to the bit line and to a power supply voltage terminal for receiving a power supply voltage, wherein the reference voltage is less than the power supply voltage.

Abstract: A read only memory cell circuit is provided. The memory cell circuit includes at least one memory cell. A pair of bit lines associated with each memory cell is provided which form a complementary output. The at least one memory cell is configured to be coupled to first or second of the bit line pair.

Abstract: A memory device includes a memory cell array, a column decoder, and a row decoder. The memory cell array includes a plurality of antifuse memory cells arranged in rows and columns, each of the antifuse memory cells connected to one of a plurality of word lines, one of a plurality of high-voltage lines, and one of a plurality of bit lines. The column decoder is arranged at a first side of the memory cell array and configured to select one bit line among the bit lines. The row decoder is arranged parallel to the column decoder in a first direction, and configured to select one word line among the word lines.

Abstract: In a particular embodiment, an apparatus includes a one-time programmable (OTP) memory circuit configured to be responsive to a programming voltage. The OTP memory circuit includes an OTP memory array including OTP memory cells, a first power switch configured to decouple the OTP memory array from the programming voltage, and a second power switch configured to decouple a subset of the OTP memory cells from the programming voltage.

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for suitable duration of time, a current flows through an OTP element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations.

Abstract: A display driver IC with a built-in memory device having a one-time programmable function is provided. The memory device includes: a cell array comprising a plurality of one-time programmable unit cells and configured to receive a writing voltage generated from an internal voltage generating unit to operate upon writing operation; a detecting unit configured to detect a change of the writing voltage; and a controlling unit configured to control the internal voltage generating unit and the unit cells according to an output signal of the detecting unit.

Abstract: A storage unit for an occupant detection system detecting an occupant based on a magnitude correlation between a detection load value obtained by a load sensor and a threshold value, the storage unit includes a first ROM storing either one of the threshold value and a threshold value specific information for identifying the threshold value, the first ROM being rewritable and a second ROM storing information except for either one of the threshold value and the threshold value specific information, a rewriting of the second ROM being more difficult than a rewriting of the first ROM.

Abstract: A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications.

Abstract: In a particular embodiment, an apparatus includes a one-time programmable (OTP) memory circuit configured to be responsive to a programming voltage. The OTP memory circuit includes an OTP memory array including OTP memory cells, a first power switch configured to decouple the OTP memory array from the programming voltage, and a second power switch configured to decouple a subset of the OTP memory cells from the programming voltage.

Abstract: Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The OTP device has an OTP element coupled to a polysilicon diode. The OTP devices can be used to construct a two-dimensional OTP memory with the N-terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. By applying a high voltage between a selected bitline and a selected wordline to turn on a diode in a selected cell for suitable duration of time, a current flows through an OTP element may change the resistance state. The cell data in the OTP memory can also be read by turning on a selected wordline and to couple a selected bitline to a sense amplifier.

Abstract: Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by e

Abstract: An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P? doped regions. Another N+ doped region, functioning as a bit line, is positioned adjacent and between the two P? doped regions on the substrate. An anti-fuse is defined over the N+ doped region. Two insulator regions are deposited over the two P? doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.

Abstract: Disclosed are a unit cell capable of improving a reliability by enhancing a data sensing margin in a read operation, and a nonvolatile memory device with the same. The unit cell of a nonvolatile memory device includes: an antifuse having a first terminal between an input terminal and an output terminal; and a first switching unit coupled between a second terminal of the antifuse and a ground voltage terminal.

Abstract: Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a mark bit, which indicates that an object is deleted data, and a data bit storage area for storing data, the memory device being built from an OTP memory including an OTP memory block and a pseudo-MTP memory block, the OTP memory block containing a given number of memory sets to operate as an OTP memory, the pseudo-MTP memory block containing the rest of the memory sets operates as a pseudo-MTP memory. The mark bit is written in advance in the mark bit storage area of the OTP memory block.

Abstract: A method and apparatus for searching compressed nucleic acid sequences are disclosed. In the method, a reference sequence is compared with a subject sequence to be encoded, the subject sequence is compressed, an index is created with respect to the reference sequence and the compressed subject sequence, a position corresponding to a query is searched for in the compressed subject sequence using the index, a character found at the position within the compressed sequence is converted into a sequence, and the sequence is output as the response to the query.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement.

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

Abstract: A method of manufacturing a read only memory cell includes connecting electrically a drain of the transistor to the bit line with a first conductor and a via. The method also includes generating a logic zero at a source of the transistor by electrically connecting the source of the transistor to a ground line with the first conductor. Further, the method includes, programming the read only memory cell to logic zero. A method of manufacturing a read only memory cell includes connecting electrically a drain of the transistor to the bit line with a first conductor and a via. The method also includes, connecting electrically a source of the transistor to the drain with the first conductor. Further, the method includes programming the read only memory cell to logic one.

Abstract: A semiconductor memory device includes a memory cell array configured to store data including a verification code; a sensing unit configured to sense the stored data including the verification code; and a verification unit configured to determine whether the sensing unit is able to sense the stored data based on a sensing condition, wherein the verification unit is configured to determine whether the sensing unit is able to sense the stored data based on the sensing condition and a value of the verification code sensed by the sensing unit.

Abstract: In-system repairing or configuring faulty memories after being used in a system are disclosed. In one embodiment, a memory chip can include at least one OTP memory to store defective addresses that are to be repaired. Advantageously, the OTP memory can operate without requiring additional I/O pins or high voltage supplies for reading or programming. The memory chip can also include control logic to control reading or programming of the OTP memory as needed.

Abstract: Methods and devices to detect analyte in body fluid are provided. Embodiments include processing sampled data from analyte sensor, determining a single, fixed, normal sensitivity value associated with the analyte sensor, estimating a windowed offset value associated with the analyte sensor for each available sampled data cluster, computing a time varying offset based on the estimated windowed offset value, and applying the time varying offset and the determined normal sensitivity value to the processed sampled data to estimate an analyte level for the sensor.