Abstract: A clock generator and interrupt bypass circuit for use in reducing the power consumption of the electrical system in which they are implemented. The clock generator provides module clock signals for sequencing modules within the same electrical system, and is capable of generating those module clock signals when in an active mode, and of not generating those module clock signals when in a stand-by mode. The clock generator is further capable of providing a delay of a predetermined length from a request to enter shut-down mode to actual entry into shut-down mode, allowing time to prepare the electrical system for shut-down mode. The interrupt bypass circuit provides a means of leaving shut-down mode in the event that the relevant interrupt requests have been masked.

Abstract: Timing signals are transmitted from reference transmitters through antenna/receivers (antenna preamplifier nodes) to collector nodes (C-Nodes) and to a central computer. The times of arrival of the signals at the various C-Nodes are measured by the C-Nodes, relative to each C-Node's clock. The time of arrival signals at each C-Node must be based upon a common time reference to be useful for positioning. Therefore, the central computer determines the offsets of clocks relative to a selected reference C-Node clock. The time of arrival signals are then calibrated against one another and used to adjust the time of arrival signals so that all time-of-arrivals are relative to the same reference and can be used for position determination and the clocks of the collection nodes are effectively synchronized.

Abstract: A system and method for controlling time-critical functions by dynamically adjusting the interrupt frequency of a microprocessor. Interrupts are generated at a predetermined frequency. Time-critical functions are then performed in response to the interrupts. The interval is adjusted based on timing data from a substantially accurate source. Where the interval is measured in terms of clock pulses, a non-integer number of pulses per interval is attained by varying the number of pulses per interval so that the average over a number of intervals is equal to the non-integer number of pulses per interval. The interval is further adjusted using a selected damping coefficient to eliminate an underdamped condition.

Abstract: A clock stoppage detector and a selector selection determining circuit are provided on each of a plurality of circuit boards. If any abnormality is detected in the clock selected in accordance with selector control information supplied from a clock selection controller provided common to the plurality of circuit boards, the selector selection determining circuit changes the selection independently of the selection control information. The selector selection determining circuit also performs clock selection independently when failure occurs to the clock selection controller.

Abstract: An improved system for providing ensemble time from an ensemble of oscillators is provided. The improved system provides an ensemble time definition whose large number of possible solutions for an ensemble time are constrained to a limited number of solutions. In one embodiment, a substantially infinite number of solutions is constrained to a single solution.

Abstract: A system for operating a pair of microprocessors with independent system clocks while at the same time providing synchronization by a common interrupt signal, and in which the system clocks are cross-monitored to thereby provide Fail-Safe operation.

Abstract: A master clock generator for a variable speed constant frequency electric power system includes a frequency select circuit for selecting an external or internal frequency reference signal and a phase comparator for producing a phase error signal representative of the phase difference between the frequency reference signal and an output clock signal. The phase error signal is combined with a control signal to produce an adjusted phase error signal. This adjusted phase error signal is integrated and a voltage control oscillator is used to produce the output signal in response to the integrated adjusted phase error signal. The control signal introduces a desired phase error between the reference signal and the output signal. Clamping circuits are provided to limit the maximum and minimum magnitudes of the integrated adjusted phase error signal, thereby limiting the maximum and minimum frequencies of the output clock signal.

Abstract: A device and method provide for an accurate output from a unit, such as an oscillator and/or clock providing an output indicative of frequency and/or time. The device includes a processing section having a microprocessor that develops a model characterizing the performance of the device, including establishing predicted accuracy variations, and the model is then used to correct the unit output. An external reference is used to provide a reference input for updating the model, including updating of predicted variations of the unit, by comparison of the reference input with the unit output. The ability of the model to accurately predict the performance of the unit improves as additional updates are carried out, and this allows the interval between the updates to be lengthened and/or the overall accuracy of the device to be improved. The accuracy of the output is thus adaptively optimized in the presence of systematic and random variations.

Abstract: A clock producing apparatus for a D/A converter switches the clocks in accordance with the inputted sampling frequencies. A deterioration in the S/N caused by unnecessary spectra which are caused by the inputting of different sampling frequencies is prevented.The selecting operation is effected by the selecting circuit so as to obtain the selected input sampling frequencies, and at the same time, the clock signals are prevented from being inputted to the frequency dividing circuits corresponding to the input sampling frequencies which are not selected. Therefore, unnecessary spectra are prevented from being generated.

Abstract: A method of adjusting the pulse rate of a local clock (1) by generating a first pulse train at a first predetermined rate, dividing the pulse train by a divisor (3) to produce a second pulse train. The value of the divisor (3) is selected (4,5,6) so that the rate of the second pulse train is adjusted within a predetermined range.

Abstract: The Harmonic Optical Oscillator is a solid state clock on a microchip. Two solid state lasers of nearly identical frequency transmit beams into an optical waveguide. The two beams interfere with each other causing a modulation of the light amplitude in the waveguide. A light detector picks up the harmonic beat. Accuracy of at least 1/2 second a year (approximately 200 times better than today's quartz microchips) is expected.

Abstract: A digital locked loop which can act as a slave clock. The digital loop is able to monitor a master clock signal and adjust its own output to accurately track the frequency of the master clock signal. In addition, the digital loop can generate a highly accurate timing signal in the absence of the master clock. An oscillator supplies a signal having a fixed frequency to a digital synthesizer. The synthesizer treats the oscillator frequency as a known standard. The synthesizer uses that standard to generate an output signal with a different frequency. The frequency of the output signal is chosen so that it is equal to a frequency supplied by an external master clock. The present invention utilizes a digital feedback loop to detect any phase shift between the output signal and the master clock signal. The presence of any phase shift indicates that the frequency of the master clock signal has changed.

Abstract: An atomic clock of the type comprising a quartz oscillator, a tube contaig a material, the atoms of which have an hyperfine spectral transition, control means capable of generating, from the quartz oscillator, a control signal of a frequency that corresponds to the hyperfine spectral transition, and of applying this control signal to the tube to cause interaction between this signal and the atoms of the material contained in the tube, and feedback means that are sensitive to the response of the tube and are adapted to modifying the frequency of the quartz oscillator so as to substantially center the frequency of the control signal on the frequency of the hyperfine spectral transition, wherein the control means are adapted to cyclically generate test signals, the controlled frequency of which is located outside the Ramsey peak.

Abstract: A counter/timer circuit for a microcontroller includes a central register and two auxiliary registers each having transfer outputs and counting inputs. Bistable output storage elements are each connected to a respective one of the transfer outputs. Interrupt request flags are also each connected to a respective one of the transfer outputs. Start/stop elements are each connected to a respective one of the counting inputs. Input control blocks are each connected to a respective one of the start/stop elements. First reload, capture and compare units are connected between one of the auxiliary registers and the central register, and second reload, capture and compare units are connected between the other of the auxiliary registers and the central register.

Abstract: Method for manufacturing a timepiece stepping motor comprising the steps of: providing a flat one-piece stator member defining an opening for the rotor and having a pair of diametrically opposed narrow sections on either side of the opening; providing a movement frame having stator locating projections and defining a pair of holes larger than the narrow sections and extending through the movement frame; locating and attaching the stator to the frame with the narrow sections spanning the holes in the frame; cutting through the narrow sections with a laser to sever the stator into two members, utilizing the holes in the frame to dispose of vaporized metal from the stator; encapsulating and re-joining the severed sections with a plastic fixation; and attaching a coil core assembly to the stator members and in magnetic circuit therewith.

Abstract: A directional starting spring which ensures that an AC synchronous motor is rotating in the proper direction is disclosed. The AC synchronous motor includes a circular magnet rotating in "synch" with the frequency of the alternating current. The magnet rotates a worm gear attached to the center on its axial face. This worm gear drives a second worm gear positioned perpendicular to the first worm gear. The second worm gear drives a series of gears which display the elapsed time. Attached to this second worm gear is the directional starting spring. If the motor is rotating in the proper direction the spring contacts the housing of the meter and slides on the second worm gear. If the motor is rotating in the wrong direction the spring contacts the axial face of the magnet stopping the rotating magnet and pushing it in the proper direction.

Abstract: A microcontroller, software-based time-of-day clock compensates for inaccurate oscillator frequency by periodically correcting the time-of-day value using a calibration offset measured by manufacturing test equipment and permanently stored in nonvolatile memory. A high degree of time keeping accuracy is achieved without the use of trimming capacitors or presorted piezoelectric crystals in the oscillator. Furthermore, frequency error compensation is incorporated into the microcontroller system without requiring a significant amount of processing time overhead.

Abstract: A timer which can be used to provide interrupt signals at predetermined but variable periods for multi-tasking microcomputers or serial data acquisition in pagers comprises a plurality of modulo counters. Each modulo counter has selectable clock inputs and has an output coupled via switches to a NOR gate and to the other modulo counters. Programmable configuring means control the switching means to configure the counters so as to produce desired outputs at the logic gate. The configuring means can also reset the modulus of the modulo counters to any desired value. Thus, the timer produces variable interrupt signals with little or no overhead processor time.

Abstract: A clocking device of substantially constant stability for short-term and long-term measurements. This clocking device comprises first generators of a clocking signal with substantially constant stability for short-term measurements, and second generators of a clocking signal of constant stability for long-term measurements. Means for the automatic locking of one of the said first or second clocking signals to the other clocking signal are provided, and enable the automatic frequency and/or phase locking of said signals. The automatic locking means have a time constant corresponding to the transition zone between the short-term and long-term measurements. The device can be applied in the high-precision time-measuring instruments industry and to air and space navigation instruments.

Abstract: A clock voltage supply for electronic control circuits such as a computer system for generating four clock signals which are synchronous as to frequency and phase. When n=4, the clock signals are generated with the help of four PLL clocks. So that the four clock signals can continue to appear even if one of the four clocks is malfunctioning, the clock signals of the four clocks are supplied to four (3:4) voters from whose outputs the clock signals are then supplied. Since each voter circuit brings about a certain delay time, which significantly limits the frequency of the clock signals, a delay element is connected downstream to each of the voter outputs respectively. The delay time of the respective delay element, plus the delay time of the respective voter connected therewith, is an integral multiple of the period of the intended clock frequency. For PLL control, the output of each delay element gives the nominal phase position and the output of each clock gives the actual phase position.

Abstract: An AC line signal of unknown frequency is compared to a signal of known reference to determine the frequency of the AC line signal. Thereafter, the AC line frequency signal is used as a time-base for keeping real time.

Abstract: A fundamental interval of time is derived from a clock signal of an inherent frequency emanating from an untrimmed crystal oscillator. Firmware and hardware of the time-of-day clock system are used to control and modify the time interval between interrupt signals generated upon the occurrence of a specified count of clock cycles of the clock signals emanating from the crystal oscillator.

Abstract: The randomly-generated energy produced by decay of a radioactive source is utilized to generate timing signals for horologic and chronographic instruments such as electronic watches, clocks or chronometers. The radioactive source is implanted by ion implantation or diffusion in or near the depletion region of a P-N junction semiconductor device which may be integrated on a common semiconductor substrate with the electronic timekeeping circuitry of the horologic or chronographic instruments. Individual pulses due to beta radiation produced in the depletion region causes electron migration from the P to the N region of the device and produces electrical pulses. These pulses are amplified and counted until a preselected count is reached. When such count is reached, the timekeeping circuitry is stepped by one second or some convenient fraction thereof.

Abstract: A periodic signal, at the frequency of the AC mains supply voltage, contains signal pulses, each having a duration that is substantially shorter than half the period of the AC mains supply voltage. The periodic signal is coupled to a high frequency transformer to form a periodic output signal that is applied to a time-of-day measurement circuit that provides time-of-day display information for a television receiver. The transformer provides conductive isolation between the time-of-day measurement circuit and the AC mains supply voltage source.

Abstract: An analog electronic timepiece wherein oscillation of the oscillator circuit is stopped when the watch is placed into a reset mode. This lowers power consumption and provides for greater battery life during shipping and stocking periods. In one embodiment of the invention the oscillator is stopped immediately upon placing the watch into a reset mode. In another embodiment of the invention, cessation of oscillation does not occur until a predetermined delay after reset.

Abstract: A laser clock includes a linear laser in one embodiment of the clock and a ring laser gyro in the other embodiment. The linear laser is frequency stabilized and utilizes a single active medium in the form of a low pressure gas, such as He-Ne, with a Doppler broadened gain curve. The ring laser gyro is a four frequency laser with a Faraday rotor. Detector and electronic circuitry associated with the laser of each embodiment detect a beat frequency and converts it to a clock signal.

Abstract: A writable non-volatile memory circuit for use in portable electronic devices such as electronic timepiece, wherein there is improved the power consumption and there is provided a volatile memory with a serial input for writing the data into the non-volatile memory and for checking the data.

Abstract: An electronic timepiece has a reference signal generator for generating a 1/10 seconds reference signal which is fed to a static counter which counts the 1/10 seconds reference signal and produces a reference count signal. A read only memory stores a system program which executes and controls a time count. An arithmetic and logic unit executes the time count and a random access memory stores the time counting data. A bidirectional data bus line is connected between the random access memory and the static counter, and a decoder is connected to the bidirectional data bus line for decoding the contents of both the random access memory and the static counter and providing corresponding decoded time data signals. A display device responds to the decoded time data signals and indicates the contents of the random access memory and the static counter.

Abstract: A control circuit for driving an electric motor at a substantially constant speed, the motor including a rotor with at least one pair of permanent magnetic poles and a stator provided with a first and second coil, the control circuit including a control element for supplying energizing pulses to the coils dependent upon a detected rotor speed, the control element having a normal speed mode wherein the rotor speed is detected by the first coil and wherein only the second coil is supplied with energizing pulses at a frequency corresponding to single coil driving and a self-starting mode wherein the energizing pulses are supplied alternately to the first and second coils to accelerate the rotor to a desired speed, the control element including rotor acceleration and braking circuitry operable during the normal speed mode and including a desired frequency pulse generator, an actual frequency pulse generator, a phase comparator for comparing the widths and phases of the desired and actual frequency pulses, and an

Abstract: An earring watch comprises an enclosure 4 with a friction clip or pierced-earlobe hook for attachment to the ear. The enclosure contains an energy cell 18, a timekeeping circuit 42-46-48 and an audio transducer 40 for announcing the time in a series of groups of tones, the number of tones in each group equal to a respective digit of the time. The time is announced when the wearer touches one part of the surface of the enclosure twice, another part 6 of the enclosure is electrically connected to the body via the ear, so that the touch completes a circuit between the two parts of the enclosure. Preferably, and to avoid false readouts due to an inadvertent touch, the watch contains circuitry for providing a time readout only if it is touched twice within a predetermined interval.

Abstract: A plug-in electronic clock being operated either by a commercial power source in a normal state or by a D.C. power source in case of a power failure, said electronic clock having means for generation of a pulse train used for a computation of time information in case of a power failure and means for stopping generation of the said pulse train in a case where the commercial power is active so as to prevent interference noise against radio receivers or television receivers, with a correct time information computation being assured when the commercial power source is recovered.

Abstract: This control device is used in connection with a motor comprising a magnetic rotor and at least two magnetic stator circuits coupled with respective coils (b.sub.1,b.sub.2). A logic circuit (21) is arranged to alternatively feed drive pulses to both coils and to connect the coil which is not fed to a detection circuit (24, 25) the output of which is connected to the logic circuit in order to determine the duration of a feed pulse or to trigger a new feed pulse. This control device allows the current consumption of the motor as well as the locking torque to be reduced, since the servo control obtained insures the rotor positioning in case an important disturbance should occur.

Abstract: An electronic timer having an oscillator, a counter which counts outputs of the oscillator up to a predetermined count value and thereupon generates an output, and an output circuit for generating an output signal in response to the output from the counter, the oscillator comprisinga first terminal for connection with a time constant circuit consisting of a resistor and a capacitor,a second terminal supplied with a reference voltage,a dividing resistance circuit for developing a first upper limit voltage and a lower limit voltage,a first upper limit comparator for comparing a potential at the first terminal with the first upper limit voltage,a second upper limit comparator for comparing the potential at first terminal with the reference voltage,an OR-circuit for receiving outputs from the first and second upper limit comparators,a lower limit comparator for comparing the potential at the first terminal with the lower limit voltage,a flip-flop which is set by an output from the OR-circuit and reset by an outpu

Abstract: An electronic timepiece including a time-base signal source having a quartz vibrator operating at a frequency of 1 MHz or higher, and a multi-stage divider. At least one stage of the divider is comprised of a static induction transistor logic inverter (SITL inverter), which includes a static induction transistor (SIT) and a bipolar load transistor, operating at a bias voltage of or less than 0.5 volts. The time-base signal source may comprise an oscillator circuit which also includes a static induction transistor.

Abstract: An electronic timer wherein a counting circuit for counting outputs of a CR oscillating circuit comprises a plurality of partial counting circuits which are cascade-connected with one another, the respective partial counting circuits are automatically reset by an automatic resetting circuit when a source current voltage is applied or reset by an external resetting circuit at a desired time, the outputs of the CR oscillating circuit are counted by the respective partial counting circuits after the resetting, and a following output circuit is driven when the count reaches an externally set value of a setting circuit. The partial counting circuits are divided into groups by an external driving test circuit to quickly test the operation of the counting circuit.

Abstract: A power source supply system uses an electric cell power source whose output voltage is 3 V, and drops the output voltage of 3 V to 1.5 V by a first voltage drop circuit and further drops the voltage of 1.5 V to 0.75 V to operate a logic circuit at the dropped voltage of 0.75 V.

Abstract: An electronic timepiece having multi-functions comprises a quartz oscillation circuit as a time standard signal generating circuit, a dividing circuit for dividing the output signal of said quartz oscillation circuit, a timing pulse generating circuit for generating a timing pulse signal which operates many kinds of circuit blocks as an input signal of one part of the output of said dividing circuit, a ROM-circuit as a program memory for executing multi-function operations of the timepiece and others, a program counter and page counter for renewing an address of said ROM-circuit, a RAM-circuit as a data-memory for memorizing a controlling memory, an operated result and a time information, an operation circuit for executing many kinds of operations, a data comparison and a data transformation, a latch circuit as an output data memory circuit for temporarily memorizing a display data or other necessary output data, a driver circuit for displaying all of or a part of the contents of said latch circuit, an alarm

Abstract: An electronic wristwatch without mechanically driven hands has an electromagnetic output which is sensed for measuring the timing rate. A modulated signal applied to the coil of an alarm sounding device produces the electromagnetic field for sensing. The display is fully illuminated while timing in order to eliminate stray electric fields.

Abstract: An electronic timepiece comprising means to appreciably increase the number of distinctive information which can be introduced and, if necessary memorized, for a given number of terminals intended for that purpose, information needed for the adjustment of the frequency. The integrated circuit of the timepiece is provided with a first group of m terminals and it comprises an introduction circuit having inputs reserved to introduce the desired information, these inputs being connected to a second group of n terminals of the integrated circuit. The introduction circuit has also control inputs and each of the n terminals of the second group is capable to be connected, by a connection external to the integrated circuit, with one of the m terminals of the first group. The introduction circuit is arranged in such a way as to deliver to its outputs, at least periodically, one distinctive information for each of the m.sup.n possible combinations of the mentioned connections.

Abstract: In an electronic timepiece powered by a lithium battery, a voltage control system is provided whereby a supply voltage of approximately one half of the battery voltage is supplied to certain portions of the timepiece circuit under normal operating conditions, but whereby cessation of operation by the timebase oscillator circuit of the timepiece due to some abnormal state such as excessively low ambient operating temperature is automatically detected and a changeover is made to supply of the full battery voltage to all of the timepiece circuitry. Upon recovery of operation of the timebase oscillator circuit, changeover to the low voltage supply state is performed.

Abstract: A rapid start oscillator latch circuit for avoiding long start up time while maintaining minimum operating power for a crystal oscillator in an electronic watch. The oscillator is operated at a relatively high gain immediately after power is applied and until the oscillator is running, after which the oscillator is caused to operate under the normally preferred conditions. A power up pulse sets a latch and the latch is reset by either a pulse from the prescaler or a manual input. When the latch is set, the oscillator circuit is modified for quick start-up. After the oscillator is running, it activates the prescaler, and after several cycles of clock inputs to the prescaler, an output from the prescaler or a manual input resets the latch and the oscillator is returned to its normal operating condition.

Abstract: In an electronic timepiece having a quartz crystal controlled standard frequency oscillator and a device which temporarily imposes a heavy load on the battery when activated, means are provided for changing a value of a circuit constant in the oscillator circuit, such as capacitance or resistance, when the load device is activated. This change in circuit constant value serves to decrease the value of the minimum battery supply voltage below which the oscillator circuit ceases to function, thereby ensuring reliable operation of the oscillator circuit when the timepiece battery voltage drops due to current being supplied to the load device.

Abstract: A electronic timepiece having a dynamic frequency divider, a static frequency divider and a reset system, in which a switching means is provided in the voltage supply circuit of the dynamic frequency divider and a gate means is provided between the dynamic frequency divider and the static frequency divider. The switching means is a transistor adapted to be cut off to stop the operation of the dynamic frequency divider in the reset state and the gate means is a digital logic gate adapted to fix the output thereof by an input voltage applied by the reset system, whereby power consumption in the dynamic frequency divider and in the static frequency divider may be reduced.

Abstract: A system for fastening the coil of a step-by-step motor in an electric or an electronic watch.It is characterized by the fact that one or both pole pieces 4 and 4' of the coil 2 have extrusions 10 and 11 of cylindrical shape which extend perpendicular to the plane of the pole piece 4 and are intended to be introduced into corresponding boreholes in the substrate of the printed circuit 1.This arrangement is advantageous since the extrusions can be produced by stamping before the heat treatment of the pole pieces, which eliminates the stresses which might, upon the mounting of the coil, destroy the magnetic qualities of the materials.

Abstract: An electronic timepiece includes a primary timepiece circuit unit including a frequency supply for providing a relatively high frequency signal, a frequency converter responsive to the relatively high frequency signal to provide a relatively low frequency time unit signal, timing signals, and a plurality of word pulses indicative of a plurality of data words representing time data concerning the current time, and a set of additional data other than the time data, a timekeeping register arranged to store the time data and the additional data, and display elements for displaying the time data and the additional data. A secondary timepiece circuit unit includes a register arranged to store the additional data to be transferred to the timekeeping register.

Abstract: In an electronic timepiece, a system for producing a unit time signal with a high degree of frequency stability, composed of a low frequency oscillator, a high frequency oscillator of a high degree of frequency stability which is activated only during periodic short intervals, and means for producing a timebase signal which is an exact integral submultiple in frequency of the high frequency oscillator signal, by modifying the output signal from the low frequency oscillator on the basis of periodically recurring phase coincidence between the high and low frequency oscillator signals. Information on this phase variation is stored in digital form, and is utilized to correct the low frequency signal during periods when the high frequency oscillator is inactivated.

Abstract: A system for performing frequency division of a high frequency signal by intermittent operation of a frequency dividing counter circuit and by a phase lock loop circuit, in which phase lock is periodically achieved with an output of the counter circuit. Phase lock loop circuit is of novel design which provides exact phase lock without cyclic variations from the reference phase.

Abstract: A quartz oscillation circuit used for a time standard of an electronic timepiece, which includes an inverter operating as an amplifier, an input capacitor and an output capacitor, the capacitors having the opposite temperature characteristics to compensate changes in oscillation frequency with the variation of temperature without any increase of the power consumption.