By Interpolating Or Maximum Likelihood Detecting Patents (Class 369/59.22)
  • Patent number: 7778133
    Abstract: An optical information recording/reproducing apparatus is adapted to record and/or reproduce multilevel information on/or from an optical information recording medium. The multilevel information is recorded in the form of pits in cells virtually formed at regular intervals on a track. The respective levels are represented by varying the length or the area of information pits such that a reproduced signal has a different amplitude level depending on the length or the area of information pits. A reproduced signal correction circuit corrects a reproduced signal obtained by performing sampling at the center of each cell. An error power calculation circuit calculates error power on the basis of the difference between the corrected reproduced signal and an ideal value of each level of the cell. A decoder performs decoding on the basis of the calculated error power values.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: August 17, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kaoru Okamoto, Jun Sumioka, Masakuni Yamamoto
  • Patent number: 7773481
    Abstract: In a recordable optical disc apparatus, the efficiency of the work necessary for optimizing the write pulse condition (write strategy) is improved and the read compatibility among drive units is ensured by a minimum addition of circuitry. An edge shift amount or a read signal and a binarized result are stored in an external memory as digital data and are later processed by analysis software in a host PC. The write pulse shape and power conditions can be optimized to individual optical disc media in a short time by means of a simple circuit. Further, by optimizing the write pulse shape and power condition in view of the PRML class or the difference in NA of the head, any deterioration of read compatibility can be avoided.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: August 10, 2010
    Assignees: Hitachi, Ltd., Hitachi-LG Data Storage, Inc.
    Inventor: Hiroyuki Minemura
  • Publication number: 20100188953
    Abstract: In a recording/reproducing system that performs PRML decoding, a suitable evaluation value for setting a recording condition can be obtained with a simple structure. It is assumed that a value corresponding to a difference between a difference metric between a maximum likelihood path for an equalized signal that is fed to maximum likelihood decoding processing and a path in a bit-advanced shift direction and a difference metric between the maximum likelihood path for the equalized signal and a path in a bit-delayed shift direction is a signal quality evaluation value dSAM. Further, the signal quality evaluation value dSAM is calculated using an equalization error value ek which is an error between an equalized signal value fed to the maximum likelihood decoding processing and an ideal equalized signal value determined from a decoded signal obtained as a result of the maximum likelihood decoding processing.
    Type: Application
    Filed: August 2, 2007
    Publication date: July 29, 2010
    Applicant: Sony NEC Optiarc Inc.
    Inventor: Mitsugu Imai
  • Patent number: 7764749
    Abstract: Phase trackers (7) for tracking phases of received data are provided with interpolators (20), error detectors (21,22), combiners (25) and indicator generators (26) for generating at least two streams of interpolated samples, for generating error signals per stream, and for generating an indicator signal for adjusting the interpolation, to avoid the use of sync words for phase tracking. The indicator generator (26) converts combined error signals into indicator signals for adjusting the interpolation through shifting sampling phases of interpolated samples.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: July 27, 2010
    Assignee: NXP B.V.
    Inventor: Arie Geert Cornelis Koppelaar
  • Publication number: 20100177615
    Abstract: In a maximum likelihood decoder, when undersampling occurs, selectors 205 to 207 do not select branch metrics from branch metric calculation sections 202 to 204 but select a value “0”, and a path metric calculation section 208 calculates a path metric based on the value “0” selected by the selectors 205 to 207, while calculating a path selection signal. An input signal wsdt_d, which is input to the branch metric calculation sections 202 to 204 and which is subjected to maximum likelihood decoding, is adjusted, with consideration given to the time of the occurrence of the undersampling at which the selectors 205 to 207 select the value “0”, so as to be a signal delayed by the number of clocks corresponding to that occurrence time. Thus, correct decoding results are obtainable even when the undersampling occurs, thereby ensuring proper operation.
    Type: Application
    Filed: October 15, 2007
    Publication date: July 15, 2010
    Inventor: Akira Yamamoto
  • Patent number: 7751507
    Abstract: A circular Viterbi decoder is capable of improving a data decoding speed without being limited by a sampling speed of a sampling and holding circuit. An analog Viterbi decoder includes: a clock divider which generates a plurality of clock signals by dividing a clock frequency of an externally-input clock signal, a plurality of sampling and holding units which sample and hold input analog data according to the clock signals generated from the clock divider, and a multiplexer which sequentially and alternately outputs the analog data sampled and held by the sampling and holding units.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: July 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-rak Son, Hyun-jung Kim, Hyong-suk Kim, Jeong-won Lee
  • Patent number: 7751295
    Abstract: Quantization noise due to analog-to-digital conversion may be larger than a noise component of an input signal, and therefore sufficient performance may not be obtained.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: July 6, 2010
    Assignees: Hitachi, Ltd., Hitachi LG Data Storage, Inc.
    Inventor: Manabu Katsuki
  • Patent number: 7746749
    Abstract: An apparatus and method for look-ahead data detection are provided, the apparatus including a boundary function generator, a boundary decision unit in signal communication with the boundary function generator, a next state generator in signal communication with the boundary decision unit, and a sample value generator in signal communication with the boundary decision unit; and the method including receiving a pickup signal sensed from an optical disc, providing a boundary function value responsive to the pickup signal, comparing the boundary function value with a programmable register value, generating decision outputs responsive to the boundary function value with combinational logic, generating a next state and detected data responsive to the decision outputs, and generating a detected sample value responsive to the decision outputs.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: June 29, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Gene Sonu
  • Patent number: 7715295
    Abstract: An optical disc reproducing apparatus includes an A/D converter; an asymmetry compensator for detecting 4T sampling signals; a phase locked loop including a frequency detector that counts and detects run-length signals from the digital signals and compensates frequency errors of the digital signals; a binary module including a Viterbi decoder, a slicer, and a minimum T compensator that compensates the digital signal with a minimum signal having a unit cycle; an equalizer; an adaptive level error detector detecting a base level of the Viterbi decoder from both an input signal into the equalizer and an output signal from the Viterbi decoder, and computing a filtering coefficient of the equalizer from the base level; and a signal quality measurer measuring a jitter or an SbER of the digital signal.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: May 11, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Hyun Lee, Eing Seob Cho, Eun Jin Ryu, Jun Jin Kong
  • Publication number: 20100103791
    Abstract: An offset corrector of an information readout apparatus receives a digital signal DRF output from an A/D converter, and performs offset correction. The offset corrector is capable of switching between a level-correction operation that corrects the offset so that the DC level of the shortest period signal included in the readout signal assumes a zero amplitude reference and a HPF operation that matches the level of the readout signal with the zero amplitude reference. The offset corrector corrects the offset in the level correction operation during a normal reproduction, and switches to the HPF operation for offset correction when a defect judgment unit detects a defective area. The information readout apparatus is stable and has a superior performance without a symmetry deviation if there occurs a waveform fluctuation caused by a defect etc.
    Type: Application
    Filed: January 25, 2008
    Publication date: April 29, 2010
    Inventor: Hiromi Honma
  • Patent number: 7697640
    Abstract: A method for bit recovery in a data channel includes the steps of: inputting a read channel signal, providing a main signal processor for adaptive bit recovery from the read channel signal, providing an auxiliary signal processor for bit recovery from the read channel signal, using an output of the auxiliary signal processor for adaptation of the main signal processor, and outputting a recovered binary bit stream.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: April 13, 2010
    Assignee: Thomson Licensing
    Inventors: Stefan Rapp, Axel Kochale
  • Publication number: 20100039912
    Abstract: An equalizer (22) performs a PR equalization of a reproduced signal waveform output from an A/D converter (21). A reference-waveform generation unit (42) generates a reference reproduced-waveform based on a recording data train estimated from the reproduced signal waveform by a recognition unit (30). An equalization-error calculation unit (43) calculates an equalization error between the reference reproduced-waveform and the reproduced signal waveform. A transient equalization-error detector (44) extracts equalization error information, as a transient equalization error, at the time instant at which the reference reproduced-waveform assumes a specific level, and at which the specific level-value and a level-value of the reference reproduced-waveform at one channel clock before or after the time instant satisfy therebetween a specific relative relationship. The extracted transient equalization error is used as an index showing the quality of the recorded mark.
    Type: Application
    Filed: September 11, 2007
    Publication date: February 18, 2010
    Inventors: Masaki Nakano, Masatsugu Ogawa, Masaru Nakamura
  • Patent number: 7660224
    Abstract: A loss of performance of slicer adaptation at high capacities due to the mismatch between the exact bits used in the computation of the RDS for the DC-control on the one hand and the often erroneous threshold decisions that are preliminarily made based on the HF waveform on the other hand, is resolved by performing a new method of DC-control at the encoder: the RDS is modified such that it is not based on the exact channel bits, but on the threshold decisions from a synthetic HF signal waveform that is generated based on a nominal MTF (modulation transfer function) or its IRF (impulse response function) of the channel. In this way, the impact of the erroneous threshold decisions in the receiver are already taken into account at the encoder, and the slicer control is no longer negatively affected thereby.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: February 9, 2010
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Willem Marie Julia Marcel Coene, Bin Yin
  • Publication number: 20100008201
    Abstract: A demodulation method comprises the steps of performing branch metric computation on each of columns of a modulation symbol; calculating column path metrics that are respective path metrics of column state values of modulation symbols; and calculating symbol path metrics that are respective path metrics of symbol state values of the modulation symbols.
    Type: Application
    Filed: March 20, 2007
    Publication date: January 14, 2010
    Applicant: PIONEER CORPORATION
    Inventors: Michikazu Hashimoto, Kiyoshi Tateishi
  • Patent number: 7646686
    Abstract: A recording/reproduction apparatus, comprising a first recording section for recording test information onto a medium using at least one recording power, a reproduction section for reproducing at least one test signal indicating the test information from the medium, and a second recording section for recording information onto the medium using one of the at least one recording power. The reproduction section comprises a decoding section for performing maximum likelihood decoding of the at least one test signal and generating at least one binary signal indicating a result of the maximum likelihood decoding, a calculation section for calculating a reliability of the result of the maximum likelihood decoding based on the at least one test signal and the at least one binary signal, and an adjustment section for adjusting a recording power for recording the information onto the medium to the one recording power based on the reliability.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: January 12, 2010
    Assignee: Panasonic Corporation
    Inventors: Harumitsu Miyashita, Takeshi Nakajima, Mamoru Shoji, Yasumori Hino
  • Patent number: 7636287
    Abstract: Reproduced signals are equalized by the least square technique by using a predetermined number of data samples binarized by a Viterbi decoder. Even when data written on an optical disk is unknown, the data can be equalized in a stable manner and can be reproduced at a low error rate without instability factors such as divergence due to interference.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: December 22, 2009
    Assignees: NEC Corporation, Kabushiki Kaisha Toshiba
    Inventors: Shuichi Ohkubo, Hiromi Honma, Masatsugu Ogawa, Masaki Nakano, Toshiaki Iwanaga, Yutaka Kashihara, Yuji Nagai, Akihito Ogawa
  • Patent number: 7616547
    Abstract: A high-speed mixed analog/digital PRML data detection and clock recovery apparatus and method. The high-speed mixed analog/digital PRML data detection and clock recovery apparatus includes a variable gain amplifier, an analog equalizer, an analog-to-digital (A/D) converter, a DC offset remover, a level error detector, a Viterbi decoder, and an adaptive digital controller. The adaptive digital controller separately stores the level error values by predetermined frequencies, calculates predetermined coefficient values by each frequency component based on the level error values, and D/A-converts and applies the calculated predetermined coefficient values to the variable gain amplifier and the analog equalizer.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: November 10, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-won Lee, Jung-hyun Lee, Jae-wook Lee, Jung-eun Lee, Konakov Maxim
  • Patent number: 7609600
    Abstract: Recording is started in an INC mode at the time of start of initial data recording (step S1). Next, it is determined whether recording onto an unrecorded region is possible in the INC mode (step S2). If it is determined that the recording is impossible, next, temp lead-out is recorded at a last portion of a recording region (step S4). Then, a recording mode for format 2 RMD is changed (step S5). Next, format 3 RMD is newly created, and is recorded in RMD in a management region (step S6). Then, the recording is restarted in a ROW mode (step S7).
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: October 27, 2009
    Assignee: Funai Electric Co., Ltd.
    Inventor: Tsuyoshi Kamitani
  • Patent number: 7599270
    Abstract: A wobble signal for an optical storage device is generated by adjusting a center frequency (?0) of a band pass filter based on an expected frequency of the wobble signal and/or an estimated position of a pick-up apparatus and filtering an input signal corresponding to the wobble signal from the pick-up apparatus with the adjusted band pass filter to provide the wobble signal. Adjusting the center frequency (?0) of the band pass filter may also be based on a measured phase change of the band pass filter. Systems for generating a wobble signal, wobble signal detection circuits and optical storage devices are also provided.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: October 6, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Woo-Kang Jin
  • Patent number: 7573794
    Abstract: A defect detection device, apparatus, and method for detecting a defect of data recorded on a recording medium. The defect detection device includes a waveform state detection part generating information representing a state of a waveform of a reproduced signal from the recording medium based on soft decision results obtained in a process of reproducing the data in accordance with a maximum likelihood decoding algorithm corresponding to a partial response. The defect detection device includes a defect determination part determining the defect of the recorded data based on the information generated in the waveform state detection part.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: August 11, 2009
    Assignee: Fujitsu Limited
    Inventors: Toru Fujiwara, Masakazu Taguchi
  • Patent number: 7567491
    Abstract: A bias loop is provided for automatic threshold level adjustment in data detectors, such as a slicer detectors or threshold detectors. The bias loop monitors characteristics of the data detector's output, such as its digital sum value, to generate a signal correction term, which is used to adjust the detector's input. Alternatively, the bias loop may adjust the data detector's actual threshold value.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: July 28, 2009
    Assignee: Marvell International Ltd.
    Inventors: Mats Oberg, Christopher Painter
  • Patent number: 7564754
    Abstract: A disk apparatus that includes: a first determining unit that determines whether the maximum value of an amplitude of an RF signal is a first reference level or more and the minimum value of the detected amplitude of the RF signal is a second reference level or less; a counting unit that counts the number of detected times of CAPA areas according to the determining results of the first determining unit; a second determining unit that determines whether the optical disk has been rotated a given amount or not; a third determining unit, when the optical disk has been rotated a given amount, determines whether the number of detected times of CAPA areas is at least equal to or larger than a given number of times or not; and a fourth determining unit that distinguishes the kind of the optical disk according to the determining results of the third determining unit.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: July 21, 2009
    Assignee: Funai Electric Co., Ltd.
    Inventor: Masaki Matsumoto
  • Patent number: 7561503
    Abstract: A clock generating circuit includes: a clock data extracting circuit extracting a clock data signal from a wobble signal detected from an optical disc by passing frequencies around a central frequency, which is changed responsive to the frequency of the wobble signal according to a control signal; and a signal generating circuit generating a recording clock signal, from the clock data signal, having a frequency proportional to a frequency of the wobble signal. An optical disc apparatus incorporates the clock generating circuit.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: July 14, 2009
    Assignee: Ricoh Company, Ltd.
    Inventor: Isamu Moriwaki
  • Patent number: 7558177
    Abstract: After a playback RF signal 3 detected from an optical disc medium 1 is waveform-shaped, it is converted into a digital RF signal 6 with a sampling clock 8 having a cycle twice as long as a channel clock. Thereafter, a first offset correction circuit 9 corrects an offset fluctuation in a high frequency band, and a digital adaptive equalizer 23 performs adaptive equalization, and then a second offset correction circuit 27 corrects an offset component that remains after the offset correction by the first offset correction circuit 9, thereby demodulating a digital binary signal 37. Therefore, even when high-speed playback is carried out and an asymmetry depending on the recording quality is large, a reduction in power consumption can be realized while maintaining high-performance playback. Consequently, it is possible to provide an optical disc playback apparatus which can realize sufficient playback performance at low power consumption.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: July 7, 2009
    Assignee: Panasonic Corporation
    Inventors: Youichi Ogura, Shinichi Konishi
  • Publication number: 20090147648
    Abstract: A Maximum Likelihood Sequence Estimator comprises a signal receiver (401) which receives a first signal for decoding. An ISI processor (403) generates a compensation signal from the first signal. The compensation signal represents intersymbol interference outside a channel model window of a Maximum Likelihood Sequence Estimation (MLSE) but does not represent intersymbol interference within the channel model window of the MLSE. A compensation processor (405) generates a compensated signal by compensating the first signal by the compensation signal, e.g. by subtracting the compensation signal from the first signal. The compensated signal is fed to a MLSE decoder (407) which decodes data of the first signal by performing the MLSE on the compensated signal. The invention may provide reduced detection error rates and may in particular be suitable for optical disc reading systems.
    Type: Application
    Filed: March 29, 2007
    Publication date: June 11, 2009
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Ruud Vlutters
  • Publication number: 20090129229
    Abstract: A method and apparatus for reproducing data, by which the quality of signals input to a Viterbi decoder are improved by using a two-step equalizer, and the Viterbi decoder is operated in an optimum state so that the quality of reproduction signals is improved, the apparatus including: a first equalizing unit to compensate for frequency gain properties of an input signal according to predetermined levels, a second equalizing unit to reduce noise of the input signal processed by the first equalizing unit, and a Viterbi decoder to Viterbi-decode the input signal processed by the second equalizing unit to output a binary signal corresponding to the data.
    Type: Application
    Filed: May 8, 2008
    Publication date: May 21, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyun-soo PARK, In-ho Hwang, Hui Zhao
  • Patent number: 7535812
    Abstract: A partial response is utilized to record information on a medium and then regenerate the information from the medium. A regenerating system undergoes equalization including subjecting a regeneration signal from the medium to the convolution of (k?s·D) (where D is one (1) bit delay operator, and k and s are positive integer). Such convolution is performed in the regenerating system so that low-frequency band noises are reduced with an improved error rate. The information is decoded from the equalized signal by use of maximum-likelihood detection.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: May 19, 2009
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Uno, Kiichiro Kasai
  • Patent number: 7535811
    Abstract: A disk device includes a reading section which reads reflected light and outputs a read signal according to the read reflected light, a processing section which calculates an adjustment value from the read signal, performs predetermined processing on the read signal based on the adjustment value, and outputs a process signal, a detecting section which detects a reading defect in the reading section based on the read signal, a determining section which determines signal quality of the process signal output from the processing section, a storage section which stores the adjustment value calculated by the processing section, in a memory area, based on a result output from the determining section, and a controller which, when the detecting section detects the reading defect, performs control so that the adjustment value is read out of the storage section and is supplied to the processing section.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: May 19, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiyasu Tatsuzawa, Koichi Otake, Hideyuki Yamakawa, Hiroyuki Moro, Toshihiko Kaneshige
  • Patent number: 7529331
    Abstract: A wobble clock generator with a protective mechanism that can avoid interference generated from a phase-modulated wobble signal. The wobble clock generator has an arithmetic/logic circuit and a phase-locked loop. The arithmetic/logic circuit calculates a period count value by counting a period of a wobble signal according to a reference clock, and compares an average value with the period count value for outputting a control signal. The phase-locked loop is electrically connected to the arithmetic/logic circuit for generating a wobble clock according to the control signal and the wobble signal. When the control signal corresponds to a first logic level, the phase-locked loop compares the wobble signal with the wobble clock to drive the wobble clock to be synchronized with the wobble signal. When the control signal corresponds to a second logic level, the phase-locked loop holds the wobble signal without synchronizing the wobble clock with the wobble signal.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: May 5, 2009
    Inventor: Yuan-Kun Hsiao
  • Patent number: 7519897
    Abstract: To provide a decoder and decoding method capable of reducing the number of times received data is decoded. A decoder according to the present invention includes: a Viterbi decoder decoding received data; a decode data length storage area storing a decode data length; a decoded data temporary storage area storing temporary storage data as decoded data up to a decode data length; a maximum data storage memory storing maximum decoded data as decoded data up to a maximum data length; a maximum-likelihood detection circuit selecting a decode data length based on likelihood information; and a decoded data reconstruction circuit replacing a part of maximum decoded data with temporary decoded data.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: April 14, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Takeshi Hashimoto
  • Publication number: 20090046557
    Abstract: An information reproducing method using PRML technology which provides asymmetry compensation and also assures media interchangeability. To compensate for asymmetry, target levels are basically adapted to readout signals and either restriction type (1) (time reversal and level reversal symmetry) or restriction type (2) (time reversal symmetry) is imposed between target levels. As a consequence, asymmetry compensation is made regardless of a readout signal distortion such as mark shift which might deteriorate media interchangeability.
    Type: Application
    Filed: October 1, 2008
    Publication date: February 19, 2009
    Inventors: Hiroyuki Minemura, Masaki Mukoh
  • Patent number: 7480224
    Abstract: The invention discloses a decoding apparatus and the method thereof for decoding a signal retrieved by an optical information reproducing system from an optical information recording medium. N legal codes are predetermined. According to the invention, first, the retrieved signal is converted into a data stream. Then, in a Viterbi decoding manner, the data stream is decoded into a digital code in accordance with a level of the data stream and N reference levels. Then, the binary code is decoded by a binary array into one of the N legal codes, and each of the N legal codes corresponds to one of N reference levels. In particular, the N reference levels are corrected by various detected conditions to enhance the correctness of decoded data.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: January 20, 2009
    Assignee: MediaTek Inc.
    Inventors: Wen-Yi Wu, Meng-Ta Yang
  • Patent number: 7478315
    Abstract: The present invention combines low density parity checking with parallel equalization channels to enhance data retrieval from tape. Viterbi analysis is done as a precursor to the use of at least one low density parity decoder. A signal decoder may include a plurality of viterbi processors and at least one low density parity check decoder. The decoder may receive a plurality of pulse-shaped signals and produces decoded output signals.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: January 13, 2009
    Assignee: Storage Technology Corporation
    Inventors: Mark Hennecken, David J. Pereira
  • Patent number: 7468940
    Abstract: An ITR (Interpolated Timing Recovery) data reproducing apparatus capable of acquiring an excellent reproduction output waveform with less distortion and updating sampling timing at high speed with a simple configuration is provided. Each sampling period (Ts) of a desired interpolation function f(t) is split into a plurality of periods, linear interpolation is performed for each of the split periods, and data at each interpolation point within each of the split periods is calculated. In addition, only a binary integer representation part is extracted as a quotient obtained by performing integer division of sampling timing for a sampling period, and only input sampling data (Ds) for a number of the binary integer representation part is captured into an interpolation filter to operate a pipeline.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: December 23, 2008
    Assignee: Sony Corporation
    Inventor: Satoru Higashino
  • Patent number: 7460627
    Abstract: A data reproduction device for equalizing a reproduced digital signal. A signal reproduced using a reproduction head is sequentially processed by an analogue filter, an A/D, and an interpolator before being supplied to a digital equalizer. The digital equalizer digitally equalizes an input digital signal to output to a subsequent Viterbi decoder, or the like. The digital equalizer comprises a variable BPF, and a variable FIR filter, and the filtering characteristic is variably adjusted.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: December 2, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Orimitsu Serizawa
  • Patent number: 7460451
    Abstract: The present invention provides highly reliable PLL without influence of variations in amplitude of a reproduced signal or variations in inclination of an edge. An information-reproducing apparatus according to the present invention includes a unit for detecting a phase difference between a reproduced signal and a reproducing clock signal, a PLL circuit for regulating a frequency of the reproducing clock signal to compensate for the detected phase difference, a unit for detecting a state of the PLL circuit, and a unit for regulating a loop gain of the PLL circuit corresponding to the detected state.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: December 2, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hisatoshi Baba
  • Patent number: 7443932
    Abstract: A method and an apparatus which adjusts a signal read from an optical disc in order to obtain stable binary data. The signal adjustment method comprises (a) detecting a period of an input signal of a predetermined code; (b) determining whether the detected period is smaller than a predetermined value; and (c) if the detected period is determined to be smaller than the predetermined value, adjusting the input signal so that its period equals the predetermined value, and outputting the input signal. The signal adjustment method and apparatus of the present invention reduce errors and improve system performance, when a signal input to the binary processor does not meet its code feature.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: October 28, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-soo Park, Jae-jin Lee, Jae-seong Shim, You-pyo Hong, Ju-han Bae, Jae-hoon Seo
  • Publication number: 20080259758
    Abstract: A partial response maximum likelihood decoder, such as a Viterbi decoder, implements a set of combined states where each combined state can represent at least two states from a plurality of complementary sets of states. For each data symbol and each combined state, a Viterbi processor (703) determines a path metric and a substate indication for each path to the combined state. A path selection processor (709) of the Viterbi processor (703) selects a selected path and a selected sub state indication for the path which corresponds to a highest likelihood path metric. The substate indication is an indication of which of the complementary set of states the combined state represents for the data symbol. The invention allows a substantial complexity reduction and/or reduced computational burden as the Viterbi algorithm can be applied to a reduced number of combined states.
    Type: Application
    Filed: October 11, 2006
    Publication date: October 23, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
    Inventor: Alexander Padiy
  • Patent number: 7440379
    Abstract: An information reproducing method using PRML technology which provides asymmetry compensation and also assures media interchangeability. To compensate for asymmetry, target levels are basically adapted to readout signals and either restriction type (1) (time reversal and level reversal symmetry) or restriction type (2) (time reversal symmetry) is imposed between target levels. As a consequence, asymmetry compensation is made regardless of a readout signal distortion such as mark shift which might deteriorate media interchangeability.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: October 21, 2008
    Assignees: Hitachi, Ltd., Hitachi-LG Data Storage, Inc.
    Inventors: Hiroyuki Minemura, Masaki Mukoh
  • Patent number: 7433289
    Abstract: The present invention relates to a frequency detection method for an optical disc bit data reproduction apparatus. The frequency detection method uses the optical disc bit data reproduction apparatus including an Analog to Digital Converter (ADC), an interpolator, an asymmetry compensator, a digital bit and successive bit length detector, a frequency detector, a phase detector and a Digital Controlled Oscillator (DCO). In the frequency detection method includes the primary frequency detection step and the secondary frequency detection step. In the primary frequency detection step, status of input RF digital bit data frequency versus sampling frequency is determined and the sampling frequency is corrected so as to allow the sampling frequency to be rapidly adjusted to the frequency of the RF digital bit data, thus primarily detecting frequency.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: October 7, 2008
    Assignee: LG Electronics Inc.
    Inventors: Eun Pyo Lee, Gun Jae Koo
  • Patent number: 7423949
    Abstract: A signal of a run-length-limited code is read out from a recording medium. The read-out signal is converted into a reproduced digital signal. A decoder subjects the reproduced digital signal to first decoding different from run length decoding to get a first decoded signal. Information bit streams are generated from the first decoded signal. The information bit streams are different in timing by 1-bit-correpsonding intervals. Run length decoders subject the information bit streams to run length decoding to get run-length-decoded bit streams respectively. Each of the run-length-decoded bit streams undergoes one of error correction and error detection. A decision is made as to which of the run-length-decoded bit streams is the smallest in error number on the basis of results of the one of error correction and error detection. The run-length-decoded bit stream being the smallest in error number is selected and outputted as a likeliest information bit stream.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: September 9, 2008
    Assignee: Victor Company of Japan, Ltd.
    Inventors: Junichiro Tonami, Yuuki Fujiwara
  • Publication number: 20080198720
    Abstract: The present invention relates to an optical disk reproducing apparatus, and provides a technology capable of supporting even a situation in which a reproduction signal characteristic is changed due to a factor other than recording density of an optical disk by using PRML of different constrained length and capable of improving reading accuracy. The optical disk reproducing apparatus includes a PRML circuit of first constrained length (for example, 4) and a PRML circuit of second constrained length (for example, 5). Equalization error values obtained during calculation of equalization learning in respective circuits are compared with each other in a determination circuit. Switching control of a switch is performed so that an output of one of the PRML circuits having a smaller equalization error value is selected.
    Type: Application
    Filed: November 30, 2007
    Publication date: August 21, 2008
    Inventors: Yusuke Nakamura, Masakazu Ikeda
  • Patent number: 7414932
    Abstract: In step S1, the address generator generates address information composed of a sync signal which is recorded on an optical disc, address data and an error correction code for the address data, pre-encodes and supplies it to a modulator. At the same time, a carrier signal generator generates a carrier signal which is to carry the address information, and supplies it to the modulator. In step S2, the modulator makes MSK modulation of the carrier signal supplied from the carrier signal generator on the basis of the pre-encoded address information supplied from the address generator, and supplies a resultant MSK modulation signal to a wobbling unit. In step S3, the wobbling unit forms, on the optical disc, a spiral groove wobbled adaptively to the MSK modulation signal supplied from the modulator. In this optical disc, a given address can be accessed quickly and accurately.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: August 19, 2008
    Assignee: Sony Corporation
    Inventors: Shoei Kobayashi, Nobuyoshi Kobayashi, Tamotsu Yamagami, Shinichiro Iimura
  • Patent number: 7408861
    Abstract: The invention relates to a recording or reproduction apparatus for optical recording media having means for increasing the resolution of a digital-to-analog converter (DA), such as, for example, a digital-to-analog converter (DA) which is provided in the servo regulating circuit of a recording or reproduction apparatus and has a smaller bit width than its digital data source (DD). In order to increase the resolution or precision of the digital-to-analog converter (DA), a method and a circuit arrangement are provided by means of which less significant bits (L) of the digital data source (DD) are quantized and the quantization result is added to the value of more significant bits (H) of the digital data source (DD) with the exception of the maximum value of the more significant bits (H) for the purpose of increasing the resolution of the output signal of the digital-to-analog converter (DA).
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: August 5, 2008
    Assignee: Thomson Licensing
    Inventor: Manfred Fechner
  • Patent number: 7403460
    Abstract: An evaluation method for calculating an identification signal by using PRML, comprises a table storing true patterns and ideal signals thereof, false patterns corresponding to the true patterns and ideal signals thereof, and Euclidean distance between the true pattern and the false pattern, a calculating unit, when a recording signal synchronized with an identification signal coincides with any pattern of the table, calculates a distance between Euclidean distance between the ideal signal of the true pattern and a reproduction signal and Euclidean distance between the ideal signal of the false pattern and a reproduction signal, and an evaluation unit which evaluates an identification signal by using an average and standard deviation of difference. A table for patterns is created for a likely mistaken pattern, whereby calculating an evaluation value with high precision, of a signal quality, with a small amount of calculation.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: July 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuji Nagai, Yutaka Kashihara, Akihiro Ogawa
  • Publication number: 20080165651
    Abstract: A recording control apparatus includes a waveform rectification section for receiving a digital signal generated from an analog signal representing information reproduced from an information recording medium, and rectifying a waveform of the digital signal; a maximum likelihood decoding section for performing maximum likelihood decoding of the digital signal having the waveform thereof rectified, and generating a binary signal representing a result of the maximum likelihood decoding; a reliability calculation section for calculating a reliability of the result of the maximum likelihood decoding based on the digital signal having the waveform thereof rectified and the binary signal; and an adjusting section for adjusting a shape of a recording signal for recording the information on the information recording medium based on the calculated reliability.
    Type: Application
    Filed: March 11, 2008
    Publication date: July 10, 2008
    Inventors: Harumitsu MIYASHITA, Takeshi Nakajima, Naohiro Kimura
  • Patent number: 7395462
    Abstract: A weighted defect estimating apparatus and a related method for determining a defect estimation value are disclosed. The weighted defect detecting apparatus includes: a defect detecting unit for generating a defect value when a defect in a predetermined region of an optical disc is detected; a weighting circuit, electrically connected to the defect detecting unit, to generate a weighted defect value according to the defect value and a weighting factor corresponding to a location of the defect on the optical disc; and a computing module, electrically connected to the weighting circuit, for computing the defect estimation value according to a plurality of weighted defect values corresponding to the predetermined region.
    Type: Grant
    Filed: December 25, 2005
    Date of Patent: July 1, 2008
    Assignee: MediaTek Inc.
    Inventors: Wei-Hsiang Tseng, Hsin-Cheng Chen, Ping-Sheng Chen
  • Publication number: 20080151726
    Abstract: An optical disc recording and reproducing apparatus includes a maximum likelihood detection unit for decoding binary data from a reproduced multivalued signal from an optical disc, an equalization error generation unit for obtaining an equalization error signal from an input signal and an output signal to and from the maximum likelihood detection unit, a convolution processing unit for performing a convolution operation between the equalization error signal and plural values determined by the partial response class, a pattern detection unit for detecting plural predetermined data sequence patterns from the binary data output from the maximum likelihood detection unit, and a grouping and averaging processing unit for calculating a recording compensation amount for each type of the data sequence patterns by grouping convolution output signals output from the convolution processing unit in accordance with the type of the data sequence patterns and by averaging each of the grouped convolution output signals.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 26, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideyuki YAMAKAWA, Koichi Otake, Tatsuji Ashitani, Hiroyuki Moro
  • Patent number: 7391699
    Abstract: Disclosed herewith is an information reproducing method for realizing significant expansion of disk capacity and processing signals having different minimum run lengths, as well as an optical disk drive that uses the method. To achieve the above objects, a PRML method is used. According to the method, a compensation value is added to an initial target value decided by a convolution operation of NN bits according to a bit array consisting of N bits (N>NN) to obtain a new target value, which is then compared with each of reproduced signals sequentially to select a bit array in which the error between the reproduced signal and the target signal is minimized most likely, then the selected bit array is binarized.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: June 24, 2008
    Assignee: Hitachi, Ltd.
    Inventor: Hiroyuki Minemura
  • Patent number: 7385900
    Abstract: A transversal filter subjects a reproduced signal to partial-response waveform equalization responsive to tap coefficients to generate an equalization-resultant signal. There is generated 0-point information representing whether or not the reproduced signal corresponds to a zero-cross point. A temporary decision device calculates a temporary decision value of the equalization-resultant signal on the basis of a PR mode signal, an RLL mode signal, at least four successive samples of the 0-point information, and at least four successive samples of the equalization-resultant signal. Calculation is made as to a difference between the temporary decision value of the equalization-resultant signal and an actual value thereof. An error signal is generated in response to the calculated difference. The tap coefficients of the transversal filter are controlled in response to the generated error signal. The partial-response waveform equalization is PR(a, b, b, b, a).
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: June 10, 2008
    Assignee: Victor Company of Japan, Ltd.
    Inventor: Junichiro Tonami