Abstract: An audio decoder architecture makes use of various component sharing techniques to conserve hardware and reduce implementation cost. In one embodiment, the audio decoder comprises a bitstreamer, a synchronization controller, a first and second decode controllers, a memory module, a data path, and an output buffer. The bitstreamer retrieves compressed data and provides token-aligned data to the synchronization controller and decode controllers. The synchronization controller initially controls the bitstreamer to locate and parse audio frame headers to extract decoding parameters. The synchronization controller initiates the decode controller which corresponds to an identified compression format, and turns control of the bitstreamer and data path over to the selected decode controller. The selected decode controller then controls the bitstreamer to parse the variable length code compressed transform coefficients.

Abstract: This invention refers to a synchronization method of a remote unit from a SPS timing signal (SPS) produced in a local unit. The SPS timing signal (SPS) is in the form of successive pulses (1) which are produced from signals received from satellites. The SPS signal (SPS) is asynchronous with respect to the system clock, that is, the reference clock defined between the local unit and the remote unit has no initial relationship with the SPS signal (SPS). The invention is characterized in that it includes the following steps: calculation in the local unit of an information (“10011010”) representing the number of local clock cycles occurring from the appearance of a pulse (1) until the moment (SL) when this information is injected into the data stream (FR); and generation in the remote unit of a synchronization signal related to the SPS signal, depending on this information (“10011010”).

Abstract: A method and apparatus of a synchronizer circuit for transferring signals between two clock domains in which a first synchronizer unit and a second synchronizer unit form a hand-shaking protocol. In particular, an input event from a source clock domain is captured in an input unit and a first signal is asserted indicating that the input signal is to be transferred to a target clock domain. This first signal is synchronized to the clock signal in the target clock domain at the first synchronizer unit, causing assertion of a second signal. The second signal is coupled to an output unit which generates an output event signal for a single clock period.

Abstract: In transmitting a packet string having variable packet intervals by converting the packet string into that having even packet intervals with each of the packets being attached with a time stamp as information for reproducing original packet string, when the value of the time stamp, which is decided by adding a specified offset time to the synchronization time, is not smaller than the value of the time stamp attached to the previous packet, the time stamp is attached to the packet and the packet is transmitted. If the value of the time stamp becomes not more than the value of the time stamp attached to the previous packet as a result of providing shortened offset time due to increased bit rate of the original packet string, the packet is discarded so as to protect the transmission from being stopped.

Abstract: A data receiving unit includes a data receiving circuit for receiving, through a transmission path, transmission data which has been encoded into a predetermined transmission code by using a predetermined transmission clock signal and includes a reference pulse having a pulse width corresponding to a period of the transmission clock signal, a clock for generating a received clock signal in synchronization with the transmission data, and a data decoding circuit for decoding the transmission data received by the data receiving circuit using the received clock signal generated by the clock, where the clock includes an oscillator generating at least a reference clock having a period which is shorter than that of the transmission clock signal, a counter circuit counting an interval between points of change of the transmission data received by the data receiving circuit according to the reference clock signal, a reference pulse detector circuit for detecting the reference pulse on the basis of a count value from th