Abstract: A router, for routing at least one input signal to at least one output, comprises at least one input module and at least one output module. Each of the input and output modules includes at least one clock selector circuit for selecting from among a first and second clock signal, and an oscillator signal, as a common output clock signal for the at least first router, based in part on whether at least one of the first and second clock signals has toggled. The clock selector circuit provides redundancy as well as distribution of clock signals among elements within each module.

Abstract: A method of calculating local time, in an intelligent network, of a subscriber's User Equipment (UE), determines whether a call originates or terminates with the UE, the UTC offset and DST observance indicator for the (G)MSC signaling the intelligent network, and a determination is of whether the UE is in a Problem Area cell site. If the UE is in a Problem Area cell site, the received time and Coordinated Universal Time (UTC) Offset is corrected. A Cell Global Identity (CGI) is used to lookup the UTC Offset and a Daylight Saving Time (DST) observance indicator for the Cell Site. For calls terminating with the UE, if the UE is not in a Problem Area cell site, the VLR serving the UE is used to lookup the UTC offset and DST observance indicator for the subscriber. A time zone delta is applied to the call time of day and the UTC Offset and if DST is in effect, and there is a difference of DST between an MSC serving the UE and the location associated with the UE, a DST delta is applied to call time of day.

Abstract: The present invention discloses a method for controlling the reporting of an event timestamp. The method includes the following steps: a timestamp control parameter is set; the MG determines whether to report the timestamp of the event according to the timestamp control parameter. Further, the present invention discloses an MG and an MGC. The technical solution provided by the present invention controls the MG to report the timestamp of an event; enables the MGC or other applications that require the timestamp of the event to determine the actual time when the event appears according to the obtained timestamp; and controls the reported event not to include the timestamp if the MGC or other applications do not need the timestamp of the event, thus saving the bandwidth resources and other system resources.

Abstract: A method of performing uplink synchronization in a wireless communication system includes transmitting a random access preamble which is randomly selected from a set of random access preambles, receiving a random access response, the random access response comprising a random access preamble identifier corresponding to the random access preamble and a time alignment value for uplink synchronization, starting a time alignment timer after applying the time alignment value, starting a contention resolution timer after receiving the random access response, wherein contention resolution is not successful when the contention resolution timer is expired, and stopping the time alignment timer when the contention resolution timer is expired.

Abstract: A transceiver includes a receiver unit including a clock and data recovery unit. The transceiver includes a transmitter unit and a digital core coupled to the receiver unit and the transmitter unit. A switch circuit is positioned after the clock and data recovery unit, and is configured to route data from the receiver unit to the transmitter unit in a test mode of the transceiver.

Abstract: Clock recovery is used in a variety of communications network applications to enable nodes using different clocks to operate in an effectively synchronized manner. Example embodiments of the present invention include an apparatus and corresponding method for supporting client data transport with timing transparency and require neither a common clock to be available at both the ingress and egress sides of the connection nor overhead bytes to recover a client clock. Rather, client traffic clock recovery may be performed in example embodiments of the present invention entirely in the egress data path using the client data received from the ingress side after removing the clients signal from a higher level carrier signal.

Abstract: The present invention relates to an apparatus and method of frame synchronization in broad band wireless communication systems. In an apparatus of frame synchronization in a mobile station, a time variant phase rotation compensator eliminates time variant phase rotation carried in received signals by conjugated multiplication between adjacent signal samples. Then, the processed signal is fed into a delay correlator to calculate a plurality of correlations between two successive frames. A local power calculator acquires an average power of several symbols centered on delayed correlation values. A normalizer normalizes the delayed correlation values with a local average power corresponding to the delayed correlation values. A maximum value detector selects the maximum value from normalized correlation values to trigger frame synchronizing and timing signals.

Abstract: An optical signal return path system analog RF signals are sampled using a master clock frequency, and combined with digital data such as Ethernet data at a cable node. The cable node sends the combined signals on a return path over a fiber optic medium to the cable hub. The cable hub extracts an approximate in-frequency replicate of a master clock signal, and can use the replicate master clock signal to desample the digitized RF signals back to analog. The cable hub can further use the replicate of the master clock signal to serialize Ethernet data, and send the Ethernet data back to the cable node via an optical cable in the forward direction. Accordingly, a single master clock signal can be used on a CATV network for encoding/decoding, and transmitting a variety of data signals, which enhances the integrity and reliability of the data signals.

Abstract: The number of channels is changed in accordance with an operation mode in an image pickup apparatus. An image-pickup control unit 240 determines the number of operation channels W in accordance with an operation mode. A sensor unit 210 outputs an image pickup signal corresponding to each pixel in accordance with the number of operation channels W. A data sending unit 220 performs serial conversion on image pickup signals, and transfers them to the image processing unit 300 using a high-speed interface (a signal line 229) such as an LVDS in accordance with the number of operation channels W. A data receiving unit 311 performs parallel conversion on the transferred serial signal for each of the channels in units of M bits. A data reconstruction unit 500 detects a synchronization code embedded in the parallel signals, extracts data windows, and supplies, to a signal line 319, image pickup signals of bit length n which are reconstructed from the data windows.

Abstract: A method for synchronizing network elements to a global clock derived from the GPS clock acquired by a plurality of base stations. The global clock is distributed to controllers of various networks, and from there to network access devices. The network access devices further distribute the global clock to various wire-line and local wireless networks and from there, to the users served by these networks. The user equipment is enabled with a simple clock discipliner that adjusts the local clock to the global clock, resulting in a reliable synchronization across the converged communication networks.

Abstract: A demodulation section 13 receives a TDMA-TDD based phase-modulated burst signal of mobile communications and demodulates the burst signal by a synchronous detection system (or a quasi-synchronous detection system). The demodulation section 13 includes a frequency deviation compensation section and a carrier recovery section each having a loop filter 14 with three or more stages of time constants. The time constants are switched by a selector switch 15 based on a control signal from a demodulation control section 16. This achieves quick pull-in and jitter after convergence is minimized, thereby allowing highly efficient performance of frequency deviation compensation, etc. that is required for synchronous detection (or quasi-synchronous detection) without increasing the size of circuit.

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.

Abstract: A method for transporting a client signal in an optical transport network (OTN) includes steps as follows. A byte number Cn of a client signal transported in a current OTN frame period is generated according to a client signal clock and a system clock. If the Cn of the current OTN frame falls in a certain range, a predetermined area in an optical channel payload unit-k (OPUk) overhead field is identified as normal, and the Cn is filled in the OPUk overhead field of the current OTN frame. Therefore, the reliability for transporting the client byte number can be improved and an OPUk overhead byte space needed for transporting the client signal byte number can be saved.

Abstract: A system, method and computer readable medium for mediating communication between a mobile device and a data source over a network is described. The system includes an asynchronous message receiver that is configured to receive an asynchronous request message from the device. The asynchronous request message includes an identifier field for identifying the asynchronous request message and a message field. The system also includes a synchronous message transceiver communicatively coupled to the asynchronous message receiver and configured to synchronously communicate with the data source by sending a synchronous request message to the data source and receiving a synchronous response message from the data source in return. The synchronous request message includes the message field of the asynchronous request message. A rules processor also forms part of the system, and is communicatively coupled to the synchronous message transceiver.

Abstract: A communications system for controlling equipment associated with a vehicle, includes a micro-controller (604) and a digital serial communication link (621, 622, 662, 663) using a multiplexed timing signal and first data signal. A camera or image sensor (650) located in the vehicular component communicates with the micro-controller (604) via the digital serial communication link.

Abstract: A communication apparatus determines a hibernation period on the basis of the amount of an offset in beacon period start timing among multiple beacon groups. The communication apparatus is placed in a hibernation status in accordance with the determined hibernation period. Thus, an offset in beacon period start timing among the beacon groups that would occur while the device is in hibernation can be prevented and the need for merging beacon groups and decrease in data rate during such merging are prevented.

Abstract: A method an apparatus is provided to generate a gray code sequence from a sequence of binary values having a length “L”. Accordingly, one aspect of the present invention provides a circuit comprising a cycle flag toggle circuit configured to toggle a cycle flag between a first value and a second value, an intermediate value generator coupled to an output of the cycle flag toggle circuit configured to receive the binary value, and configured to generate an intermediate value from the cycle flag and the binary value, and a binary to gray converter coupled to an output of the intermediate value generator, configured to convert the intermediate value to a gray code.

Abstract: A method for synchronizing measurements in a mobile communication apparatus having a first active radio access means (100) adapted to communicate according to a first radio access technology (RAT) and at least a second passive radio access means (200) adapted to communicate according to a second RAT. A time reference common to the first and the second access means (100) is generated. At least one time schedule is obtained, said schedule indicating at least one time gap wherein the second access means (200) is allowed to be active. The activation time of the schedule is based on the common time reference. An arrangement adapted to generate the common time reference and the time schedule is also disclosed.

Abstract: Synchronizing multiple-phase data converters by exchanging terminal count pulses via a bidirectional link. Multiple-phase data converters such as analog to digital converters (ADCs) or digital to analog converters (DACs) are synchronized to operate at the same phase by exchanging terminal count (TC) pulses and capturing counter state, representing a time offset from TC. Time offset and the symmetrical delay introduced by the link are used to solve for the delay introduced by the link and the off-set between devices. The offset information is used to align the devices. The process may be repeated to correct for drift.

Abstract: According to a method for generating a system time clock in a receiving device for digital packetized elementary data streams (E), the packetized elementary data streams (E) being generated in a transmitting device by sampling at a sampling frequency (fsample) synchronized by a system time clock of the transmitting device, the sampling frequency (fsample) of one data stream is determined in the receiving device, and the program clock reference counter is synchronized with the data stream's sampling frequency.

Abstract: A receiving system includes: FIFO memory 13 storing audio data AD contained in a transmission signal T; an extraction unit 14 configured to extract a clock parameter contained in the transmission signal T; a parameter change unit 152 configured to change the clock parameter in accordance with a result of a comparison between a data storage rate SR of the FIFO memory 13 and a predetermined value; a frequency setting unit 153 configured to set a read frequency fr using the changed clock parameter; and a data read unit 16 configured to read the audio data AD from the FIFO memory 13 in synchronization with a reception end audio clock signal AC of the read frequency fr.

Abstract: A system and method for state synchronization between a base station and a mobile station in a mobile communication system. A count value indicative of a state change of the base station is received. The received current count value is compared with a previous count value previously received and stored. If the current count value is different from the previous count value, the mobile station performs a network entry procedure with the base station.

Abstract: Methods and systems are provided for in-band signaling of at least two simultaneous digital media streams in a network, the two simultaneous streams being a part of a media session. Each of the at least two simultaneous streams is generated from a corresponding source. The generated simultaneous streams are synchronized by using a unique marker packet. Each synchronized stream is transmitted to a destination corresponding to each source.

Abstract: At an ingress interface of a data network first information data are generated, at an egress interface of the data network second information data are generated, correction data are generated on the basis of the second information data, and at the egress interface a clock frequency is recovered on the basis of the first information data and the correction data.

Abstract: The invention includes a technique for clock recovery in a network having master and slave clocks in respective Time Division Multiplexing (“TDM”) network segments which are interconnected by a non-TDM segment. Master clock timestamps are sent to the slave. The slave measures a master clock timestamp inter-arrival interval, and sends slave clock timestamps to the master. The master measures a slave clock timestamp inter-arrival interval, and sends that slave clock timestamp inter-arrival interval to the slave. The slave then calculates an error signal based at least in-part on the difference between the master clock timestamp inter-arrival interval and the slave clock timestamp inter-arrival interval, and employs the difference to recover the first service clock in the second TDM segment.

Abstract: A communication system carrying out an isochronous transfer, includes a cycle master node and nodes connected with each other through a system bus. The cycle master node sets a cycle time of the isochronous transfer and transfers a cycle start packet onto the system bus for every the cycle time. Each of the nodes transfers an isochronous packet onto the system bus in response to the cycle start packet.

Abstract: The present invention discloses a method and Ethernet device for clock synchronization, a method for clock synchronization in an entire Ethernet, and the relevant Ethernet. The method for clock synchronization in an Ethernet device includes: the PHY layer unit of the Ethernet device extracts a clock from the data sent by the receive unit; the MAC layer unit makes adjustments to the extracted clock according to the local clock and takes the adjusted clock as the transmit clock of the Ethernet device. The method for clock synchronization in an entire Ethernet includes: clocks of all Ethernet devices are synchronized to the clock generated by the Ethernet device at the highest level. The invention provides a method for clock synchronization so that sending and receiving of clocks in Ethernet devices can be synchronized and clock synchronization can be realized in the entire Ethernet.

Abstract: A network-on-chip apparatus including a plurality of network interfaces being independently connected to a plurality of processing elements; a network including a plurality of switches for controlling data transmission/reception between the network interfaces; and a plurality of bidirectional links for connecting between the network interfaces and the switches, and between the switches.

Abstract: PCR jitter is improved when writing an input stream TS having a packet with a PCR in a memory 10 and reading it at a high speed. An oscillator 44 oscillates a local clock signal having a frequency of a reference clock for the input TS and a counter 46 counts the local clock signal. When a PCR detection section 38 detects the PCR in the input TS, a latch circuit 42 latches a counted value of the counter and a PCR exchange section 40 exchanges the original PCR with a result of subtracting the latched count value from the PCR of the input TS.

Abstract: Data is synchronized between a mobile device and a computing device over a wireless link. Synchronization operations are scheduled according to a synchronization schedule that is based on a current time of day.

Abstract: A signal converter having a memory bank and radix-2 Fast Fourier Transform (FFT) transforms an Orthogonal Frequency Division Multiplexing (OFDM) signal having a long preamble and data into an OFDM signal in the frequency domain, and outputs the transformed OFDM signal. The radix-2 FFT has a linear systolic array architecture, transforms the long preamble stored in the memory bank by FFT, then stores the transformed long preamble into the memory bank, transforms data input through a buffering process and data input directly by FFT, and stores the transformed data in the memory bank. The memory bank has four memories, stores the long preamble transformed or not transformed and outputs the stored long preambles or the transformed data for the purpose of demodulation as the transformed data is input. Data-processing delay and/or power consumption may be reduced during the operation of the FFT processor.

Abstract: A technique for establishing a logical path between two servers in a coordinated timing network of a processing environment is provided. The technique includes the exchange of command and response message pairs by a server and an attached server, via a physical link. The server transmits a command message to an attached server to establish a server-time-protocol (STP) logical path and receives a response from the attached server. The technique also includes the server receiving a request transmitted by the attached server to establish an STP logical path to the server and transmitting a response to the attached server's request. A logical path between the server and the attached server is established if the attached server's response indicates that the server's request was accepted by the attached server and if the server's response indicates that the attached server's request was accepted by the server.

Abstract: A packet preamble search method is disclosed for locating a packet preamble with multiple predetermined patterns of a regular form within a received transmission signal with sequential multiple patterns. The pattern of the received transmission signal and the predetermined pattern of the packet preamble have the same length with even bits. The pattern of the transmission signal is sequentially compared with the predetermined pattern. A hit count is increased and a miss count is reset when the pattern of the transmission signal matches the predetermined pattern. The miss count is increased and the hit count is decreased when the pattern of the transmission signal does not match the predetermined pattern. The hit count and the miss count are reset when the hit count is less than or equal to the miss count. An address matching procedure is activated when the hit count exceeds or is equal to a threshold value.

Abstract: A flexible framing format and implementation scheme for transmitting uncompressed video data selected from a group of various video formats, audio data and control data over a single serial communication channel at a fixed clock rate, thereby eliminating the need for transmitting a pixel clock signal. The data is transmitted over the single communication channel in packets and recreated at the destination side. Blank pixels of the video data are completely suppressed so that only active pixels are transmitted over the single communication channel, thereby reducing communication bandwidth requirement of the channel.

Abstract: A timing network is provided that includes a plurality of servers. The servers of the network obtain information used to maintain the servers in time synchronization, thus ensuring the integrity of the servers.

Abstract: Local Interconnect Network message budget calculation error is reduced by utilizing an eight bit time measurement of the sync byte in the message header. The method determines the header budget separately from the data budget, simplifying the required logic. The sync byte reference time is multiplied by the message data size to determine the data budget.

Abstract: A timing network is provided that includes a plurality of servers. The servers of the network obtain information used to maintain the servers in time synchronization, thus ensuring the integrity of the servers.

Abstract: According to one embodiment of the invention, a network element synchronizes a number of clocks within the system while supporting multiple independent timing domains. The network element includes a local clock, which is free-running and is not necessarily synchronized with an external reference, that synchronously provides a local time value to the slave and master interfaces of each timing domain. Each slave interface of each timing domain independently determines timing information based on a received master clock synchronization event and the value of the local time when that synchronization event was received. The timing information is distributed to the master interfaces of the appropriate timing domain, and each master interface calculates an adjusted synchronization event based on the received timing information and the value of the local time when that timing information was received. The adjusted synchronization events are transmitted out of the network element to an external slave interface.

Abstract: Techniques for synchronizing routing data include determining whether conditions are satisfied for one-way transfer with an adjacent router. If it is determined that conditions are satisfied for one-way transfer of routing table data with the adjacent router, then a refresh-notice message is sent from the initiating router to the adjacent router. The refresh-notice message includes data that indicates a particular direction for transfer of routing table data. If the particular direction is inbound, then a copy of an adjacent routing table is received without sending a copy of the initiating router's own routing table. If the particular direction is outbound, then a copy of the own routing table is sent without receiving a copy of the adjacent routing table.

Abstract: Provided is a system and method for communicating audio. A method includes transmitting audio information segments on a first signal line, each segment including a format portion representative of audio format modes, and a data portion having audio data corresponding to one or more of the format modes. The method also includes transmitting a number of synchronization markers on a second signal line. Each marker is representative of a timing of one of the audio information segments.

Abstract: A stream data processing apparatus includes a demultiplexing portion configured to demultiplex multiplexed stream data, to which a PCR is added, into a plurality of pieces of stream data to which a PTS is added, a system time measuring portion configured to measure a system time according to a PCR, a synchronous control portion configured to determine continuity of a reference time according to a PCR and system time information (SYC), to determine continuity of a reproduction time according to a PTS and an STC, and to output synchronous control information according to results of these determinations, a storage portion configured to store stream data, a decoding portion configured to decode stream data stored in the storage portion, an output portion configured to output decoded data, and a decoded data output control portion configured to control a mode of an operation of handling decoded data by the output portion, according to the synchronous control information.

Abstract: The disclosed invention relates to a re-synchronization system that operates in a switching arrangement receiving a plurality of incoming data packets. The switching arrangement is made of an active switch card that transmits the incoming data packets and a backup switch card that may be re-activated by an operator after replacement. The re-synchronization system is implemented in each switch card. When the backup switch card is re-activated, both switch cards receive the incoming data packets and the system of the invention allows to re-synchronized both switch cards by controlling the transmission of the incoming data packets out of each switch card until the same data packets are transmitted. The re-synchronization system further comprise storage for storing the incoming data packets and detector for detecting a re-synchronization information among the incoming data packets.

Abstract: An interworking function (IWF) is coupled to a switch of a packet network and communicates with the network switch based on an Ethernet clock signal or some other type of clock signal. A primary reference clock (PRC) of the network generates a PRC signal, and a timing analyzer determines timing information indicative of timing relationships between the Ethernet clock signal and the PRC signal. The timing analyzer periodically transmits such timing information, and the IWF uses the timing information to generate a PRC signal that is traceable to the network PRC signal.

Abstract: In one embodiment, a gateway for a constant delay network identifies a baseband clock that is synchronized by exchanging synchronization messages over a packet switched network. The gateway then generates a strobe by manipulating the identified baseband clock using a custom multiplier that is selected according to transmission variables. The gateway then signals a front end component to process fixed length packets for transfer to a back end component according to the generated strobe, which can reduce or eliminate buffering by the back end component and can improve cable modem operation.

Abstract: In one embodiment, a system is configured to generate a time reference where the system includes a bi-directional loop configured to have a first propagation speed in a first direction and a second propagation speed in a second direction, wherein the first propagation speed is substantially equal to the second propagation speed. In one embodiment, the system further includes a plurality of system elements coupled to the bi-directional loop, wherein each respective system element of the plurality of system elements is configured to determine a time reference common to each as an average arrival time at the respective system element of a first signal transmitted in the first direction over the bi-directional loop and a second signal transmitted in the second direction over the bi-directional loop.

Abstract: A distributed cable modem termination system of the present invention includes a downstream transmitter hub, an upstream receiver hub, and a head end that communicatively couples to the downstream transmitter hub and to the upstream receiver hub via a packet data network. The head end and the downstream transmitter hub are operable to synchronize a clock of the downstream transmitter hub with a clock of the head end. Further, the upstream receiver hub and the downstream transmitter hub are operable to synchronize a clock of the upstream receiver hub with the clock of the downstream transmitter hub. Clock synchronization between the upstream receiver hub and the downstream transmitter hub are performed using ranging operations supported by at least one cable modem communicatively coupled to both the upstream receiver hub and the downstream transmitter hub via cable modem network plant.

Abstract: A node of a real-time scheduled packet network synchronizes an internal frequency reference to a master node by receiving first heartbeat packets that are transmitted by the master node at a predetermined frequency. The node calculates a link phase of a link over which the first heartbeat packets are received by subtracting a time at which the node transmitted a second heartbeat packet to another node from a time at which the node received a first heartbeat packet.

Abstract: A system for transmitting a clock signal through a packet-based network is disclosed. The system comprises a first node configured to measure a clock frequency of the clock signal and calculate an accuracy indicator of the measured clock frequency; a second node configured to receive the clock frequency measurement and the accuracy indicator of the clock frequency measurement, and synthesize the clock signal therefrom; and a packet-based network for transmitting the measured clock frequency and accuracy indicator from the first node to the second node. A method of deriving a clock frequency by identifying packets with the shortest total transmission time is also disclosed.

Abstract: Method and apparatus are disclosed for synchronizing multimedia in asynchronous networks. In this invention, clock domains are first reduced to separate hardware clock correction circuits at the separate endpoints of an asynchronous network. At each end of the network node, the controllable input device such as a video device is synchronized to the non-controllable output device such as a set top box to prevent unknown or poor-quality alterations by the output device. Output device timestamp packets are regularly sent to the input device, which then adjusts its clock accordingly. The exchange of packets between input devices over the asynchronous network is then subjected to a software-based scheme to effectively synchronize these devices.

Abstract: A data recovery apparatus and method for receiving at least an original clock and at least an original data stream output from a transmitter to output at least one recovery data are provided. The original data stream and the recovery data respectively include N steps in a period T of the original clock, wherein N is an integer larger than 0. The data recovery apparatus includes a sampling unit and a processing unit. The sampling unit samples the original data stream according to the original clock, wherein the sampling unit samples the corresponding data of the original data stream at least three times with T/(4N) sample period in each step. The processing unit receives and compares the sampled result output from the sampling unit, and recovers the sampled result to the recovery data according to the compared result.