Having Both Input And Output Queuing Patents (Class 370/413)
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Patent number: 8477789Abstract: A transmission device (100) outputs, to a reception device (200), a stored amount of packets in a first transmission buffer (105) just before a certain packet has been written to the first transmission buffer. A first reception buffer amount read unit (206) in the reception device reads a stored amount of packets in a first reception buffer just before the certain packet has been read from the first reception buffer. A storage amount addition unit (207) adds the stored amount of packets in the first transmission buffer and the stored amount of packets in the first reception buffer, and a correction unit (208) adjusts the frequency of a variable frequency oscillator in a reception timestamp timer 209 so that the resulting added value is a constant value.Type: GrantFiled: December 20, 2006Date of Patent: July 2, 2013Assignee: Panasonic CorporationInventor: Yasuo Hamamoto
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Patent number: 8472458Abstract: A buffer space allocation method for a packet switch includes periodically performing a measurement process to obtain a plurality of measurement results at different times, each measurement result indicating a total size of accumulated packets in an output queue corresponding to one of a plurality of network ports of the packet switch, and adjusting a dedicated buffer space of the output queue according to the plurality of measurement results and a reserved space value for the dedicated buffer space.Type: GrantFiled: September 30, 2010Date of Patent: June 25, 2013Assignee: Ralink Technology Corp.Inventor: Kuo-Cheng Lu
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Patent number: 8463909Abstract: A method, computer readable medium, and apparatus for managing server resources includes receiving at a traffic management device one or more requests in a message based protocol. The traffic management device determines a difference between a level of utilization of resources maintained by a server that handles the one or more received requests and a threshold level of utilization of resources that can be maintained by the server; and randomly delays the one or more requests based upon the determined difference.Type: GrantFiled: September 15, 2010Date of Patent: June 11, 2013Assignee: F5 Networks, Inc.Inventors: Paul I. Szabo, Nat Thirasuttakorn, Benn Bollay
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Patent number: 8458319Abstract: A system for tracking resource usage in network. In a specific embodiment, the system includes a memory in a distributed-forwarding switch that maintains resource evolution information. A module, which communicates with the memory, is adapted to update the resource evolution information when the resource changes or information associated with the resource changes. In a more specific embodiment, the memory is implemented via plural resource-tracking hash tables associated with forwarding engines in switches connected to a network. Each hash table communicates with a corresponding resource-tracking module that monitors changes in accompanying forwarding engines and updates the hash tables in response thereto. The resource-tracking modules may also selectively provide information in the resource-tracking modules to a user interface in response to queries or control signals originating from a user interface.Type: GrantFiled: January 11, 2006Date of Patent: June 4, 2013Assignee: Cisco Technology, Inc.Inventor: Ravikanth Samprathi
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Patent number: 8442063Abstract: A system and method for scheduling delivery of packetized data traffic at an output port of a network node featuring a hybrid queue with a unicast subqueue and a multicast subqueue. An interleave indicator for each unicast and multicast entry in the queue is used to toggle the header type field of the hybrid queue. Upon departure, a scheduler selects between the unicast subqueue and multicast subqueue as dictated by the state of the header type field. The disclosed interleave indicator techniques add minimal overhead to the system, allowing ready scaling with increasing port densities. Further, the data structure of the multicast subqueue can be selected to optimize the system and achieve desired performance characteristics.Type: GrantFiled: December 21, 2009Date of Patent: May 14, 2013Inventors: Xuyang Zhou, Yongbing Xu, Xiaoxi Sun
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Patent number: 8442057Abstract: A node in a mobile ad-hoc network or other network classifies packets (a) in accordance with a first set of priority levels based on urgency and (b) within each priority level of the first set, in accordance with a second set of priority levels based on importance. The node: (a) queues packets classified at highest priority levels of the first and/or second sets in high-priority output queues; (b) queues packets classified at medium priority levels of the first set in medium-priority output queue(s); and (3) queues packets classified at low priority levels of the first and/or second set in low-priority output queue(s). Using an output priority scheduler, the node serves the packets in order of the priorities of the output queues. In such manner, orthogonal aspects of DiffServ and MLPP can be resolved in a MANET or other network.Type: GrantFiled: July 11, 2012Date of Patent: May 14, 2013Assignee: The Boeing CompanyInventors: Wayne R. Howe, Muhammad Akbar Qureshi
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Patent number: 8432927Abstract: A fixed-size data packet switch comprising: 1) N input ports for receiving incoming fixed-size data packets at a first data rate and outputting the fixed-size data packets at the first data rate; 2) N output ports for receiving fixed-size data packets at the first data rate and outputting the fixed-size data packets at the first data rate; and 3) a switch fabric interconnecting the N input ports and the N output ports.Type: GrantFiled: December 31, 2001Date of Patent: April 30, 2013Assignee: STMicroelectronics Ltd.Inventor: Ge Nong
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Patent number: 8428076Abstract: The present invention provides a preemptive priority scheduling system and method for optimal load balancing of messages and preserving the lightweight allocation resources in an intersystem communication. The invention also provides a system and method for scheduling of messages of a plurality of classes in an intersystem communication.Type: GrantFiled: March 30, 2011Date of Patent: April 23, 2013Assignee: Tata Consultancy Services LimitedInventor: Rajesh Mansharamani
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Patent number: 8422366Abstract: In a data transmission device and method provided with duplexed switches outputting frames in the order of input for continuing the communication without instantaneous interruptions even though one of the switches is faulted, input interfaces generate frames in which every time data is inputted, input order information indicating the input order is added to the data together with unique information of each input interface and providing the frame generated to the switches in parallel. At least one output interface sequentially stores the frames outputted from the switches for every unique information and selects a first arrived frame among the frames stored with same input order information.Type: GrantFiled: May 20, 2010Date of Patent: April 16, 2013Assignee: Fujitsu LimitedInventors: Masaki Hirota, Hiroshi Tomonaga, Akihiro Hata, Shigeyuki Kobayashi
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Patent number: 8391281Abstract: A network-on-chip router which includes an input buffer, an input controller connected to said input buffer, an arbiter connected to said input controller, a crossbar connected to said arbiter and said input buffer, and an output buffer connected to said crossbar. The network-on-chip router minimizes propagation time of data through the router by ensuring that the propagation delay of data through an input buffer is less than the combined propagation delay of data through an input controller and arbiter.Type: GrantFiled: March 31, 2010Date of Patent: March 5, 2013Assignee: Toshiba America Research, Inc.Inventor: Bipul C. Paul
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Patent number: 8385357Abstract: A network device of is a network device that transfers frames by repeating, in a constant cycle, a reserved transfer interval and a free transfer interval. The network device includes a transmission port, a cycle timer, a mode switching control unit that monitors a transfer state of the transmission port and selects a store-and-forward system when the transmission port is in the transfer process and selects a cut-through system when the transmission port is not in the transfer process, and a transfer prohibition control unit that selects the cut-through system as a transfer system when a non-reserved frame is transmitted and switches a transfer method of the non-reserved frame to the store-and-forward system when a reserved transfer interval is established, with reference to the cycle timer.Type: GrantFiled: March 26, 2009Date of Patent: February 26, 2013Assignee: Toyota Jidosha Kabushiki KaishaInventors: Junichi Takeuchi, Naoto Iga, Hideki Goto, Shinichi Iiyama
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Patent number: 8379647Abstract: A device may reserve a slot for a received packet in a packet ordering queue (POQ), convey the packet to one of a plurality of threads for processing, obtain the packet from the one of the plurality of threads after the packet has been processed, organize the packet in the POQ in accordance with a position of the reserved slot, and release the packet from the POQ if the reserved slot is a head of the POQ.Type: GrantFiled: October 23, 2007Date of Patent: February 19, 2013Assignee: Juniper Networks, Inc.Inventors: Chih-Wei Chao, Dongyi Jiang, Rakesh Gopala Krishnan Nair, Jiaxiang Su
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Patent number: 8363649Abstract: A generalized multi-link multi-stage network comprising (2×logdN)?1 stages is operated in strictly nonblocking manner for unicast, also in rearrangeably nonblocking manner for arbitrary fan-out multicast when s?2, and in strictly nonblocking manner for arbitrary fan-out multicast when s?3, includes an input stage having N/d switches with each of them having d inlet links and s×d outgoing links connecting to second stage switches, an output stage having N/d switches with each of them having d outlet links and s×d incoming links connecting from switches in the penultimate stage. The network also has (2×logdN)?3 middle stages with each middle stage having N/d switches, and each switch in the middle stage has s×d incoming links connecting from the switches in its immediate preceding stage, and s×d outgoing links connecting to the switches in its immediate succeeding stage. Also each multicast connection is set up by use of at most two outgoing links from the input stage switch.Type: GrantFiled: May 22, 2008Date of Patent: January 29, 2013Assignee: Konda Technologies Inc.Inventor: Venkat Konda
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Patent number: 8355329Abstract: The packet relay device includes a clock generation portion adapted to generate a clock signal of prescribed frequency as a standard for operation of the packet relay device; a timer portion adapted to count up a timer value over a first number of clock cycles on the basis of the clock signal; a relay control portion adapted relay received packets while limiting to a prescribed amount of packets the amount of packets forwardable per a predetermined increment of the timer value; and a power control portion adapted to reduce the frequency of the clock signal to 1/n in order to reduce power consumption by the packet relay device. If the frequency of the clock signal has been reduced to 1/n by the power control portion, the timer portion counts up the timer value over a number of clock cycles equivalent to 1/n the aforementioned number of clock cycles.Type: GrantFiled: October 2, 2009Date of Patent: January 15, 2013Assignee: Alaxala Networks CorporationInventor: Yuichi Ishikawa
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Patent number: 8351445Abstract: Network interface systems are disclosed comprising a bus interface system, a media access control system, a memory system, a security system for selectively encrypting outgoing data and decrypting incoming data, a checksum system for generating and verifying checksum values, and a segmentation system for selectively segmenting outgoing data, where the network interface system may be fabricated as a single integrated circuit chip. Methods are also provided for interfacing a host system with a network, in which checksum information is obtained from the host system, which is used to generate checksum values for outgoing data while the data is being stored in a network interface memory system.Type: GrantFiled: June 17, 2004Date of Patent: January 8, 2013Assignee: GlobalFoundries Inc.Inventors: Marufa Kaniz, Jeffrey Dwork, Chin-Wei Kate Liang, Kevin Pond, legal representative, Somnath Viswanath, Robert Alan Williams
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Patent number: 8351446Abstract: Provided herein are an electronic device, method and system for wireless communication over a wireless network. The device comprises an addressable point in network (Pin) which listens for all available wireless signals and creates and relays wireless signals containing destination address(es) for message(s) to other Pin(s). Wireless signal(s) are relayed from the Pin device(s) to other Pins over the network. Destination, receiving and originator Pin addresses and message flags within received messages are compared with message flags in a device memory trace queue to determine if the receiving Pin is the destination and/or origin of the message and whether the received message is retained and/or relayed or dropped. The system includes the Pin(s), a wireless communication network over which the message(s) are relayed to and from the Pin(s) and an enterprise provider information system (PIS) with an application stack configured to wirelessly transmit product and services information to the Pin(s).Type: GrantFiled: February 18, 2010Date of Patent: January 8, 2013Inventor: Michel Ghosn
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Patent number: 8351428Abstract: A digital broadcast transmitting/receiving system and a method for processing data are disclosed. The method for processing data may enhance the receiving performance of the receiving system by performing additional coding and multiplexing processes on the traffic information data and transmitting the processed data. Thus, robustness is provided to the traffic information data, thereby enabling the data to respond strongly against the channel environment which is always under constant and vast change.Type: GrantFiled: January 5, 2010Date of Patent: January 8, 2013Assignee: LG Electronics Inc.Inventors: Jin Pil Kim, Young In Kim, Ho Taek Hong, In Hwan Choi, Kook Yeon Kwak, Hyoung Gon Lee, Byoung Gill Kim, Jin Woo Kim, Jong Moon Kim, Won Gyu Song
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Patent number: 8345548Abstract: An example of a method comprises the steps of generating at a local node where a congestion emerges a first congestion information; sending the first congestion information to at least one upstream node; responsive to one received first congestion information comparing the content of the received first congestion information with a present local status based on a set of predefined rules in order to identify at least one packet stream causing the congestion, and generating a second congestion information comprising the identified at least one packet stream causing the congestion; and sending the second congestion information to at least one further upstream node from where the identified at least one packet stream was received.Type: GrantFiled: July 3, 2008Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Mircea Gusat, Marc Verhappen, Cyriel Minkenberg, Jose Dusto
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Patent number: 8347359Abstract: An encryption sentinel system and method protects sensitive data stored on a storage device and includes sentinel software that runs on a client machine, sentinel software that runs on a server machine, and a data storage device. When a client machine requests sensitive data from the data storage device, the data storage device interrogates the sentinel software on the server machine to determine if this client machine has previously been deemed to have proper encryption procedures and authentication. If the sentinel server software has this information stored, it provides an approval or denial to the storage device that releases the data if appropriate. If the sentinel server software does not have this information at hand or the previous information is too old, the sentinel server interrogates the sentinel software that resides on the client machine which scans the client machine and provides an encryption update to the sentinel server software, following which data will be released if appropriate.Type: GrantFiled: December 23, 2008Date of Patent: January 1, 2013Inventor: Bruce Backa
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Patent number: 8325749Abstract: In one embodiment, a method can include receiving at an egress schedule module a request to schedule transmission of a group of cells from an ingress queue through a switch fabric of a multi-stage switch. The ingress queue can be associated with an ingress stage of the multi-stage switch. The egress schedule module can be associated with an egress stage of the multi-stage switch. The method can also include determining, in response to the request, that an egress port at the egress stage of the multi-stage switch is available to transmit the group of cells from the multi-stage switch.Type: GrantFiled: December 24, 2008Date of Patent: December 4, 2012Assignee: Juniper Networks, Inc.Inventors: Sarin Thomas, Srihari Vegesna, Pradeep Sindhu, Chi-Chung Kenny Chen, Jean-Marc Frailong, David J. Ofelt, Philip A. Thomas, Chang-Hong Wu
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Patent number: 8325735Abstract: One embodiment includes distributing user traffic packets to a plurality of queues, and draining the queues of the user traffic packets according to a defined methodology. The drained user traffic packets are sent to a plurality of physical channel interfaces. Each of the plurality of physical channel interfaces interfaces with a respective channel of the backhaul. The sending step sends each of the drained user traffic packets to the physical channel.Type: GrantFiled: June 28, 2007Date of Patent: December 4, 2012Assignee: Alcatel LucentInventors: Mohammad Riaz Khawer, Mark H. Kraml, Stephen George Pisano, Tomas S. Yang
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Publication number: 20120300788Abstract: Systems and methods for a serial redirector device to provide services using serial communication redirection through a packet-based interface. In one implementation, the serial redirector device is configured to receive messages via a packet-based interface and redirect the same to a device in serial communication with the serial redirector device. The serial redirector mediates the communication between serially connected devices and devices connected via packet-based interfaces.Type: ApplicationFiled: May 25, 2012Publication date: November 29, 2012Applicant: NOMADIX, INC.Inventors: Vadim Olshansky, Allen Martin Swig
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Patent number: 8320392Abstract: A method and apparatus for programmable buffer with dynamic allocation to optimize system throughput with deadlock avoidance on switches have been disclosed where a buffer availability is based on a programmable reservation size for dynamic allocation.Type: GrantFiled: December 16, 2009Date of Patent: November 27, 2012Assignee: Integrated Device Technology, Inc.Inventors: Chi-Lie Wang, Jason Z Mo
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Patent number: 8306045Abstract: The packet forwarding apparatus of the present invention includes a packet buffer for temporarily storing packets to be forwarded, a timer for measuring the time of every predetermined unit period, a plurality of first queues corresponding to each of a plurality of address groups that form the packet buffer, a plurality of second queues that are provided corresponding to the property of the packets, a first controller for executing the writing of the packets, and a second controller for executing the discarding of the packets. According to this invention, through managing the first queues and the second queues, packets in the packet buffer can be discarded without the packets being read from the packet buffer.Type: GrantFiled: January 29, 2009Date of Patent: November 6, 2012Assignee: Fujitsu LimitedInventors: Akihiro Hata, Hiroshi Tomonaga, Katsumi Imamura
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Patent number: 8300526Abstract: The present invention provides a network relay apparatus capable of assuring the prevention of occurrence of order reversion of packets within flows and shifting a packet distribution destination according to load information. The network relay apparatus includes: a packet distribution processor for distributing input packets to thereby achieve load dispersion of packet processing; a statistical information collector for regularly collecting load conditions of respective packet processors; and a distribution information holder for retaining information for specifying the packet distribution destinations upon distribution of the packets. Information about the load conditions of the respective packet processors are compiled and distributed to the packet processor smallest in load. Timing provided to change the packet distribution destination is assumed to be given when a processing waiting queue does not include a packet corresponding to its flow.Type: GrantFiled: November 30, 2009Date of Patent: October 30, 2012Assignee: Hitachi, Ltd.Inventors: Shinichiro Saito, Xiping Lin, Haruo Yamashita
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Patent number: 8274988Abstract: Examples are disclosed for forwarding data partitioned into one or more cells through at least a portion of a three-stage memory-memory-memory (MMM) input-queued Clos-network (IQC) packet switch. In some examples, each module of the three-stage MMM IQC packet switch includes a virtual queue and a manager that are configured in cooperation with one another to forward cells through at least a portion of the switch. The cells may have been partitioned and stored at an input port for the switch and destined for an output port for the switch.Type: GrantFiled: July 29, 2009Date of Patent: September 25, 2012Assignee: New Jersey Institute of TechnologyInventors: Roberto Rojas-Cessa, Ziqian Dong
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Patent number: 8270423Abstract: Systems and methods for utilizing transaction boundary detection methods in queuing and retransmission decisions relating to network traffic are described. By detecting transaction boundaries and sizes, a client, server, or intermediary device may prioritize based on transaction sizes in queuing decisions, giving precedence to smaller transactions which may represent interactive and/or latency-sensitive traffic. Further, after detecting a transaction boundary, a device may retransmit one or more additional packets prompting acknowledgements, in order to ensure timely notification if the last packet of the transaction has been dropped. Systems and methods for potentially improving network latency, including retransmitting a dropped packet twice or more in order to avoid incurring additional delays due to a retransmitted packet being lost are also described.Type: GrantFiled: March 12, 2007Date of Patent: September 18, 2012Assignee: Citrix Systems, Inc.Inventors: Robert Plamondon, Michael Ovsiannikov, Allen Samuels
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Patent number: 8259739Abstract: A mechanism for combining plurality of point-to-point data channels to provide a high-bandwidth data channel having an aggregated bandwidth equivalent to the sum of the bandwidths of the data channels used is provided. A mechanism for scattering segments of incoming data packets, called data chunks, among available point-to-point data channel interfaces is further provided. A decision as to the data channel interface over which to send a data chunk to can be made by examining a fullness status of a FIFO coupled to each interface. An identifier of a data channel on which to expect a subsequent data chunk can be provided in a control word associated with a present chunk of data. Using such information in control words, a receive-end interface can reassemble packets by looking to the control word in a currently processing data chunk to find a subsequent data chunk.Type: GrantFiled: October 31, 2005Date of Patent: September 4, 2012Assignee: Cisco Technology, Inc.Inventors: Yiren R. Huang, Raymond Kloth
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Patent number: 8259710Abstract: An improved packet handler for VoIP cable modems and other high-speed digital devices includes a direct communication link via hardware among internal processing components. Incoming and outgoing digital information packets are filtered into MAC packets, voice PDU packets, and non-voice PDU packets, such that priority can be given to relaying voice packets and minimizing potential voice delay within the cable network. Hardware components, including specialized logic circuitry, modify voice packets to an appropriate signal form for subsequent signal processing or signal transmission. Proprietary bus communication protocols can also be provided to facilitate relay of packets between a central processing unit (CPU) and a digital signal processor (DSP) within a VoIP cable modem. Line cards including subscriber line interface circuit (SLIC) and subscriber line audio processing circuit (SLAC) components provide analog-to-digital (A/D) and digital-to-analog (D/A) conversion functionality.Type: GrantFiled: August 2, 2010Date of Patent: September 4, 2012Assignee: Rockstar Bidco, L.P.Inventor: Russell T. Enderby
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Patent number: 8254376Abstract: A method of dynamically adjusting the buffer delay of an adaptive jitter buffer of a network node receiving packets of a media stream from a packet switched network. The method comprises inserting packets arriving to the network node into the jitter buffer and executing a jitter buffering procedure once every Trepin, wherein Trepin is equal to the jitter buffer play-out interval. Executing the jitter buffer procedure involves updating a jitter protection time, Tjit, wherein Tjit defines a current target value for the maximum buffering delay, on the basis of the variation of the number of pending packets, N in the jitter buffer.Type: GrantFiled: January 25, 2008Date of Patent: August 28, 2012Assignee: Telefonaktiebolaget L M Ericsson (publ)Inventor: Arto Juhani Mahkonen
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Patent number: 8254339Abstract: In a receiver apparatus of HSDPA (High Speed Downlink Packet Access) data transmission scheme, it is achieved to minimize the occurrence of the system performance degradation and problems caused by TSN flash execution. In the receiver apparatus, each of a plurality of reordering buffers that temporarily store received traffic data is ranked on the basis of QoS information of the traffic data. When it is determined that memory release of the reordering buffers is necessary, the memory release is performed from the lowest ranked reordering buffer.Type: GrantFiled: July 7, 2005Date of Patent: August 28, 2012Assignee: Sony Mobile Communications Japan, Inc.Inventor: Isman Bazar
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Patent number: 8238346Abstract: A node in a mobile ad-hoc network or other network classifies packets (a) in accordance with a first set of priority levels based on urgency and (b) within each priority level of the first set, in accordance with a second set of priority levels based on importance. The node: (a) queues packets classified at highest priority levels of the first and/or second sets in high-priority output queues; (b) queues packets classified at medium priority levels of the first set in medium-priority output queue(s); and (3) queues packets classified at low priority levels of the first and/or second set in low-priority output queue(s). Using an output priority scheduler, the node serves the packets in order of the priorities of the output queues. In such manner, orthogonal aspects of DiffServ and MLPP can be resolved in a MANET or other network.Type: GrantFiled: July 9, 2009Date of Patent: August 7, 2012Assignee: The Boeing CompanyInventors: Wayne R. Howe, Muhammad Akber Qureshi
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Publication number: 20120195322Abstract: An apparatus comprising a chip comprising a plurality of nodes, wherein a first node from among the plurality of nodes is configured to receive a first flit comprising a first timestamp, receive a second flit comprising a second timestamp, determine whether the first flit is older than the second flit based on the first timestamp and the second timestamp, transmit the first flit before the second flit if the first flit is older than the second flit, and transmit the second flit before the first flit if the first flit is not older than the second flit.Type: ApplicationFiled: December 1, 2011Publication date: August 2, 2012Applicant: FUTUREWEI TECHNOLOGIES, INC.Inventors: Rohit Sunkam Ramanujam, Sailesh Kumar, William Lynch
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Patent number: 8228930Abstract: Interconnection router arrangements are implemented using a variety of arrangements and methods. Using one such arrangement, an interconnection network router arrangement sends data units between a set of router inputs and a set of router outputs. The interconnection network router arrangement includes a sub-switch that is capable of selectively transferring a data unit from an array of sub-switch inputs to an array of sub-switch outputs. The sub-switch has a memory circuit for storing the data unit before the data unit is transferred to a sub-switch output and a memory circuit for storing the data unit after the data unit is transferred from the sub-switch inputs and before the data unit is sent to a router output.Type: GrantFiled: June 2, 2006Date of Patent: July 24, 2012Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: John J. Kim, William J. Dally
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Patent number: 8229943Abstract: There is provided a computer-implemented method of modifying a query executing in a database management system. The method comprises sending a no-wait message for the query to a control broker. The method also comprises receiving a reply to the no-wait message from the control broker. The reply to the no-wait message specifies a modification to the query. Additionally, the method comprises performing the modification.Type: GrantFiled: August 26, 2010Date of Patent: July 24, 2012Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael J. Hanlon, Anoop Sharma, Subbarao Kakarlamudi, Selvaganesan Govindarajan
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Patent number: 8218439Abstract: An adaptive buffering scheme allows more effective media transport and buffering. In one aspect of the adaptive buffering scheme, buffering parameters are adapted to different media characteristics, such as media play commands or the amount of encoding/transcoding required for the particular media stream. In another aspect of the adaptive buffering scheme, buffering is adapted to different transmission or memory conditions, such as transmission rate, packet jitter, or the amount of available buffer memory. In one example, the adaptive buffering is supported using Real Time Streaming Protocol (RTSP), and/or Real Time Transport Protocol (RTP) and associated Real Time Control Protocol (RTCP), and/or Session Description Protocol (SDP) messages.Type: GrantFiled: November 14, 2005Date of Patent: July 10, 2012Assignee: Sharp Laboratories of America, Inc.Inventor: Sachin G. Deshpande
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Patent number: 8218546Abstract: A network device for processing packets includes at least one ingress module for performing switching functions on a packet, a memory management unit for storing the packet and at least one egress module for transmitting the packet to at least one port. The at least one egress module is configured to maintain multiple queues for the at least one port, including a purge queue, and to store the packet in the purge queue when an error condition is determined when the end of the packet is received by the at least one ingress module.Type: GrantFiled: November 13, 2006Date of Patent: July 10, 2012Assignee: Broadcom CorporationInventor: Eugene Opsasnick
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Patent number: 8213449Abstract: Methods and systems are provided for aging EV-DO pages in a queue based on latency-sensitivity. An access node receives data for access terminals, and responsively generates pages and adds them to the back of a queue. The access node associates a respective aging value with any latency-tolerant pages. The access node transmits the pages in the queue, which involves: (a) assessing the pages on a first-in, first-out basis; (b) transmitting latency-sensitive pages when those pages reach the front of the queue; (c) sending latency-tolerant pages to the back of the queue (and incrementing their aging values) when those pages reach the front of the queue with an aging value that is less than a maximum-delay parameter; and (d) transmitting latency-tolerant pages when those pages reach the front of the queue with an aging value that is greater than or equal to the maximum-delay parameter.Type: GrantFiled: August 29, 2008Date of Patent: July 3, 2012Assignee: Sprint Spectrum L.P.Inventors: Andrew M. Wurtenberger, Rajveen Narendran
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Patent number: 8213421Abstract: The present invention relates to communications networks, and more particularly to packet switching and routing devices used in communication networks that provide efficient multicast services. The invention provides methods and systems for switching and routing of multicast data packets in two stages. In particular, in the first stage a received multicast data packet is in an internal multicast operation by an ingress line card across a switching fabric to a plurality of egress line cards through which multicast destinations of the packet are reachable. In a second stage each egress line card further replicates the data packet to the actual transmission links across which the multicast group are reachable. This invention also includes system performing this method. The invention reduces the service time for the multicast packets making it the same as for the unicast packets, and provides for better system throughput in comparison to traditional systems.Type: GrantFiled: May 3, 2004Date of Patent: July 3, 2012Assignee: Alcatel LucentInventors: Nabil N. Bitar, Thomas A. Hoch, Martin Kannampuzha Varghese
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Patent number: 8213445Abstract: An apparatus including a holding portion temporarily holding packets for each individual quality class; a counter counting the amount of data of packets output from the holding portion for each individual quality class; a comparison portion comparing count values of the counter for individual quality classes with threshold values which are threshold values for the quality classes, respectively, the ratio of the threshold values for the quality classes being coincident with the weighting ratio between the quality classes; an output portion outputting packets held in the holding portion based on results of comparisons made by the comparison portion; and a control portion which, according to the results of the comparisons, subtracts values corresponding to the threshold values for the quality classes from the count values of the counter for the individual quality classes.Type: GrantFiled: March 11, 2008Date of Patent: July 3, 2012Assignee: Fujitsu LimitedInventor: Hiroshi Murakawa
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Patent number: 8194653Abstract: Network data switching includes receiving a cell; associating the cell with a destination port; selecting, based at least in part on a mapping of a plurality of output ports and a plurality of egress links, a selected egress link that has been soft configured to be associated with the destination port, wherein each of the plurality of egress links is configured to send data from a switch fabric to a corresponding access node; and switching the cell to the selected egress link.Type: GrantFiled: March 4, 2008Date of Patent: June 5, 2012Assignee: Alcatel LucentInventors: Nelson Willhite, Mike Noll, Robert Steven Martin, Akhil Duggal, Craig Lindberg, Thomas Carleton Jones, Srinivas Komidi
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Patent number: 8194690Abstract: Packets are processed in a system that comprises a plurality of interconnected processor cores. The system receives packets into one or more queues. The system associates at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate. The system maps a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and based on at least one rate associated with a node not in the set. The packets are processed in one or more processor cores including the mapped processor core according to the hierarchy.Type: GrantFiled: May 24, 2007Date of Patent: June 5, 2012Assignee: Tilera CorporationInventors: Kenneth M. Steele, Vijay Aggarwal
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Patent number: 8190770Abstract: A system and method of transmitting data frames between a plurality of input ports to a plurality of output ports is described. The input ports segment portions of the received data frames to provide smaller data cells which are individually transmitted to an output port associated with a destination of the segmented data frame. Based upon information provided in the data cells received at the output port, the output port determines the ordinal positions of the received data cells within the segmented data frame and reassembles the data frame which was segmented at the input port. The output port then forwards the reassembled frame toward the associated destination.Type: GrantFiled: May 18, 2009Date of Patent: May 29, 2012Assignee: Intel CorporationInventor: Robert M Grow
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Patent number: 8189599Abstract: A reconfigurable, protocol indifferent bit stream-processing engine, and related systems and data communication methodologies, are adapted to achieve the goal of providing inter-fabric interoperability among high-speed networks operating a speeds of at least 10 gigabits per second. The bit-stream processing engine operates as an omni-protocol, multi-stage processor that can be configured with appropriate switches and related network elements to create a seamless network fabric that permits interoperability not only among existing communication protocols, but also with the ability to accommodate future communication protocols. The method and systems of the present invention are applicable to networks that include storage networks, communication networks and processor networks.Type: GrantFiled: August 24, 2010Date of Patent: May 29, 2012Assignee: RPX CorporationInventors: Viswa Sharma, Roger Holschbach, Bart Stuck, William Chu
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Patent number: 8184649Abstract: In a system in which several data links are available for the transmission while one respective sending unit is allocated to the data links to temporarily store data that is to be transmitted via the respective data link, data packets containing non-real-time critical data are subdivided into fragments of variable sizes prior to forwarding to a sending unit. Data packets containing real time-critical data are preferably forwarded to a sending unit without being fragmented. Additionally, a minimum fragment size can be predefined for the fragmentation process.Type: GrantFiled: August 30, 2005Date of Patent: May 22, 2012Assignee: Siemens Enterprise Communications GmbH & Co. KGInventors: Birgit Bammesreiter, Wolfgang Entler, Klaus Wenninger
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Patent number: 8175085Abstract: A scaling device or striper improves the lane efficiency of switch fabric. The striper controls or adjusts transfer modes and payload sizes of a large variety of devices operating with different protocols. The striper interfaces between network devices and the switch fabric, and the resulting switching system is configurable by a single controller. A source device sends a data packet to its corresponding striper for transmission across the switch fabric to a destination device. The corresponding striper parses the packet to determine its type and payload length, and divides the packet into numerous smaller segments when the payload length exceeds a predetermined length. The segments may be stored in the striper to adapt to the available bandwidth of the switch. The segments are sent across the switch fabric and reassembled at a destination striper. The packet as reassembled is forwarded to the destination device.Type: GrantFiled: January 14, 2009Date of Patent: May 8, 2012Assignee: Fusion-io, Inc.Inventors: Kiron Malwankar, Daniel Talayco
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Patent number: 8160086Abstract: A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulated spread spectrum clock (SSC) enabled source having predetermined spread spectrum link clock frequency characteristics, and at least one output for transmitting the data packets after passage through the switch, the switch further comprising at least one receive buffer having a link side and a core side for receiving the SSC modulated input data packets from the link, at least one transmit buffer and a core clock, wherein the core clock operates at a given frequency between predetermined error limits determined by oscillation accuracy alone and is not SSC-enabled, the core clock frequency being set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side.Type: GrantFiled: October 14, 2008Date of Patent: April 17, 2012Assignee: VirtenSys LimitedInventors: Finbar Naven, John Roger Drewry
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Patent number: 8160863Abstract: A system and method for connecting a running logic circuit simulation to a network running at a higher speed that includes a computer for receiving data packets from the network and storing the received data packets in a first buffer. The computer next transmits the received data packets to an electronic circuit in the logic circuit simulation at a slower speed. The computer also receives data packets from the electronic device under simulation, and stores the data packets received from the electronic device under simulation in a second buffer. The computer then transmits the data packets received from the electronic device under simulation to the network at a higher speed.Type: GrantFiled: November 19, 2001Date of Patent: April 17, 2012Assignee: Ionipas Transfer Company, LLCInventor: Robert M. Zeidman
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Patent number: 8155134Abstract: A Queue Manager (QM) system and method are provided for communicating control messages between processors. The method accepts control messages from a source processor addressed to a destination processor. The control messages are loaded in a first-in first-out (FIFO) queue associated with the destination processor. Then, the method serially supplies loaded control messages to the destination processor from the queue. The messages may be accepted from a plurality of source processors addressed to the same destination processor. The control messages are added to the queue in the order in which they are received. In one aspect, a plurality of parallel FIFO queues may be established that are associated with the same destination processor. Then, the method differentiates the control messages into the parallel FIFO queues and supplies control messages from the parallel FIFO queues in an order responsive to criteria such as queue ranking, weighting, or shaping.Type: GrantFiled: September 29, 2007Date of Patent: April 10, 2012Assignee: Applied Micro Circuits CorporationInventors: Mark Fairhurst, John Dickey
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Patent number: 8149856Abstract: Each of the plurality of queues stores packet data of a received packet. The read concession assignor assigns one of the plurality of queues with a read concession for a predefined time period. The overdraft storage stores an overdraft amount in connection with each of the plurality of queues. The read adequacy determiner determines, in accordance with an overdraft amount stored in connection with one queue out of the plurality of queues, whether to read packet data from the one queue. The overdraft updater updates at least one of a first overdraft amount stored in connection with a first queue and a second overdraft amount stored in connection with a second queue different from the first queue upon reading packet data from the first queue during a time period while the second queue is assigned with the read concession.Type: GrantFiled: September 24, 2009Date of Patent: April 3, 2012Assignee: Fujitsu LimitedInventors: Hiroyuki Kogata, Hisaya Ogasawara, Akio Shinohara