Abstract: A method may include receiving a data unit and identifying a state of a memory storing data units. The method may include selecting a threshold value having a first threshold unit or a second threshold unit based on the state of the memory. The method may include comparing the threshold value to a queue state using the first threshold unit if the memory is in a first state. The method may include comparing the threshold value to the queue state using the second threshold unit if the memory is in a second state.

Abstract: A communication device for transmitting and receiving frames, which is capable of preventing an overflow of a buffer memory due to clock error even when the utilization factor of a transmission line is high. A frame holding section stores frames awaiting transmission. A transmission section sequentially takes out each frame from the frame holding section and outputs the frame to the transmission line, based on a control signal indicative of timing for transmitting the frame. A transmission control section initially outputs the control signal at a repetition period of T clocks (T?2) and acquires the number of waiting frames in the frame holding section every N×T clocks (N?2).

Abstract: A process is described to build physical layer frames with a modcode adapted to the signal quality of a destination terminal. Data packets assigned to the same modcode may be sent in the same frame, although packets associated with higher modcodes may be used to complete a frame before switching to the applicable higher modcode for construction of subsequent frames. After an interval, the order of progression is restarted with an out of order packet above a threshold age. Flow control filtering mechanisms and a variable reliability margin may be used to adapt dynamically to the current data traffic conditions.

Abstract: Methods and systems for processing signals in a communication system are disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while simultaneously storing on-chip, a portion of the plurality of information bits in the received bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and the storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits may be partitioned into a functional data processing path and a functional address processing path.

Abstract: A method of generating frame receive interrupts in an Ethernet controller including receiving incoming data frames and storing data frames into a receive queue, monitoring the number of received data frames, and when the number of received data frames exceeds a first threshold, generating a frame receive interrupt. In another embodiment, the method further includes monitoring the amount of received data stored in the receive queue and generating a frame receive interrupt when the first threshold is exceeded and when the amount of received data stored in the receive queue exceeds a second threshold. In yet another embodiment, the method further includes monitoring the time duration of the data frames stored in the receive queue, and generating a frame receive interrupt when the number of received data frames exceeds the first threshold or when the time duration of the data frames stored in the receive queue exceeds a third threshold.

Abstract: Embodiments of the invention provide a packet processing circuit card with scalable performance at specified operational bandwidths over a given range of bandwidths. Advantageously, these embodiments enable a packet processing circuit card developed for a high bandwidth application to be used in a lower bandwidth application. This allows for cost-effective scaling of packet processing performance to the needs of the data communications system.

Abstract: Techniques for accelerating network receive side processing of packets. Packets may be associated into flow groupings and stored in flow buffers. Packet headers that are available for TCP/IP processing may be provided for processing. If a payload associated with a header is not available for processing then a descriptor associated with the header is tagged as indicating the payload is not available for processing.

Abstract: Allocation of buffer space for segment re-ordering is restricted based on a probability that the flow would consume too much space. A flow's current or recently past space consumption is used to predict the flow's activity with respect to future consumption. If the prediction of future consumption is high relative to other flows and to the total allocable buffer space in the device, then a decreasing amount of space than would otherwise be provided is allocated to the flow. In a preferred embodiment, if a flow's buffers are below a predetermined threshold for the flow (i.e., the “flow threshold”), and the amount of overall system memory space is above a predetermined system threshold then buffer allocation can proceed normally for that flow. For example, all of an additional amount of space that the flow may currently be requesting can be allocated to the flow.

Abstract: A method and system for providing delay bound and prioritized packet dropping are disclosed. The system limits the size of a queue configured to deliver packets in FIFO order by a threshold based on a specified delay bound. Received packets are queued if the threshold is not exceeded. If the threshold is exceeded, a packet having a precedence level less than that of the precedence level of the received packet is dropped. If all packets in the queue have a precedence level greater than that of the packet received, then the received packet is dropped if the threshold is exceeded.

Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.

Abstract: A method for buffering variable length data at a decoupler includes receiving, at a decoupler, a request to queue variable length data from a producer, with the decoupler comprising a management header and a buffer pool. One of a plurality of fixed-length segments in the buffer pool is dynamically selected based, at least in part, on the management header. Buffer space in the selected segment is automatically allocated based on the request and the allocated space is then populated with the variable length data.

Abstract: A network device switches variable length data units from a source to a destination in a network. An input port receives the variable length data unit and a divider divides the variable length data unit into uniform length data units for temporary storage in the network device. A distributed memory includes a plurality of physically separated memory banks addressable using a single virtual address space and an input switch streams the uniform length data units across the memory banks based on the virtual address space. The network device further includes an output switch for extracting the uniform length data units from the distributed memory by using addresses of the uniform length data units within the virtual address space. The output switch reassembles the uniform length data units to reconstruct the variable length data unit. An output port receives the variable length data unit and transfers the variable length data unit to the destination.

Abstract: A switching device includes an ingress memory system having a VOQ-based design to provide an infrastructure for enabling fine-grained QoS and SLAs.

Abstract: The invention provides a system and method of controlling timing of release of traffic for a communication switch. The traffic originates from at least one source, is directed to a common ingress point of the switch and is directed to a common egress point in the switch. The egress point has a maximum egress transmission rate. The traffic has at least one datastream. Each datastream has a requested transmission rate. The method comprises, for each datastream, establishing a maximum cell release rate such that a sum of each of the maximum cell release rate does not exceed the maximum egress transmission rate and utilizing the maximum cell release rate to govern release of local traffic in the datastream from the ingress point.

Abstract: A network device receives a label-switched-path (LSP) labeled data packet, maps the LSP labeled data packet to an input queue, maps a data packet in the input queue to an output queue based on a received LSP label value and a received exp label value, and transmits the LSP labeled data packet from the output queue.

Abstract: The present invention provides a method of high speed assemble process capable of dealing with long packets with effective buffer memories usage. A processing method of fragmented packets in packet transfer equipment for transmitting and receiving packet data between terminals through network, includes, receiving fragmented packets, identifying whether the received packet is a packet fragmented into two from original, or a packet fragmented into three or more, for the packet identified as fragmented into two, storing the two fragmented packets into assembly buffer in fragmentation order, on basis of the respective offset values in the packets, and reading out from top, and for the packet fragmented into three or more, chain-connecting the assembly buffers and storing the packets therein in reception order, reading out the packets after deciding the order by comparing chain information and offset values of the fragmented packets within the chain, and then reassembling the packets.

Abstract: Methods, apparatus, data structures, computer-readable media, and mechanisms may include or be used with a hierarchy of schedules with propagation of minimum guaranteed scheduling rates among scheduling layers in a hierarchical schedule. The minimum guaranteed scheduling rate for a parent schedule entry is typically based on the summation of the minimum guaranteed scheduling rates of its immediate child schedule entries. This propagation of minimum rate scheduling guarantees for a class of traffic can be dynamic (e.g., based on the active traffic for this class of traffic, active services for this class of traffic), or statically configured. One embodiment also includes multiple scheduling lanes for scheduling items, such as, but not limited to packets or indications thereof, such that different categories of traffic (e.g., propagated minimum guaranteed scheduling rate, non-propagated minimum guaranteed scheduling rate, high priority, excess rate, etc.

Abstract: In one embodiment, a packet-based system having a number of buses is stimulated using apparatus having 1) a hardware interface configured to provide data packets to the buses; 2) a plurality of hardware-based queue schedulers, each configured to schedule data packets received from a respective one of a plurality of data packet sources, in a respective one of a plurality of hardware-based queues; and 3) a hardware-based priority scheduler configured to cause each particular queue to transmit a next highest priority data packet over one of the buses, based on i) timing requirements of the next highest priority data packet in the particular queue, and ii) a determination that transmission of the next highest priority data packet in the particular queue will not delay a transmission of a higher priority data packet in another one of the hardware-based queues.

Abstract: A weighted round-robin arbitrator for a plurality of data queue includes an arbitration table comprising a plurality of entries. Each entry represents a time slot for the transmission of one data packet from a selected one of the plurality of data queues. There is one arbitration logic circuit for each of the plurality of entries in the arbitration table. Each arbitration logic circuit includes a first multiplexer receiving an output from a first table entry and an output from a second table entry in the arbitration table. A second multiplexer receives empty flags from each of the data queues, the flags indicating that there is no data to the sent from that queue.

Abstract: A method, apparatus and computer program product are provided for optimizing packet flow control through buffer status forwarding. A sending device includes buffer status information of the sending device in transactions being sent to a receiving device. The receiving device uses the buffer status information of the sending device for selecting transactions to offload.

Abstract: An audio-on-demand communication system provides real-time playback of audio data transferred via telephone lines or other communication links. One or more audio servers include memory banks which store compressed audio data. At the request of a user at a subscriber PC, an audio server transmits the compressed audio data over the communication link to the subscriber PC. The subscriber PC receives and decompresses the transmitted audio data in less than real-time using only the processing power of the CPU within the subscriber PC. According to one aspect of the present invention, high quality audio data compressed according to lossless compression techniques is transmitted together with normal quality audio data. According to another aspect of the present invention, metadata, or extra data, such as text, captions, still images, etc., is transmitted with audio data and is simultaneously displayed with corresponding audio data.

Abstract: A high speed and high capacity switching apparatus is disclosed. The apparatus includes: N input ports each of which for outputting maximum l cells in a time slot, wherein each of the N input ports includes N virtual output queues (VOQs) which are grouped in l virtual output queues group with n VOQs; N×N switch fabric having l2 crossbar switch units for scheduling cells inputted from N input ports based on a first arbitration function based on a round-robin, wherein l VOQ groups are connected to l XSUs; and N output ports connected to l XSUs for selecting one cell from l XSUs in a cell time slot by scheduling cells by a second arbitration function based on a backlog weighed round-robin, which operates independently of the first arbitration function, and transferring the selected cell to its output link.

Abstract: Systems and methods employing a flexible mesh structure for hierarchical scheduling are disclosed. The method generally includes reading a packet grouping configured in a two dimensional mesh structure of N columns, each containing M packets, selecting and promoting a column best packet from each column to a final row containing N packets, reading, selecting and promoting a final best packet from the final row to a next level in the hierarchy. Each time a final best packet is selected and promoted, the mesh structure can be refreshed by replacing the packet corresponding to the final best packet, and reading, selecting and promoting a column best packet from the column containing the replacement packet to the final row. As only the column containing the replacement packet and the final row are read and compared for each refresh, the mesh structure results in reduced read and compare cycles for schedule determination.

Abstract: A TCP acceleration apparatus includes input queues each having a service level and storing at least one session packet list having packets from a same TCP session. The apparatus also includes a distributor connected to the input queues and to the client and configured to retrieve a session packet from a session packet list at a top of an input queue for transmission to the client. The input queue at the service level selected by the distributor moves the session packet list at a top of the input queue to a bottom of the input queue after the session packet is retrieved by the distributor. Acceleration apparatuses including other features, as well as a method, computer program product and system for TCP acceleration are also discussed.

Abstract: According to the invention, a method for processing an audio media stream that originates from a packet communication network is disclosed. In one step, packets are received as they arrive from the packet communication network. The packets are part of the audio media stream. A playout buffer in a media playout device is monitored. It is determined that the playout buffer is filled below a threshold. A portion of the audio media stream is retrieved when the playout buffer is filled below the threshold. The portion is stored in the playout buffer of the media playout device.

Abstract: Disclosed is a device, a computer program and a method to receive and buffer data packets that contain information that is representative of time-ordered content, such as a voice signal, that is intended to be presented to a person in a substantially continuous and substantially uniform temporal sequence; to decode the information to obtain samples and to buffer the samples prior to generating a playout signal. The samples are time scaled as a function of packet network conditions to enable changing the play-out rate to provide a substantially continuous output signal when the data packets are received at a rate that differs from a rate at which the data packets are created. The time scaling operation operates with a base delay that is controlled in a positive sense when the data packets are received at a rate that is slower than a rate at which the data packets are created, and a reserve delay that is managed to provide insurance against an interruption should the base delay become negative.

Abstract: A method and apparatus to perform buffer management for media processing are described.

Abstract: An improved combined Switching Data Unit (SDU) queuing discipline for unicast and multicast (Protocol Data Unit) PDU forwarding at a switching node is provided. Multicast SDU descriptors are replicated and stored in entries of a First-In/First-Out queue portion of a hybrid output port queue. Unicast SDU descriptors are chained in entries of a linked list queue portion of the hybrid output port queue. Servicing of the hybrid queue uses hybrid queue counters, and inter-departure-counters stored in multicast FIFO queue entries to keep track of the number of unicast SDU linked list entries, to be serviced between the multicast FIFO queue entries. The combined hybrid queue derives storage efficiency benefits from linking unicast PDUs in linked lists and further derives benefits from a simple access to multicast PDU entries.

Abstract: A method and system for use in data communications. The method and system substantially ensure that actual data transmission per unit time from at least one cross-point buffer switch ingress to at least one cross-point buffer switch egress substantially satisfies a designated target amount of actual data transmission per unit time.

Abstract: A method and system for transmitting packets in a packet switching network. Packets received by a packet processor may be prioritized based on the urgency to process them. Packets that are urgent to be processed may be referred to as real-time packets. Packets that are not urgent to be processed may be referred to as non-real-time packets. Real-time packets have a higher priority to be processed than non-real-time packets. A real-time packet may either be discarded or transmitted into a real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time queue congestion conditions. A non-real-time packet may either be discarded or transmitted into a non-real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time and non-real-time queue congestion conditions.

Abstract: A method is described that resets a first count and resets a second count if a first transmission unit is recognized as being within a new measurement time window. The first transmission unit has a size. The method also increments the first count by the first transmission unit size and by the size of each subsequent transmission unit that is received within the new measurement time window after the first transmission unit—so long as the first count does not exceed a maximum allowable value for the first count. The method also checks if a maximum value for the second count is exceeded if it is incremented by a second transmission unit size. The second transmission unit is received within the measurement time window. The check is in response to a determination that the first count would have exceeded the first count maximum allowable valuable if the first count were incremented by the second transmission unit size.

Abstract: An MIQ packet switch device and packet switching method are provided. The MIQ packet switch device performs cell-based switching of packet data, and includes one or more input queue arrays for buffering cells input through one or more input ports. Each of the one or more input queue arrays includes an input interface for outputting the cells to one or more output ports. The one or more input queue arrays further include a switch matrix for switching and outputting each of the cells transferred by the input interface to a corresponding output port of the one or more output ports. The one or more queue arrays also include a scheduler for receiving descriptor information for cell scheduling from each of the one or more input queue arrays, and creating control information for controlling each of the one or more input queue arrays to selectively output the cells, based on the descriptor information.

Abstract: An electronic communications device including a user input device for inputting characters; and buffering and communications systems for storing in a buffer characters input by the user input device, and transmitting the content of the buffer over a communications link when there is a pause in input by the user input device for a predetermined time duration. The content of the buffer may also be transmitted over the communications link when the amount of stored characters in the buffer reaches a predetermined size, or when a designated submit key is detected.

Abstract: A method and system for managing asynchronous transfer mode (ATM) traffic in a computer system is disclosed. The computer system is used in sending, receiving, or sending and receiving a plurality of ATM flows. Each ATM flow has a plurality of ATM cells, a minimum ATM bandwidth guarantee, and a maximum ATM bandwidth. The method and system include determining whether excess bandwidth exists for the ATM flows. The method and system also include gracefully increasing a portion of the ATM cells transmitted for each ATM flow during periods of excess bandwidth. The portion of the ATM cells transmitted is not more than the maximum ATM bandwidth limit. If an ATM flow presents a sufficient offered load, the portion of the ATM cells transmitted in the flow is not less than a minimum ATM bandwidth guarantee.

Abstract: There is disclosed an QoS-oriented burstification method supporting various grades of burstification delay guarantee. For the arrival packets, the packets are sequentially inserted in a sequence of windows on weight basis, thereby forming a queue. The window size together with the weight of each flow determines a maximum number of packets of each flow in a window. For the departure packets, there is generated a burst consisting of a plurality of packets from the head of the queue when either a total number of packets reaches a maximum burst size or a burst assembly timer expires.

Abstract: In a multitasking system executing real-time harmonic and dynamic tasks having various priority levels, slack is stolen from timeline and reclaimed slack to enable execution of high priority non-essential tasks on a best efforts basis. Counts of the amount of slack consumed, slack reclaimed, and periodic compute time consumed are maintained by individual priority level and dynamically updated at certain times. Idle time is calculated by priority level. Available slack is calculated, allocated and consumed by rate, with the highest rate first and the lowest last. Slack is made available to tasks in more than one time partition. All slack belongs to a common system-wide pool of slack obtained from any one or more time partitions. Common slack can also be time-shared by static, non-harmonic tasks residing in different time partitions. Also described are a computer system and methods that perform slack scheduling in a time-partitioned system.

Abstract: Input buffer type packet switching equipment, which can output cells to an external output line having a slower output line rate than a corresponding input line rate without having buffers in its output line sections, is provided. The input buffer type packet switching equipment provides M input line buffers that store cells inputted from M input lines temporarily in a state that one of the M input line buffers stores cells inputted from corresponding one of the M input lines, in this the M is an integer being 2 or more, an M×N crossbar type switch, which provides N output lines, for switching cells outputted from the M input line buffers based on a cross point on/off control signal, in this N is an integer being 2 or more.

Abstract: In a first aspect, a network processor includes a scheduler in which a scheduling queue is maintained. A last frame is dispatched from a flow queue maintained in the network processor, thereby emptying the flow queue. Data indicative of the size of the dispatched last frame is stored in association with the scheduler. A new frame corresponding to the emptied flow queue is received, and the flow corresponding to the emptied flow queue is attached to the scheduling queue. The flow is attached to the scheduling queue at a distance D from a current pointer for the scheduling queue. The distance D is determined based at least in part on the stored data indicative of the size of the dispatched last frame.

Abstract: Mechanisms for reducing the number of block masks required for programming multiple access control lists in an associative memory are disclosed. A combined ordering of masks corresponding to multiple access control lists (ACLs) is typically identified, with the multiple ACLs including n ACLs. An n-dimensional array is generated, wherein each axis of the n-dimensional array corresponds to masks in their requisite order of a different one of the multiple ACLs. The n-dimensional array progressively identifies numbers of different masks required for subset orderings of masks required for subsets of the multiple ACLs. The n-dimensional array is traversed to identify a sequence of masks corresponding to a single ordering of masks including masks required for each of the multiple ACLs.

Abstract: The present invention relates to high speed communications, in particular, to an interface device between a transmitting device and a receiving device of a transmission system, wherein the transmitting device is capable of automatic compensation of cross-talk timing errors in the interface device, for a group of signals, by using information stored in a storage attached to that interface device. Preferably, the data stored in said storage comprises data on interconnections between said first and second plurality of terminals and data on crosstalk timing errors in said transmission lines relating to a specific data pattern, for each of said stored interconnection.

Abstract: Queues which correspond to each of the LANs in multiplexed virtual LANs are created. Received packets are distributed to the queues in accordance with a VLAN-ID and a destination address included in each of the received packets. The packets are output from the respective queues in a predetermined order, thereby ensuring fairness among the virtual LANs. As a result, even if a user of a virtual LAN transmits data with traffic having a wide transmission band, the virtual LAN does not occupy the band of the physical port and does not hamper transmission of other users.

Abstract: A method and apparatus for in-line processing a data packet while routing the packet through a router in a system transmitting data packets between a source and a destination over a network including the router. The method includes receiving the data packet and pre-processing layer header data for the data packet as the data packet is received and prior to transferring any portion of the data packet to packet memory. The data packet is thereafter stored in the packet memory. A routing through the router is determined including a next hop index describing the next connection in the network. The data packet is retrieved from the packet memory and a new layer header for the data packet is constructed from the next hop index while the data packet is being retrieved from memory. The new layer header is coupled to the data packet prior to transfer from the router.

Abstract: A method for sharing signaling event data in a telephony system can include receiving within a first service logic component an event from a telephony signaling network. An event context can be determined for the event and asynchronously stored within an event context cache communicatively linked with at least said first service logic component and a second service logic component.

Abstract: A packet switching system arbitrates between Virtual Output Queues (VoQ) in plural input buffers, so as to grant the right of transmitting data to a crossbar switch to some of the VoQs by taking both an output data interval of a VoQ and the queue length of a VoQ as parameters. The system suppresses the delay time of the segment of a VoQ having a high load, thereby preventing buffers from overflowing; and, also, the system permits a VoQ having a low load to transmit segments under no influence of the VoQ that has a high load and is just reading out the segment.

Abstract: A method and system for managing memory in a packet switching device is disclosed. The method and system comprises managing the memory as a single FIFO when inserting packets and managing the memory as a plurality of FIFO queues when removing packets. A memory management scheme in accordance with the present invention takes advantage of the nature of packet switching to give an efficient implementation of multiple independent queues in a memory. The key observation that is made is that in a packet switch it is expected that packets may be stored in the memory for a time no greater than the time it takes to fill up the memory. If a packet due to extreme congestion is delayed longer than that, then deleting that packet is an acceptable result.

Abstract: A method and system for transporting traffic having disparate qualities of service classes across a packet-switched network includes receiving at an ingress node of a network a plurality of packets each comprising a quality of service (QoS) class defined externally to the network. Packets having a QoS class comprising delay bound guarantees and a low drop priority are combined into a first internal QoS class. Packets having a QoS class comprising a flexible drop priority and no delay bound guarantees are combined into a second internal QoS class. Packets having a QoS class including no delivery guarantees are combined into a third internal QoS class. The packets are transmitted in the network based on their internal QoS class.

Abstract: A method and system for implementing weighted fair flow control on a metropolitan area network. Weighted fair flow control is implemented using a plurality of metro packet switches (MPS), each including a respective plurality of virtual queues and a respective plurality of per flow queues. Each MPS accepts data from a respective plurality of local input flows. Each local input flow has a respective quality of service (QoS) associated therewith. The data of the local input flows are queued using the per flow queues, with each input flow having its respective per flow queue. Each virtual queue maintains a track of the flow rate of its respective local input flow. Data is transmitted from the local input flows of each MPS across a communications channel of the network and the bandwidth of the communications channel is allocated in accordance with the QoS of each local input flow. The QoS is used to determine the rate of transmission of the local input flow from the per flow queue to the communications channel.

Abstract: A communication control device includes a determination circuit for determining whether reception of an asynchronous packet from an IEEE 1394 serial bus is allowed or denied by comparing the sum of the size of the asynchronous packet to be received and the size of packets currently stored in a receive FIFO unit with the size of packets which can be stored in the receive FIFO unit. The communication control device further includes an acknowledge generating circuit for generating an acknowledge signal asserting whether reception of the asynchronous packet is allowed or denied based on the determination result of the determination circuit, and the generated acknowledge signal is sent back to the IEEE 1394 serial bus.

Abstract: There is provided a packet scheduler for managing output awaiting packets stored in a plural of queue blocks each having a weighting coefficient settled based on an output guaranteeing bandwidth, whereby an output order for the head packets is stored in respective queue blocks. The packet scheduler includes means for controlling selection of a queue having a packet to be sent at the highest priority, based on scheduled output time information obtained by calculation using management information of the output awaiting packets and the weighting coefficient of each queue, and means for correcting processing carried out in the controlling means based on the current time information. The arrangement enables to ensure assignment of vacant bandwidth in a fair manner while suppressing erroneous operation deriving from deviation of a scheduled packet output time from the real time caused by a calculation error or the like in WFQ calculation.

Abstract: In general, in one aspect, the invention features a method, apparatus, and computer-readable media for sending a frame of data from a first channel to a second channel using at least one of m memory buffers for storing a frame, m being at least 2, in which n of the m buffers have an available status and p of the m buffers have an unavailable status, wherein m=n+p.