Abstract: To ensure seamless reproduction of video data and audio data even when the video data and audio data are edited video object unit by video object unit in multiplexing of the video data and audio data, a playback time of the video data is compared with that of the audio data and packets are multiplexed in such a way that a video packet and an audio packet to be reproduced within a given timing range are included in the same video object unit.

Abstract: An improvement is provided to a network switch of the type including a set of input and output ports for receiving and forwarding data transmissions from and to network stations and a crosspoint switch for selectively routing data transmissions between the input and output ports. Each input port stores successive incoming data transmissions in an input buffer queue. When a data transmission reaches the head of the queue, the input port requests a route through the crosspoint switch to an output port that is to forward the transmission to a network station. When the output port is ready to receive the transmission the crosspoint switch establishes the route and the input port forwards the data transmission from its buffer queue to the output port. In the improved network switch, the input port discards the data transmission at the head of the buffer queue without forwarding it to an output port when necessary to make room in the buffer for incoming transmissions.

Abstract: In a mobile communication system using a code division multiple access (CDMA) method, spreading code detection and frame/slot timing synchronization (cell search) is conducted by using a long code masked symbol. The spreading factor of the long code masked symbol is set to a value lower than spreading factors of other ordinary symbols. As a result, it becomes possible to reduce the circuit scale and power dissipation of the mobile terminal and raise the speed of cell search.

Abstract: A ring interface is coupled to a current node in a ring network having a plurality of nodes and corresponding ring interface for each of said nodes. The ring interface includes a ring input port operative to conduct upstream message packets from a previous node to the ring interface, a ring output port operative to conduct message packets to a next node of the ring network, and a bypass queue operative to buffer message packets. A receive queue buffers message packets before passing them on to the current node. An address filter is coupled to the ring input port to receive the upstream message packets, read their destination addresses and pass them to the bypass queue if the addresses correspond to another node and pass them to the receive queue if their addresses are that of the current node.

Abstract: A load balancing system and method for network nodes is provided. The load balancing system includes crossbar devices, queues to receive data and a load balancer. The load balancer determines the amount of data in each of the queues and sends data to specific crossbar devices based on the amount of data in each queue. The queues include a high priority queue and a number of non-high priority queues.

Abstract: A packet transfer device that can be easily realized even when a number of input ports is large. Each input buffer temporarily stores entered packets class by class, and outputs packets of a selected class specified by the control unit, while the control unit determines the selected class of packets to be outputted from the input buffers according to a packet storage state in the packet storage units of the input buffers as a whole for each class. Each input buffer can temporarily store entered packets while selecting packets to be outputted at a next phase, and the control unit can specify packets to be selected in the input buffers according to an output state of packets previously selected in the input buffers as a whole. Packets stored in the buffer can be managed in terms of a plurality of groups, and each packet entered at the buffer can be distributed into a plurality of groups so that packets are distributed fairly among flows.

Abstract: The invention provides a method and apparatus for providing hitless protection switching in a synchronous transmission system. A switching apparatus is arranged to receive data signals on at least two transmission paths and to output data from a selected one of said transmission paths. The apparatus is arranged to align the respective received data signals so that a selector mechanism can select between corresponding elements of the received data signals. This arrangement allows hitless switching to be performed since there is no loss or repetition of signal elements when switching occurs. In a preferred embodiment, data in respect of each frame of each data signal is stored and the selector mechanism selects between paths on a frame-by-frame basis by comparing quality information carried by the data signals. This arrangement offers a very low end to end Bit Error Rate (BER) performance.

Abstract: An input or output switch port for a network switch converts each incoming packet into a cell sequence stores each cell in a cell memory. The switch port includes a traffic manager for queuing cells for departure from the cell memory and then signaling the cell memory to read out and forward cells in the order they are queued. The traffic manager selectively queues cells for departure on either a cell-by-cell or sequence-by-sequence basis. When cells are queued for departure on a cell-by-cell basis, cells of two or more sequences may be alternately read out and forwarded from the cell memory. Thus cells of different sequences may be interleaved with one another as they depart the cell memory. When a cell sequence is queued on a sequence-by-sequence basis all of its cells are read out of the cell memory and forwarded as a contiguous sequence and are not interleaved with cells of other sequences of the same departure queue.

Abstract: A packet multiplexing apparatus is presented for multiplexing packets to be transmitted from a number of user facilities to a local service node in such a way to assure equal access to the output port for all the users. The apparatus is provided with input ports for inputting a packet in a respective input port; a buffer memory provided for each input port for temporary storage of a packet; an output signal transmission circuit for retrieving a packet from each buffer memory in a specific sequence; an output port for transmitting packets output from the output signal transmission circuit; and a retrieval sequencing section for controlling the specific sequence by changing a retrieving order of packets from buffer memories for each complete round of packet retrieval so that a frequency of the retrieving order for each input port is uniformly shared by the input ports.

Abstract: Disclosed herein is a system architecture capable of processing fixed length and/or variable length data packets. Under the method of the invention, incoming data packets are queued together according to their corresponding switch processing parameters (SPPs), and then the commonly-queued data packets are processed through a switch fabric as a single unit. In one aspect of the invention, the commonly-queued data packets are processed by the switch fabric as a single train packet. In another aspect of the invention, the commonly-queued data packets are sliced into a set of subtrain packets. A switch fabric then processes the set of subtrain packets in parallel using a plurality of switch planes. Both aspects of the invention can be implemented with a plurality of packet formatters and deformatters linked to a switch fabric in various configurations, including multi-path and hierarchical switching systems. a multichannel switching system.

Abstract: Apparatus for routing packets in a communication network comprises a plurality of per-connection queues, each queue established for receiving packets from a respective source and temporarily storing received packets before routing to a particular destination; a weighted fair-queuing scheduler for servicing packets from each of the plurality of per-connection queues at guaranteed pre-allocated rates; a sensing device for sensing a presence or absence of packets in queues, the absence of packets in queues indicating availability of excess bandwidth; and, a state dependent scheduler for redistributing excess bandwidth upon sensing of queues absent packets, the state dependent scheduler servicing those queues in accordance with a state variable corresponding to a performance property of the queues, wherein delay and isolation properties for routing packets of respective queues in weighted fair-queuing is preserved.

Abstract: A packet switch which can cyclically use &agr; scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by &agr; scheduler sections independently performing scheduling processes is disclosed.

Abstract: A method of controlling the flow of traffic in synchronous transfer mode (ATM) network (10), which brings into possible existence a class (class II) of ATM cells. The ATM network (10) comprises one or more ATM switches (14) coupled by links (20) providing communication channels between the ATM switches (14). The method subjects the class II cells received at an input port of a particular ATM switch (14) to control, originating within the switching element of that ATM switch. The method allows only up to a fixed number of class II cells from a particular input port to be in the switch awaiting onward transfer. Although the control is on class, it nonetheless tends to produce fairness in service among different connections.

Abstract: A method of processing frames received at a sending port of a switching device for communication to a destination port includes storing in the switching device an offset value, a comparator value, and an expectant value; comparing information located at a position in a frame determined by the offset value with the comparator value to obtain an outcome; and processing the frame with the outcome. Processing the frame may include communicating the frame to a destination port or setting the priority of the frame. The offset and comparator values may be part of a filter that also includes an anchor value from which the offset value is measured and a mask value that masks the frame information before comparison with the comparator value. Where there are a multiple of filters in the switching device, the method may include combining the filter outcomes to obtain a filter group outcome; and processing the frame with the group outcome. Combining the filter outcomes may include logically combining their outcomes.

Abstract: An apparatus and method for DBWRR (Delay Bound Weighted Round Robin) cell scheduling in an ATM (Asynchronous Transfer Mode) switch. More particularly, the present invention provides an apparatus and method for DBWRR cell scheduling in a high-speed ATM switch which can meet requirements for a cell transfer delay of real-time traffic in the ATM switch and minimize a processing overhead of the switch.

Abstract: Low speed switches operated under the common control of a global scheduler can be used to switch high speed data while preserving packet ordering if the incoming packets are queued in a temporal order. By operating several low speed switches in parallel, a high-speed switching capacity can be realized.

Abstract: An apparatus for transferring packetized data includes an input for receiving packetized data, a memory coupled to the input and configured to store the packetized data in queues, each queue having an associated size, an output for transmitting the packetized data coupled to the memory, and a controller operatively coupled to the memory and configured to control transfer of the packetized data from the memory to the output, the controller being configured to determine which of multiple of ranges of sizes of queues has the largest range of sizes of queues and at least one associated queue, and to discard packetized data of a selected queue from among the at least one associated queue.

Abstract: Opportunities to transmit ATM cells of identical level onto an ATM line are equally afforded to respective terminal side lines. In a cell assembler/disassembler, data from the terminal side lines 1100 are turned into ATM cells, and the ATM cells are assigned priority levels. Then, the ATM cells are stored in internal buffers 111-116 respectively corresponding to the terminal side lines 1100. The priority controller 1210 selects the ATM cells of the highest priority levels from within the respective internal buffers, and further selects the ATM cell of the highest priority level as an ATM cell to-be-transmitted from among the selected ATM cells. In the presence of a plurality of such ATM cells of the highest priority level, the priority controller 1210 determines the ATM cell to-be-transmitted in accordance with the priority sequence of the internal buffers in which the ATM cells of the highest priority level are stored.

Abstract: In a frame aligner, a serial/parallel converter converts an input serial data signal into a first parallel data signal. A first buffer receives the first parallel data signal to generate a first parallel data signal, and a second buffer receives the first parallel data signal to generate a second parallel data signal. A selector selects one of the first and second parallel data signals to generate a third parallel data signal. A parallel/serial converter converts the third parallel data signal into an output serial data signal. A buffer control circuit operates the first and second buffers at different phase timings in accordance with an input frame phase signal. A selector control circuit operates the selector in accordance with a difference in phase between the input frame phase signal and an output frame phase signal.

Abstract: A scheduler allowing high-speed scheduling scalable with the number of input and output ports of a crosspoint switch and suppressed unfairness among inputs is disclosed. The scheduler includes an M×M matrix of scheduling modules, each of which schedules packet forwarding connections from a corresponding input group of input ports to selected ones of a corresponding output group of output ports based on reservation information. A diagonal modulo pattorn is used to determine a set of M scheduling modules to avoid coming into collision with each other. Each determined scheduling module performs reservation of packet forwarding connections based on current reservation information and transfers updated reservation information in row and column directions of the M×M matrix.

Abstract: The invention provides an arbitration method and an arbiter circuit by which equal arbitration of output cells can be achieved with a comparatively simple configuration even where a very great number of queues are involved. The arbiter circuit includes a plurality of queues for storing output cells, and a plurality of round robins for successively providing the right of outputting output cells to the queues. The round robins are arranged in a multi-stage tree link configuration, and the queues are distributed under those of the round robins which are in the lowest order stage. Each of the round robins in the lowest order stage has a rate information holding function of holding rate information representative of a rate of cells inputted thereto.

Abstract: The invention relates to a switching device (300) having a plurality of line interface cards (LICs) (310), a plurality of egress LICs (320), a cross-bar (330) and a management card (340). The switching device (300) routes fixed sized cells of data across the cross-bar (330). The cells comprise fragments of variable length data packets. Each ingress LIC (312, 314, 316) is associated with a respective schedule or timetable (362, 364, 366) governing the transmission of cells by the ingress LIC. Similarly, each egress LIC (322, 324, 326) is also associated with a respective schedule or timetable (382, 384, 386) governing the reception of cells by said egress LIC. The schedules are in the form of a table whose entries are the identities of transmission queues corresponding to a respective egress LIC identification number (for ingress LICs) and ingress LICs from which to receive (egress LICs). Each ingress and egress LIC maintains a pointer into its associated schedule.

Abstract: Data switching systems for use in ATM and other packet and cell switching networks can more smoothly switch data if incoming data packets to be switched are re-ordered to avoid overwhelming an output port with too many consecutive packets to a particular destination. An apparatus and method for simply re-ordering data samples in a non-consecutive manner is computationally efficient and effective.

Abstract: A perch channel transmission and cell selection method for a CDMA mobile communication system which is capable increasing a system capacity by reducing an amount of interference power. In this method, each base station intermittently transmits a perch channel which is spread by using a spread code assigned to each base station. Then, a mobile station receives more than one perch channels transmitted from more than one base stations, measures a receiving level of an intermittently transmitted portion of each received perch channel, and judges a located cell according to measured receiving levels of these more than one perch channels.

Abstract: A self-routing switch such as a Banyan switch has a controller which recognizes incoming routing requests which would give rise to blocking in the switch and makes and optimum selection of queued requests which can be handled without blocking. The controller is implemented by means of an optical neural network having a light source array to illuminate a photodetector array through a mask, there being a light source array element and a photodetector element for each possible path through the switch. The assignment of paths to array locations is such that, for the path corresponding to any light source array element, the photodetector array element positions corresponding to the paths blocked thereby form a pattern which is a shifted version of the pattern formed by the photodetector array elements corresponding to the paths blocked by a path corresponding to any other light source array element, whereby a single mask may be employed.

Abstract: The device and method for multiplexing cells inputted to an asynchronous transmission mode using an input buffer according to the amount of traffic. The cell multiplexing device of an asynchronous transmission mode, includes: a buffer portion which include cell buffers corresponding to input ports, for storing cells received through the input ports; counters which have the number corresponding to that of the buffers, for storing the number of cells to be stored in the buffers a unit clock unit for determining for the counters a count unit of cells to be stored in the buffers; selector for outputting control signals to select buffers having their maximum values by comparing the values of the counters with each other; and a unit for inputting the output of the buffer unit and multiplexing the input cells according to the control signal, wherein the generation of buffer overflow is prevented by primarily processing the cells from a buffer where the most cells are stored.

Abstract: A switch guaranteeing a minimum amount of memory space for desired connection while allowing efficient dynamic change of maximum memory space that can be used by a connection. Only an amount of memory space which is required for guaranteeing the minimum amount of memory space is reserved. When the reserved space is decremented due to new cells being received on connections, the maximum memory space reserved for each connection is dynamically increased. For multicast connections, only a single copy of the cell data is stored even though a multicast cell is transmitted on several ports. Multicast cells can also be processed using the same signals used for processing unicast cells.

Abstract: A packet switch device having a plurality of input buffers; a packet switch; a plurality of schedulers, having a pipeline scheduling process module wherein a plurality of time units corresponding to the number of output lines is spent in scheduled sending process of the fixed length packets from the input buffer, and wherein the scheduled sending process is executed in a number of processes, in parallel, the number of processes corresponding to the number of the input lines, having a sending status management module wherein sending status of the fixed length packets which constitute one frame is managed for each of the input lines, and provided corresponding to any of the output lines; and at least one result notification module for notifying the input buffer of result information from the scheduled sending process performed by each of the plurality of schedulers.

Abstract: An apparatus for and a method of collapsing multiple ports to a single queue. The invention has applications in switching devices whereby several external ports share the same resource, such as a switching fabric. In order to allocate the resources fairly to all the ports, a scanning method is used to allocate the division of the resources to each of the external ports. A port combiner circuit continuously scans or polls the external ports in a round robin fashion checking for a port ready to input data. An external port in a ready state transfers its frame data to an input queue. The frame data is written to the next available segment in the input queue which is comprised of RAM configured as a circular buffer. After a frame is written, the write pointer is incremented to point to point to the next available segment. The next frame segment read out of the input queue is always the first one written. The queue thus formed received multiple inputs but has a single output.

Abstract: A simple high speed Real-Time method and apparatus for processing a queue in a network queue server is presented. Long packets at the beginning of the queue are processed while a pointer chains down the queue to find shorter packets. When a shorter packet is found the pointer stops and waits for a timing threshold to be met. When the timing threshold is met the short packet is processed until completion and then work is resumed on the long packet. The method is implemented using a pointer to identify the position in the queue that is currently being processed, a pointer to search for the shorter packets, two registers to hold values of the respective pointers and memory to hold the location of the discontinued packet. An additional register is utilized to hold the incremented cycle processing time, and a final register is used to hold a threshold value for processing a packet. Lastly, a previous pseudo head register is also utilized when the queue is not doubly linked.

Abstract: There is provided a method for a flow control to a mobile communication network in which an ATM virtual channel established between a first base station having a radio zone in which a mobile station exists and a terminating ATM node to which a remote station with which the mobile station communicates is connected. The first step of the method is to queue, in an ATM node, incoming cells to be sent to a second base station having a radio zone when the mobile station is handed over to the radio zone of the second base station. The second step of the method is to stop queuing and send the incoming cells queued in the ATM node to the second base station after the mobile station is handed over.

Abstract: A plurality of cell switches that operate at a basic switching rate are provided, and a unit including (FIFO buffers) for queuing cells from the transmission line are provided in correspondence with respective ones of the cell switches. Cells from the transmission line are demultiplexed and written to the prescribed FIFO buffer by a cell demultiplexer, cells are read out of each FIFO buffer at the basic switching rate and entered into the corresponding cell switch, and cells switched by each of the cell switches are multiplexed and sent to a transmission line by a multiplexer.

Abstract: A real-time data acquisition system for a remote, unmanned underwater vehe includes an array of sensors within the vehicle which gather data from the environment surrounding the vehicle. The sensor data is digitized and stored in an imbedded computer on the unmanned vehicle. To display the data, the imbedded computer transfers the digital data over a local area network connection to a second computer aboard a mother ship. The second computer converts the digital data back to analog data for display. The data can also be analyzed and processed depending on test requirements. To test the unmanned vehicle performance, the vehicle can be operated adjacent the mother ship with the local area network connection in place. In this mode, the imbedded computer transfers the digital data to the second computer as the data is being stored in the imbedded computer.

Abstract: An arrangement for lookahead interflowing traffic among a plurality of serving sites of one customer. Incoming calls received at a site are queued if they cannot be served immediately. Queued calls are then examined periodically and if the call has not yet been served by a local agent and if the call is one of the oldest call in the queue, then the call is a candidate for lookahead interflow. A candidate for lookahead interflow causes a message to be sent to another switch requesting that the call be interflowed. If the other switch accepts the call, the call is routed to that other switch; if the other switch does not accept the interflowed call then the call remains in the queue of the requesting switch and is reexamined at the next period. All calls in the queue are completed to a local agent if a local agent is available.

Abstract: A method of controlling the supply of cells into an asynchronous network, comprises the steps of storing incoming bytes from multiple channels in respective channel buffers, creating in memory a timing event wheel partitioned into a plurality of sectors, of which one is active at any time, and placing cell pointers in the sectors. The cell pointers identify channel buffers and are distributed around the wheel in accordance with a desired transmission schedule. The wheel is stepwise advanced at a predetermined rate, and the cell pointers in the active sector are scanned at each advance of the wheel to identify the corresponding channel buffers. The bytes from the identified channel buffers are assembled into cells, which are forwarded for transmission over the asynchronous network. These are then multiplexed with VBR cells from another source.

Abstract: A plurality of modules, each connected to communication lines, are interconnected by a logically separated interprocessor communication bus for transferring header information and control information and a frame transfer bus for transferring data. When each module receives data from a line, the module generates a header containing header information from the received data, stores the header and user data in respective queue-type data storage sections, and transmits the header on the interprocessor communication bus; when one of the other modules detects its own identification from the header on the bus, the module sends a data send request to the transmitting module which in response reads the data from the data storage and outputs it on the frame transfer bus for transmission to the requesting module.

Abstract: The device and method for multiplexing cells inputted to an asynchronous transmission mode using an input buffer according to the amount of traffic. The cell multiplexing device of an asynchronous transmission mode, includes: a buffer portion which include cell buffers corresponding to input ports, for storing cells received through the input ports; counters which have the number corresponding to that of the buffers, for storing the number of cells to be stored in the buffers; a unit clock unit for determining for the counters a count unit of cells to be stored in the buffers; a selector for outputting control signals to select buffers having their maximum values by comparing the values of the counters with each other, and a unit for inputting the output of the buffer unit and multiplexing the input cells according to the control signal, wherein the generation of buffer overflow is prevented by primarily processing the cells from a buffer where the most cells are stored.

Abstract: A method and system for optimizing data link occupation in a multipriority data traffic environment by using data multiplexing techniques over fixed or variable length data packets being asynchronously transmitted. The packets are split into segments including both a segment number and a packet number. The segments are dispatched, on a priority basis, over available links or virtual channels based on a global link availability control word indications, which control word is dynamically adjusted according to specific predefined conditions.

Abstract: It is disclosed hereby that a switch system comprises a N:M switch circuit, a plurality of layer 2 switches, each comprising a plurality of packet processing channels, and a plurality of network interfaces, each comprising a fixed number of pairs of ports to be directly connected to the same number of devices. The N:M switch is coupled with the N number of the packet processing channels of the layer 2 switches at the N-side and with the M number of the ports of the network interfaces at the M-side. When a packet containing a destination to a receiving device sent by a sending device arrives at the network interface, the N:M switch establishes an electronic connection between an available packet processing channel and a port to which the sending device is connected, the packet passes through to the packet processing channel in which the packet is processed and stored.

Abstract: A method of operating an input-queued multicast switch includes the step of loading input cells into a set of input queues. Each of the input cells specifies one or more output cells. Selected output cells are accepted from head-of-line input cells of the set of input queues in a manner to concentrate unaccepted output cell residue among a subset of the set of input queues. This concentration operation can be performed in a number of ways. One technique is to assign weights to the head-of-line cells on the basis of cell age and cell fanout. Another technique to achieve concentration is to iteratively match unaccepted output cell residue to an input queue with the most output cells in common with the unaccepted output cell residue.

Abstract: A cache apparatus and method for improving the connection capacity of an Asynchronous Transfer Mode (ATM) switch. The cache updates the ATM switch with information for configuring connections while maintaining a separate connection table. Incoming data cells are examined by a cell router and routed either directly to the switch, if a connection is already configured, or to a cell holding area while the connection is being set up in the switch. Unused or underused connections are detected in the connection table by a reclaim ager and marked underused. An updater then reviews the connection table to use the connection resources represented by the underused connections for configuring connections for the data cell stored in the cell holding area.

Abstract: A method for scheduling a connection through a node is disclosed. A resource request message is received from a master. An identity of a trunk where the resource request message is to be issued is determined. It is determined whether the node is issuing a predetermined number of resource request messages previously received. The resource request message is issued if the node is issuing less than the predetermined number of resource request messages previously received on the trunk. A busy message is sent to the master if the node has the predetermined number of resource request messages outstanding on the trunk.

Abstract: A multiplexer for use in conjunction with a cell-based network, which includes a plurality of access terminals each of which receives respective cells, each of the cells having one of a plurality of different classifications, a plurality of FIFO buffers each of which is coupled to a respective one of the access terminals for queuing the cells received at the respective access terminals, a plurality of decoding elements each of which is coupled to a respective one of the FIFO buffers, and, an allocation circuit which generates a coded selection signal that is applied to each of the decoding elements, wherein the decoding elements each decode the coded selection signal for selectively reading the cells out of the FIFO buffers in a manner whereby the cells are read out of the FIFO buffers in an order which is dependent upon their classification.

Abstract: A network-to-CPU interface circuit interfaces an isochronous physical layer to an ISA bus such that a host CPU connected to the ISA bus can communicate with the isochronous physical layer. Inbound B-channel interface circuity is connectable to receive, from the isochronous physical layer, an inbound data stream which includes a plurality of B-channels time division multiplexed into time division multiplexed (TDM) frames. The TDM frames have a predetermined format that defines at least one logical stream such that each logical stream comprises those B-channels that are time division multiplexed into corresponding predetermined locations within the TDM frames. An inbound buffer portion of a memory is provided to hold the received inbound data stream, and an outbound buffer portion of the memory is provided for holding an outbound data stream which, like the inbound data stream, includes a plurality of B-channels time division multiplexed into time division multiplexed (TDM) frames.

Abstract: A method of fairly and efficiently scheduling transmission of a packet from a plurality of sessions onto a network is presented. The method includes providing an input having a plurality of sessions, grouping the sessions into a plurality of classes, scheduling the classes with first level schedulers associated with one of the classes, scheduling the outputs of some of the first level schedulers with a second level scheduler, and prioritizing among the output of the remaining first level scheduler(s) and the output of the second level scheduler to provide an hierarchical scheduler output. The scheduler accepts traffic types at its input, and provides an output suitable for scheduling cell based traffic such as Asynchronous Transfer Mode (ATM) network traffic.

Abstract: In an ATM switch, the total required buffer storage is concentrated in a central memory which is used by all input and output channels. The connection between the input and output channels and the memory is established by a synchronous bus. The time allocation on the bus is designed in such a manner that within the transmitting time of a data cell according to the ATM norm, e.g., over a wide band network, a time slice which is sufficient for the transfer of a complete data cell between an input or an output and the memory is allocated to each input and output. The memory is fixedly divided into areas of the same size, each of the areas serving as a buffer for a respective input. Due to the simple time allocation of the bus it is possible to combine a plurality of input and output channels in an input/output unit and to still realize the latter in a small number of integrated circuits. For the memory, unexpensive standard memory devices can be used.

Abstract: A distributor with controlled switching elements (CSE) which simplifies hardware construction by distributing the function of a running adder into a reverse banyan network. The distributor comprises a CSE-based network using switching stages, each switching stage having control switching elements. A control signal input stage switches two packet input signal switching channels, each stage receiving each control signal from an output stage having switching elements. An active packet counter counts and generates an output signal which represents the number of active packets inputted to the CSE network. A tail-of-queue register is used for storing output vectors.