Contention Resolution For Output Patents (Class 370/416)
  • Patent number: 7917656
    Abstract: A messaging service is described that incorporates messages into cached link lists. The messages are not yet acknowledged as having been received by one or more consumers to whom the messages were sent. A separate link list exists for each of a plurality of different message priority levels. Messages within a same link list are ordered in their link list in the same order in which they where received by the messaging service. At least one of the link lists contains an element that represents one or more messages that are persisted but are not cached in any of the cached link lists.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: March 29, 2011
    Assignee: SAP AG
    Inventors: Radoslav I. Nikolov, Desislav V. Bantchovski, Stoyan M. Vellev
  • Patent number: 7869452
    Abstract: A FIFO communication system is provided using a FIFO and connection circuit to transmit data from a single source to multiple sinks. The connection circuit operates to enable simultaneous reads by the multiple sinks with a single output port FIFO. Multiple FIFOs can likewise be used to distribute data from a single source to multiple sinks without requiring a simultaneous read by both sinks. Similarly, a multiple output port FIFO can be used to supply multiple sinks without requiring simultaneous reads and without requiring additional memory use.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: January 11, 2011
    Assignee: Xilinx, Inc.
    Inventor: Stephen A. Neuendorffer
  • Patent number: 7813360
    Abstract: Embodiments of the present invention are directed to controlling device access fairness in frame-based switches by automatically and continuously counting the number of actively communicating devices connected to each port and the type of devices connected to each port, and adjusting fairness accordingly. During a sampling window, the number of active devices and the type of devices connected to each port is determined. At the start of each fairness window, a weighted number of slots are assigned to each port based on the number of active devices connected to each port and the type of devices connected to that port. Within a single fairness window, each port is able to provide device accesses to the frame-based switch in accordance with the number of slots assigned to that port.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: October 12, 2010
    Assignee: Emulex Design & Manufacturing Corporation
    Inventors: Bruce Gregory Warren, Carl Joseph Mies, Thomas Phillip Ambrose, Terrence R. Doherty
  • Patent number: 7813414
    Abstract: A transceiver apparatus and a method comprise detecting means for detecting messages, wherein the detecting means comprises a first detector arranged to operate over a first detection period and which output indicates the beginning of a message with a first detection probability, and a second detector arranged to operate over a second detection period and which output indicates the detection of the beginning of a message with a second detection probability. The second detection probability is higher than the first detection probability and the transceiver apparatus is arranged to receive the message if the second detector indicates detection of the beginning of a message.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: October 12, 2010
    Assignee: Infineon Technologies AG
    Inventor: Michael Lewis
  • Publication number: 20100232449
    Abstract: A system and method of switching data using a switch device that includes a plurality of input ports, a plurality of switch units, and a plurality of output ports. Each input port storing data to be sent may generate a request to output data to each of the output ports to which stored data is to be sent, wherein each request identifies a specific one of the plurality of switch units to be used to transfer the data from the corresponding input port to the corresponding output port. Grants may be generated per output port per switch unit. Grants may be accepted per input port per switch unit. Data may be outputted from the respective input ports to the respective output ports, based on the accepted grants, utilizing the switch units identified in the requests corresponding to the accepted grants.
    Type: Application
    Filed: May 20, 2010
    Publication date: September 16, 2010
    Inventor: Jacob V. Nielsen
  • Patent number: 7787446
    Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Francois Le Maut, Rene Glaise, Michel Poret, Rene Gallezot
  • Patent number: 7751319
    Abstract: In a method for classifying data packet units, each comprising a group of data packet parameters which comprises a plurality of data packet parameters, a subgroup of data packet parameters for configuring a classification key is selected, the data packet units are divided into data packet classes on the basis of the classification key and a selected classification algorithm, and the data packet units are allocated to further data packet parameters which correspond to the respective data packet class.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: July 6, 2010
    Assignee: Infineon Technologies AG
    Inventors: Matthias Heink, Raimar Thudt, Charles Bry, Taro Kamiko, Franz-Josef Schafer
  • Patent number: 7738474
    Abstract: A method for transferring data includes connecting N ports of a crossbar to N devices, respectively, where N is an integer greater than one. Inbound data is received at one of the N ports from a respective one of the N devices. N?1 output buffers are associated with others of the N ports, respectively. At least one of the N?1 output buffers is selected to output outbound data corresponding to the inbound data. The inbound data from the input buffer of one of the N ports is selectively transferred to at least one of the N?1 output buffers of the others of the N ports.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: June 15, 2010
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventors: Eitan Medina, David Shemla
  • Patent number: 7733895
    Abstract: A graph based on a data traffic matrix represents the occupancy of a set of virtual output queues to an optical crosspoint packet data switch. Edges in the graph are assigned to a matching in order of decreasing weight, provided that the edges do not conflict with other edges previously placed in the matching. If a conflict is found for a particular edge, a new matching is created and the conflicting edge is placed in the new matching. The process iterates until all edges are covered, resulting in creating a collection of matchings. The collection of matchings is transformed into a schedule such that each matching defines a switch configuration and the weight of the heaviest edge determines its holding time. The length of the obtained schedule equals the total cost of the collection. The cost of the collection is the total weight of the matchings plus the product of the re-configuration delay and the number of matchings.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: June 8, 2010
    Assignee: Cisco Technology, Inc.
    Inventors: Alex Kesselman, Kirill Kogan
  • Patent number: 7724760
    Abstract: A method for selecting a queue for service across a shared link. The method includes classifying each queue from a group of queues within a plurality of ingresses into one tier of a number “N” of tiers. The number “N” is greater than or equal to 2. Information about allocated bandwidth is used to classify at least some of the queues into the tiers. Each tier is assigned a different priority. The method also includes matching queues to available egresses by matching queues classified within tiers with higher priorities before matching queues classified within tiers with lower priorities.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: May 25, 2010
    Assignee: Broadcom Corporation
    Inventors: Hari Balakrishnan, Srinivas Devadas, Arvind Mithal
  • Patent number: 7720092
    Abstract: A hierarchical round robin arbiter includes a first set of arbitration vectors, each associated with a plurality of requesters. A second arbitration vector includes one bit for each arbitration vector in the first set. The single bit informs the round robin arbiter if any of the requesters associated with the corresponding arbitration vector in the first set are requesting service. The round robin arbiter can determine whether one of a number of requesters is requesting service by examining the single bit in the arbitration vector.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: May 18, 2010
    Assignee: Juniper Networks, Inc.
    Inventors: Pradeep Sindhu, Debashis Basu, Edwin Su
  • Patent number: 7688839
    Abstract: A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: March 30, 2010
    Inventors: Donald R. Primrose, I. Claude Denton
  • Patent number: 7646782
    Abstract: A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: January 12, 2010
    Inventors: Donald R. Primrose, I. Claude Denton
  • Patent number: 7609653
    Abstract: Systems and methods for resolving a partial topology are disclosed. In one embodiment a media engine includes a topology loader module that receives a partial topology from another module associated with the media engine. The topology loader implements logic operations that convert a partial topology into a full topology, which may be returned to the media engine for presentation of the media stream(s) to a user.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: October 27, 2009
    Assignee: Microsoft Corporation
    Inventors: Samuel Amin, Brian D. Crites, Kirt A. Debique, Sohail Baig Mohammed, Niranjan S. Nayak, Eric H. Rudolph, Mei L. Wilson
  • Patent number: 7602797
    Abstract: In accordance with at least one embodiment of the present invention, a method and apparatus for scheduling traffic in a communications node is provided. Line cards request communication opportunities from a switch fabric. The switch fabric issues grants for such communication opportunities in response to specific requests. By dynamically adjusting usage of such communication opportunities corresponding to such grants among requests of differing priorities and/or latency criteria, embodiments of the present invention are able to provide increased capacity utilization of switching fabric bandwidth while maximizing adherence to priority requirements and/or latency criteria.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: October 13, 2009
    Assignee: Alcatel Lucent
    Inventor: Robert Elliott Robotham
  • Patent number: 7602798
    Abstract: Techniques for accelerating network receive side processing of packets. Packets may be associated into flow groupings and stored in flow buffers. Packet headers that are available for TCP/IP processing may be provided for processing. If a payload associated with a header is not available for processing then a descriptor associated with the header is tagged as indicating the payload is not available for processing.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: October 13, 2009
    Assignee: Intel Corporation
    Inventors: John Ronciak, Christopher Leech, Prafulla Deuskar, Jesse Brandeburg, Patrick Connor
  • Patent number: 7567556
    Abstract: A circulating switch comprises switch modules of moderate capacities interconnected by a passive rotator. Data is sent from a one switch module to another switch module either directly, traversing the rotator once, or indirectly through at least one intermediate switch module where the rotator is traversed twice. A higher capacity extended circulating switch is constructed from higher-capacity switch modules, implemented as common memory switches and having multiple ports, interconnected through a multiplicity of rotators preferably arranged in complementary groups of rotators of opposite rotation directions. A polyphase circulating switch having a low switching delay is derived from a multi-rotator circulating switch by providing programmable rotators having adjustable relative rotator-cycle phases. A low delay high-capacity switch may also be constructed from prior-art medium-capacity rotator space switches with mutually phase-shifted rotation cycles.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: July 28, 2009
    Assignee: Nortel Networks Limited
    Inventor: Maged E. Beshai
  • Patent number: 7561590
    Abstract: A network switching device for transferring data among n channels includes n receive circuits and n ingress modules. The receive circuits receive frames from n channels. The ingress modules include a memory circuit that stores each frame in buffers. The buffers store bytes of data. A destination resolution circuit selects a destination channel for each of the frames. A forwarding module enqueues each buffer to the respective destination channel. Egress modules transmit data in the buffers enqueued to the n channels. Each of the n counters stores a count for a respective n channel. The counters are incremented when a respective ingress module enqueues a buffer to a destination channel. The counters are decremented after the data stored in a buffer is transmitted to the n channels. The egress modules exercise flow control on a respective channel when a respective count is greater than a pause threshold.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: July 14, 2009
    Assignee: Marvell International Ltd.
    Inventor: Hugh Walsh
  • Patent number: 7545808
    Abstract: A network device switches variable length data units from a source to a destination in a network. An input port receives the variable length data unit and a divider divides the variable length data unit into uniform length data units for temporary storage in the network device. A distributed memory includes a plurality of physically separated memory banks addressable using a single virtual address space and an input switch streams the uniform length data units across the memory banks based on the virtual address space. The network device further includes an output switch for extracting the uniform length data units from the distributed memory by using addresses of the uniform length data units within the virtual address space. The output switch reassembles the uniform length data units to reconstruct the variable length data unit. An output port receives the variable length data unit and transfers the variable length data unit to the destination.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: June 9, 2009
    Assignee: Juniper Networks, Inc.
    Inventors: Pradeep S. Sindhu, Dennis C. Ferguson, Bjorn O. Liencres, Nalini Agarwal, Hann-Hwan Ju, Raymond Marcelino Manese Lim, Rasoul Mirzazadeh Oskouy, Sreeram Veeragandham
  • Patent number: 7535899
    Abstract: An apparatus and method includes grouping filters to form a tree according to a bitmask. The bitmask includes entries indicating whether a value is assigned to an element of a filter. The method also includes receiving a packet that includes a particular bitmask, searching the tree to determine filters associated with the particular bitmask and the associated values, and returning a set of filters that are an intersection of the filters indicated by the associated values.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Pankaj N. Parmar, David M. Durham
  • Patent number: 7525978
    Abstract: A system and method that can be deployed to schedule links in a switch fabric. The operation uses two functional elements: to perform updating of a priority link list; and then selecting a link using that list.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: April 28, 2009
    Assignee: Altera Corporation
    Inventors: Vahid Tabatabaee, Son Truong Ngo
  • Publication number: 20090086750
    Abstract: A system and method for using a doorbell command to allow sRIO devices to operate as bus masters to retrieve data packets stored in a serial buffer, without requiring the SRIO devices to specify the sizes of the data packets. The serial buffer includes a plurality of queues that store data packets. A doorbell frame request packet identifies the queue to be accessed within the serial buffer, but does not specify the size of the data packet(s) to be retrieved. Upon detecting a doorbell frame request packet, the serial buffer operates as a bus master to transfer the requested data packets out of the selected queue. The selected queue can be configured to operate in a flush mode or a non-flush mode. The serial buffer may also indicate that a received doorbell frame request has attempted to access an empty queue.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Applicant: Integrated Device Technology, Inc.
    Inventors: Chi-Lie Wang, Jason Z. Mo, Stanley Hronik, Jakob Saxtorph
  • Publication number: 20090059942
    Abstract: A system and method of scheduling packets or cells for a switch device that includes a plurality of input ports each having at least one input queue, a plurality of switch units, and a plurality of output ports. There is generated, by each input port having a packet or cell in its at least one queue, a request to output the corresponding packet or cell to each of the output ports to which a corresponding packet or cell is to be sent to, wherein the request includes a specific one of the plurality of switch units to be used in a transfer of the packet or cell from the corresponding input port to the corresponding output port. Access is granted, per output port per switch unit, to the request made on a first priority scheme. Grants are accepted per input port per switch unit, the accepting being based on a second priority scheme.
    Type: Application
    Filed: July 24, 2008
    Publication date: March 5, 2009
    Inventor: Jacob V. NIELSEN
  • Patent number: 7477650
    Abstract: A method and apparatus for frame-aware and pipelined hierarchical scheduling is described. In accordance with at least one embodiment of the invention, some or all schedulers of a communication node are associated with one or more storage devices that maintain values used by corresponding higher level schedulers to make scheduling decisions. Because of the nature of the scheduling decision flow and the potential to update registers in real-time, the scheduling arrangement can respond almost immediately to changes occurring at the input queues, which allows scheduling to be responsive to differing priorities of incoming cells. The nature of the scheduling decision flow also allows pipelined scheduling, in which scheduling of one or more additional cells can begin before scheduling of a first cell is completed.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: January 13, 2009
    Assignee: Alcatel Lucent
    Inventors: Robert Elliott Robotham, Jordan Lu
  • Patent number: 7477652
    Abstract: A crossbar for communicating with at least one device, the crossbar comprises N ports. Each one of the N ports comprises a link logic unit to receive messages and data from a respective device, N-1 output buffers each corresponding to another one of the N-1 ports and a port arbiter to select one of the N-1 output buffers to output data to the respective device. The stored data is transferred to the corresponding output buffer of a selected one of the other one of the N ports.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: January 13, 2009
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventors: Eitan Medina, David Shemla
  • Patent number: 7474668
    Abstract: A two stage rate shaping and scheduling system and method is implemented to control the flow of traffic to at least one output interface. The system and method involves initially queuing incoming packets into type-specific queues and applying individual rate shaping rules to each queue. A first stage arbitration is performed to determine how traffic is queued from the type-specific queues to interface-specific queues. Packets that win arbitration and pass the applied rate shaping rules are queued in interface-specific queues. Rate shaping rules are applied to the interface-specific queues. The interface-specific queues are further distinguished by priority and priority-specific and interface-specific rate shaping rules are applied to each queue. A second stage arbitration is performed to determine how different priority traffic that is targeting the same output interface is dequeued in response to interface-specific requests.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: January 6, 2009
    Assignee: Alcatel-Lucent USA Inc.
    Inventors: James Bauman, Eric Anderson, Gunes Aybay, Mike Morrison
  • Patent number: 7453810
    Abstract: A backpressure mechanism uses a TDM backpressure bus with each port card being assigned time slot. During its time slot, each ingress card/port writes on the bus the number of packets it transmitted to an egress ports during the last data refresh cycle. This information is read by the egress ports and used to compute current depth of the switch fabric output queues. In addition to information received from ingress cards, egress cards keep count of number of packets received from the appropriate switch fabric port and based on it estimate/calculate the current depth of the switch fabric output queue. Congestion states are calculated for all queues by comparing the queue depth with a respective threshold. Each egress card uses these congestion states to generate backpressure signals to ingress cards. Ingress card are using these signals to make decision whether to send or not traffic to destination egress card/port.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: November 18, 2008
    Assignee: Alcatel Lucent
    Inventors: Milan Zoranovic, Brian McBride, Peter Rabinovitch
  • Patent number: 7447152
    Abstract: An apparatus for controlling traffic congestion includes: a transmitting processor including a packet classifying unit adapted to classify packets to be processed in a receiving processor and packets to be forwarded via the transmitting processor, the transmitting processor and the receiving processor having different traffic processing speeds; a buffer adapted to store the packets to be forwarded from the packet classifying unit to the receiving processor; and the receiving processor including a token driver adapted to output the packets stored in the buffer in accordance with a token bucket algorithm in response to an interrupt signal of the transmitting processor and to transmit the packets to a corresponding application, and a monitoring unit adapted to analyze and monitor a resource occupancy rate and a traffic characteristic used by the token driver to set an amount of tokens.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: November 4, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Cheol Kim, Byung-Gu Choe, Yong-Seok Park
  • Patent number: 7424026
    Abstract: Disclosed is a device, a computer program and a method to receive and buffer data packets that contain information that is representative of time-ordered content, such as a voice signal, that is intended to be presented to a person in a substantially continuous and substantially uniform temporal sequence; to decode the information to obtain samples and to buffer the samples prior to generating a playout signal. The samples are time scaled as a function of packet network conditions to enable changing the play-out rate to provide a substantially continuous output signal when the data packets are received at a rate that differs from a rate at which the data packets are created. The time scaling operation operates with a base delay that is controlled in a positive sense when the data packets are received at a rate that is slower than a rate at which the data packets are created, and a reserve delay that is managed to provide insurance against an interruption should the base delay become negative.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: September 9, 2008
    Assignee: Nokia Corporation
    Inventor: Jani Mallila
  • Patent number: 7391766
    Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: June 24, 2008
    Assignee: International Business Machines Corporation
    Inventors: Francois Le Maut, Rene Glaise, Michel Poret, Rene Gallezot
  • Publication number: 20080037574
    Abstract: A method of securing an invited Push-To (PT) user's privacy in an automatic answer mode of a PT service is discussed. According to an embodiment of the present invention, a method for performing a PT (Push-To) service setting procedure, includes transmitting PT service setting information of a PT client to a PT server during a PT service setting procedure, the PT service setting information including answer mode setting information and privacy information, the answer mode setting information indicating if an answer mode of the PT client is an automatic answer mode or a manual answer mode, the privacy information indicating whether or not an identity of the PT client is to be kept private in the answer mode; and storing the PT service setting information of the PT client in the PT server, whereby the PT server can selectively inform identification information of the PT client to another PT client based on the privacy information.
    Type: Application
    Filed: June 6, 2007
    Publication date: February 14, 2008
    Applicant: LG Electronics Inc.
    Inventors: Kang-Suk Huh, Sung Bum Choi
  • Patent number: 7330900
    Abstract: Packets of real-time media streams are processed at a network node such within a desired maximum latency less than the frame interval of the streams. The media streams have respective packet rates all substantially equal to a nominal packet rate and respective packet arrival times that are generally non-deterministic. The streams are assigned to digital signal processors (DSPs), each capable of processing up to a predetermined maximum number of the streams within real-time constraints. The number of streams assigned to each DSP is less than the predetermined maximum number and no greater than the quotient of a desired maximum processing latency less than the frame interval and the DSP processing latency for a single packet. For example, if the desired maximum processing latency is 5 ms. and the processing latency for one packet is 1.6 ms., then only three streams are assigned to a DSP (5/1.6˜3), even if the DSP can process many more than 3 streams in real time.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: February 12, 2008
    Assignee: Dialogic Corporation
    Inventors: Eric Burger, Joel Hughes, David Penny
  • Patent number: 7321595
    Abstract: A method for processing various numbers of ports in a network processor. A method for processing various numbers of ports in a network processor comprises the steps of: a) receiving the number N of ports from a system controller; b) allocating N?1 number of registers for storing N?1 number of port management information in response to the number N of ports; c) processing a packet by sequentially accessing the N number of ports; and d) after processing a packet related to a predetermined port, storing management information related to the predetermined port in a register used for the next port, and storing the management information related to the predetermined port in a first register among the N?1 number of registers when a register for storing management information in a previous packet processing is the last (N?1)-th register among the N?1 number of registers.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: January 22, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su-Hyun Kim, Young-Seok Kim, Young-Il Kim, Jong-Sang Oh
  • Patent number: 7319670
    Abstract: An apparatus for transmitting to a network comprises a queue, packetization logic, interface logic, and queue logic. The packetization logic is configured to packetize data into a plurality of data packets and to store, to the queue, entries pointing to the data packets. The interface logic is configured to read the entries from the queue. The interface logic, for each of the read entries, is configured to retrieve one of the packets pointed to by the read entry and to transmit the retrieved packet to a network socket. The queue logic is configured to limit, based on a number of retransmission requests detected by the queue logic, a number of entries that the packetization logic may store to the queue during a particular time period thereby controlling a transmission rate of the apparatus.
    Type: Grant
    Filed: February 8, 2003
    Date of Patent: January 15, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeffrey Joel Walls, Michael T Hamilton
  • Patent number: 7313147
    Abstract: A network device for transmitting data of a host system to a network including a buffer for storing the data, a first transmission interface providing a control signal to the host system, and a second transmission interface coupled to the buffer for transmitting the data from the buffer to the network. A data transmission method of the network device includes the following steps: providing a network device and a host system, wherein the network device is providing a control signal to the host system, and the network device immediately activates a frame transmission procedure after providing the control signal; the host system starting to transmit data to the network device after the host system receives the control signal; and the network device transmitting the data to the network after a frame transmission pre-procedure is finished and when the data of the host system are completely transmitted to the network device.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: December 25, 2007
    Assignee: Infineon-ADMtek Co., Ltd.
    Inventor: Sheng-Yuan Cheng
  • Patent number: 7298703
    Abstract: Disclosed is a circuit and method for reducing control code transmission between a line card and a switching fabric. One embodiment includes a memory receiving (and storing) data transmitted at a second rate during a first period of time. A quantity of data in the memory at time t, q(t), is compared with first, second, third, and fourth quantity values. The memory may receive data transmitted at the first rate if q(t) is less than the second, third and fourth values but greater than the first value. The memory may receive data transmitted at the third rate if q(t) is greater than the first, second, and third values but less than the fourth value. The memory may receive data transmitted at the second rate if q(t) is greater than the first and second values but less than the third and fourth values.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: November 20, 2007
    Assignee: Cisco Technology, Inc.
    Inventor: Kenneth M. Rose
  • Publication number: 20070258477
    Abstract: A PT (Push-To) service among SIP based session services, and particularly, a method and terminal for establishing a PT session in order to allow a certain user to use a PT box service under control of a PT server in a SIP (Session Initiation Protocol) based service, are discussed. According to an embodiment, the method of providing a Push-To (PT) box service, includes storing, in a PT server, PT box setting information of a terminal; receiving, by the PT server, a session invitation directed to the terminal; and determining, by the PT server, a routing of the session invitation to a PT box for the terminal based on at least the PT box setting information.
    Type: Application
    Filed: April 30, 2007
    Publication date: November 8, 2007
    Inventor: Kang-Suk Huh
  • Patent number: 7292594
    Abstract: A switching fabric connects input ports to output ports. Each input has an input pointer referencing an output port, and each output has an output pointer referencing an input port. An arbiter includes input and output credit allocators, and an arbitration module (matcher). The input credit allocator resets input credits associated with input/output pairs and updates the input pointers. Similarly, the output credit allocator resets output credits associated with input/output pairs and updates the output pointers. The matcher matches inputs to outputs based on pending requests and available input and output credits. A scheduler schedules transmissions through the cross-bar switch according to the arbiter's matches.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: November 6, 2007
    Assignee: LSI Corporation
    Inventors: Gopalakrishnan Meempat, Gopalakrishnan Ramamurthy, William J. Dally
  • Patent number: 7277388
    Abstract: A method is disclosed for a router to provide random assignments of three priorities, each signifying a drop precedence, to packets on a per customer basis. The router determines a sending rate estimate. Then the router marks a packet a priority level based on the sending rate estimate.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: October 2, 2007
    Assignee: Nokia Corporation
    Inventor: Rajeev Koodli
  • Patent number: 7272150
    Abstract: A system for shaping traffic from a plurality of data streams comprised of a first queuing stage configured to shape traffic from the data streams and having a plurality of shaping queues; and a second queuing stage coupled to the first queuing stage and configured to manage congestion from the first queuing stage that occurs when multiple of the shaping queues become eligible to send traffic at substantially the same time.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: September 18, 2007
    Assignee: World Wide Packets, Inc.
    Inventors: Keith Michael Bly, C Stuart Johnson
  • Patent number: 7260063
    Abstract: A switch of a network, which services a contract, for switching frame relay frames having a variable size. The switch includes ports through which frames are received from and sent to the network. The switch includes a memory in which data of the frames is stored, the memory in communication with the ports. The switch includes a processor which sends traffic contract conforming frames within a first time interval having a bandwidth to the network and adds unusable bandwidth from the first time interval to a second time interval in which the processor sends data to the network. A method for switching frame relay frames having a variable size in a network, which services a contract.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: August 21, 2007
    Assignee: Ericsson AB
    Inventors: Lei Feng, Siva Kandasamy
  • Patent number: 7260104
    Abstract: A method and apparatus for temporarily deferring transmission of packets/frames to a destination port in a buffered switch is disclosed. When a request for transmission of at least one packet/frame to the destination port is received, it is determined whether the destination port is available to receive the at least one packet/frame. The transmission of the at least one packet/frame is deferred when the destination port is not available to receive the at least one packet/frame. The packet/frame identifier and memory location for each deferred packet/frame is stored in a deferred queue and the process then repeats for the next packet/frame. Periodically, the apparatus attempts to transmit the packets/frames in the deferred queue to their respective destination ports.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: August 21, 2007
    Assignee: Computer Network Technology Corporation
    Inventor: Steven G. Schmidt
  • Patent number: 7249228
    Abstract: Mechanisms for reducing the number of block masks required for programming multiple access control lists in an associative memory are disclosed. A combined ordering of masks corresponding to multiple access control lists (ACLs) is typically identified, with the multiple ACLs including n ACLs. An n-dimensional array is generated, wherein each axis of the n-dimensional array corresponds to masks in their requisite order of a different one of the multiple ACLs. The n-dimensional array progressively identifies numbers of different masks required for subset orderings of masks required for subsets of the multiple ACLs. The n-dimensional array is traversed to identify a sequence of masks corresponding to a single ordering of masks including masks required for each of the multiple ACLs.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: July 24, 2007
    Assignee: Cisco Technology, Inc.
    Inventors: Amit Agarwal, Venkateshwar Rao Pullela, Qizhong Chen
  • Patent number: 7221647
    Abstract: Disclosed is a packet communication apparatus of large capacity capable of realizing high throughput and packet priority control in packet switching for changing connection of input and output ports of a switch on a variable-length packet unit basis. A variable-length packet is divided into a group of cells in an ingress interface, and the cells are stored in VOQs divided in correspondence with destination output ports of a switch. For each of the VOQs, a corresponding first-cell storing register is provided. When a packet arrives at the head of the VOQ, the first cell indicating an output path of the packet is transferred to a first-cell storing register. Each ingress interface selects one of first cells of packets which can be output and transmits the selected one to the switch. The switch performs a scheduling process so as to select one first cell per output port.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: May 22, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Norihiko Moriwaki, Hirofumi Masukawa
  • Patent number: 7203171
    Abstract: Disclosed herein is a packet switching device coupled to receive inbound packets from a network, switch the packets through a switching fabric, and provide outbound packets to a network. Multiple different packet switching devices use such switching fabric to exchange inbound packets. The packet switching device includes an output traffic manager that selectively stores outbound packets from the switching fabric in queues until the packets can be transmitted to the network. When any queue is unable to store more outbound packets, the output traffic manager communicates to the input traffic manager to drop inbound packets destined for that queue, instead of transferring them to the switching fabric and ultimately dropping the packets as outbound packets. Thereby traffic through the switching fabric is reduced.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: April 10, 2007
    Assignee: Cisco Technology, Inc.
    Inventor: Ian M. Wright
  • Patent number: 7203202
    Abstract: An exhaustive service dual round-robin matching (EDRRM) arbitration process amortizes the cost of a match over multiple time slots. It achieves high throughput under nonuniform traffic. Its delay performance is not sensitive to traffic burstiness, switch size and packet length. Since cells belonging to the same packet are transferred to the output continuously, packet delay performance is improved and packet reassembly is simplified.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: April 10, 2007
    Assignee: Polytechnic University
    Inventors: Hung-Hsiang Jonathan Chao, Yihan Li, Shivendra S. Panwar
  • Patent number: 7184444
    Abstract: The present invention provides method for data packet processing in a telecommunications system. The method of the present invention can include the steps of (i) determining a set of classification parameters for a data packet at an ingress edge unit, wherein the classification parameters include a packet destination, (ii) communicating the data packet to an egress edge unit and (iii) routing the data packet to a destination egress port at the egress edge unit according the classification parameters determined at the ingress edge unit. In one embodiment of the present invention, the classification parameters can include a destination egress edge unit, a destination egress port at the destination egress edge unit, and quality of service parameter for proper processing of the data packet.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: February 27, 2007
    Assignee: Yotta Networks, LLC
    Inventor: Nolan J. Posey, Jr.
  • Patent number: 7180862
    Abstract: A method of providing virtual output queue feedback to a number of boards coupled with a switch. A number of virtual queues in the switch and/or in the boards are monitored and, in response to one of these queues reaching a threshold occupancy, a feedback signal is provided to one of the boards, the signal directing that board to alter its rate of transmission to another one of the boards. Each board includes a number of virtual output queues, which may be allocated per port and which may be further allocated on a quality of service level basis.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventors: Brian E. Peebles, Gerald Lebizay, Neal C. Oliver
  • Patent number: 7170903
    Abstract: Arbitration for a switch fabric (e.g., an input-buffered switch fabric) is performed. For a first port, a link subset from a set of links associated with the first port is determined. Each link from the link subset is associated with its own candidate packet and is associated with its own weight value. A link from the link subset for the first port is selected based on the weight value associated with each link from the link subset for the first port. For a second port, a link subset from a set of links associated with the second port is determined. Each link from the link subset associated with the second port is associated with its own candidate packet and is associated with its own weight value. The determining for the second port is performed in parallel with the determining for the first port. A link from the link subset for the second port is selected based on the weight value associated with each link from the link subset of associated with the second port.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: January 30, 2007
    Assignee: Altera Corporation
    Inventors: Mehdi Alasti, Kamran Sayrafian-Pour, Vahid Tabatabaee
  • Patent number: 7168032
    Abstract: In one embodiment, an integrated circuit provides a test access port that communicates with scan chain registers in a processor core. The integrated circuit synchronizes data transferred between a debug controller that operates under control of a test clock (TCK) and the processor core that operates under control of a processor clock (CLK).
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: January 23, 2007
    Assignees: Intel Corporation, Analog Devices, Inc.
    Inventors: Charles P. Roth, Ravi P. Singh, Ravi Kolagotla, Tien Dinh