Input Or Output Circuit, Per Se (i.e., Line Interface) Patents (Class 370/419)
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Publication number: 20150063369Abstract: Methods and systems for operating a packet switch that communicates packets with error indication, including the steps of: receiving a packet comprising an error detection field; utilizing the error detection field to identify an error in the packet; marking the occurrence of the error in an error propagation field in the packet; updating the value of the error detection field; and forwarding the modified packet, with the updated value of the error detection field and the error propagation field, according to information carried in the packet.Type: ApplicationFiled: October 20, 2014Publication date: March 5, 2015Applicant: Valens Semiconductor Ltd.Inventors: Eyran Lida, Nadav Banet, Aviv Salamon
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Patent number: 8971208Abstract: The invention relates to a multichannel radio-frequency receiver for electromagnetic waves, having a radio-frequency analogue section, which has an input for an electrical signal from a reception device, and having a lower-frequency section, which is connected downstream of the radiofrequency analogue section and has a plurality of parallel channels (6b, 6c; 7b, 7c) for in each case different signal levels and an evaluation circuit, in which, in the radiofrequency analogue section in order to split the signal in accordance with a predeterminable division ratio into signal elements which can be supplied to radio-frequency analogue channels (6a, 7a), downstream from which the channels (6b, 6c; 7b, 7c) of the lower-frequency section are respectively connected, and the channels (6b, 6c; 7b, 7c) of the lower-frequency section each have an evaluation circuit for detection of the phase and amplitude of the respective signal element.Type: GrantFiled: May 8, 2014Date of Patent: March 3, 2015Assignee: Selex ES GmbHInventors: Frank Gekat, Dieter Ruhl
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Patent number: 8972588Abstract: A system, method and computer program product are disclosed for monitoring a telecommunications network that comprises a plurality of Mobility Management Entity (MME) nodes and a plurality of evolved UTRAN NodeB (eNodeB) nodes coupled by S1-MME interfaces. A Stream Control Transmission Protocol (SCTP) association identifier is assigned to an SCTP association between interconnected MME and eNodeB nodes. Specific S1-MME messages allow discovering the MME nodes and the eNodeB nodes with their network identifiers, identifying the connections between them and populating proper tables for this topology information.Type: GrantFiled: November 5, 2012Date of Patent: March 3, 2015Assignee: Tektronix, Inc.Inventors: Antonio Bovo, Xiaoju Chen
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Patent number: 8971326Abstract: The present invention provides methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS vile verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, the payload header suppress circuit examines the payload header suppression mask to identify one or more bits in the payload header for which an associated byte string is to be suppressed. Next, the associated byte string for each of the identified bits are suppressed to generate a suppressed packet payload header. Finally, a payload header suppression index is added to the suppressed packet payload header.Type: GrantFiled: November 4, 2010Date of Patent: March 3, 2015Assignee: Broadcom CorporationInventors: Shane P. Lansing, Heratch Avakian
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Patent number: 8964772Abstract: A multi-chip module (MCM) may include a substrate, and first and second physical-layer (PHY) chips mounted on the substrate. In some implementations, the first PHY chip includes a multiplexer and a PHY circuit. The multiplexer is configured to receive a multiplexed data stream from a media access control (MAC) device, to demultiplex the multiplexed data stream into first and second data streams, to output the first data stream to the PHY circuit, and to output the second data stream to the second PHY chip. In some implementations, the first PHY includes a router and a PHY circuit. The router is configured to receive a plurality of data packets from a MAC device, to route one or more of the data packets having a first address to the PHY circuit, and to route one or more of the data packets having a second address to the second PHY chip.Type: GrantFiled: October 9, 2012Date of Patent: February 24, 2015Assignee: Broadcom CorporationInventor: William Calvin Woodruff
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Patent number: 8964746Abstract: A method of transmitting an upstream communication packet from a distributed trunk (DT) switch is described. The method comprises receiving a packet from a device connected to a DT port of the DT switch; and transmitting the received packet via a non-DT port of the DT switch if the DT switch is the owner of the device and transmitting the received packet via a DT interconnect (DTI) port of the DT switch if the DT switch is not the owner of the device.Type: GrantFiled: February 15, 2008Date of Patent: February 24, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Shaun Wakumoto, Bruce E. Lavigne, Robert L. Faulk, Jr., Mark A. Tassinari, Mark Gooch
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Patent number: 8966202Abstract: In this wireless communication device, a storage unit stores writing identification information relating to permission and prohibition of writing. An acquisition unit acquires device identification information that uniquely specifies an arbitrary wireless communication device from the arbitrary wireless communication device. A determination unit determines permission or prohibition of writing to a recording medium on the basis of the device identification information acquired by the acquisition unit and the writing identification information stored in the storage unit when a communication protocol of a session layer that performs writing to and readout from the recording medium in sector units is selected. A recording medium control unit controls permission and prohibition of writing to the recording medium on the basis of a result determined by the determination unit.Type: GrantFiled: April 3, 2012Date of Patent: February 24, 2015Assignee: Olympus CorporationInventor: Keito Fukushima
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Patent number: 8958302Abstract: Some demonstrative embodiments include apparatuses, systems and/or methods of controlling data flow over a wireless communication link with credit allocation. For example, an apparatus may include controller to control a data flow of a stream of data from a first device to a second device over a wireless communication link, the stream of data including data to be delivered to a plurality of endpoints, wherein the controller is to provide to the first device a plurality of credit allocations corresponding to the plurality of endpoints, wherein the controller is to determine a particular credit allocation corresponding to a particular end point based at least on an estimated link delay of the wireless communication link, and an estimated delivery rate of delivering data from a buffer of the second device to the particular endpoint.Type: GrantFiled: December 4, 2012Date of Patent: February 17, 2015Assignee: Intel CorporationInventors: Oren Kedem, Bahareh Sadeghi, Michael Glik, Elad Levy, Ophir Edlis
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Patent number: 8958435Abstract: An information management method and an information processing device functioning as a node are provided to enable an effective use of information distributed to, and shared with, a plurality of nodes on a network and to enable maintenance of security against leakage of information by controlling information retention. This management method of information gathers information distributed to, and shared with, a plurality of the nodes on a network and holds the information in a state accessible from other nodes to a temporary information memory unit when generating restored information. The information management method is also characterized in setting a flag for showing a history of the information and immediately discarding the information in the case that the retention of restored information becomes improper from a view point of contents of the flag.Type: GrantFiled: October 5, 2007Date of Patent: February 17, 2015Assignee: Konica Minolta Holdings, Inc.Inventor: Satoshi Deishi
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Publication number: 20150043593Abstract: A networking device including a plurality of client ports arranged for communicating with a plurality of clients, a service port arranged for communicating with a machine arranged to communicate with the plurality of clients, and networking componentry arranged to communicate electromagnetic communications between the plurality of client ports and the service port.Type: ApplicationFiled: April 19, 2012Publication date: February 12, 2015Applicant: BOOBERA LAGOON TECHNOLOGY, LLCInventors: David Charles Ambler Snowdon, Charles Nicholas Alexander Thomas, Scott McDaid
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Patent number: 8953637Abstract: A networking device includes a media access controller, a first rate adaptation layer communicating with the media access controller, a first physical extension module communicating with the first rate adaptation layer, a second physical extension module communicating with the first physical extension module, a second rate adaptation layer communicating with the second physical extension module, and a physical layer device communicating with the second rate adaptation layer. The physical layer device communicates with the second rate adaptation layer using an extended 10 Gbps media independent interface (EXGMII). The EXGMII includes a plurality of signal interconnections, a first mapping of signals of a media independent interface (MII) to the signal interconnections, a second mapping of signals of a 1 Gbps MII (GMII) to the signal interconnections, and a third mapping of signals of a 10 Gbps MII (XGMII) to the signal interconnections.Type: GrantFiled: October 22, 2013Date of Patent: February 10, 2015Assignee: Marvell International Ltd.Inventor: William Lo
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Patent number: 8953473Abstract: A plurality of frame buffers of a communication device store input frames for respective flows, which are units of managing communication. A sequential scheduler and an adjustment scheduler cyclically visit the plurality of frame buffers to read a frame for external output from each frame buffer. The sequential scheduler reads one frame per a visit to each frame buffer at a speed lower than a communication speed of the communication device. The adjustment scheduler reads one or more frames per a visit to each frame buffer such that a restriction on read quantity defined by a reference value greater than the shortest frame size is imposed.Type: GrantFiled: March 7, 2012Date of Patent: February 10, 2015Assignee: Fujitsu Telecom Networks LimitedInventor: Kazukuni Ugai
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Patent number: 8953630Abstract: A circuit arrangement comprises an input circuit for reading in a serial data stream, which comprises a plurality of useful data bits, and for reading in a piece of information which indicates the start of the serial data stream. The circuit arrangement also comprises a data processing circuit for removing at least one useful data bit from the read-in, serial data stream. The data processing circuit is designed such that it removes the at least one useful data bit at a prescribed position after the start of the serial data stream. The circuit arrangement also comprises a first output circuit for outputting the read-in, serial data stream for the omission of the at least one removed useful data bit.Type: GrantFiled: July 7, 2010Date of Patent: February 10, 2015Assignee: Infineon Technologies AGInventor: Josef-Paul Schaffer
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Patent number: 8953584Abstract: In some embodiments, a non-transitory processor-readable medium includes code to cause a processor to receive, at a network management module, a request for data plane information associated with a set of access switches of a distributed switch. The non-transitory processor-readable medium includes code to cause the processor to send, in response to the request, an instruction to each access switch from the set of access switches such that a proxy module at each access switch accesses data plane information at at least one line card at that access switch. The non-transitory processor-readable medium includes code to cause the processor to receive, from each access switch from the set of access switches, the data plane information associated with that access switch, and then send a signal to output, on a single interface, the data plane information associated with each access switch from the set of access switches.Type: GrantFiled: June 5, 2012Date of Patent: February 10, 2015Assignee: Juniper Networks, Inc.Inventor: Hexin Wang
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Patent number: 8953629Abstract: A blade router for increased interface scalability is provided. The blade router may address interface scalability by having each of the linecards manage its interfaces locally and may use the concept of virtual and local interfaces for intelligent forwarding. The blade router may appear as a single router from the customer perspective during configuration. For some embodiments, two virtual interfaces may be used, one for regular interface traffic and another for Network Address Translation (NAT)-enabled interface traffic.Type: GrantFiled: February 26, 2008Date of Patent: February 10, 2015Assignee: Cisco Technology, Inc.Inventors: Dileep Kumar Devireddy, Michael Smith, Saravanakumar Rajendran, Pradeep K. Kathail, Chandrashekhar Appanna, Jeffrey Ym Wang
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Patent number: 8948204Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header may include an invert bit to alter the majority sign of an n-bit portion. Other aspects of the present invention are also described herein.Type: GrantFiled: April 12, 2010Date of Patent: February 3, 2015Assignee: Cisco Technology, Inc.Inventors: Neil Sharma, Matthew Todd Lawson, Mick R. Jacobs
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Patent number: 8948013Abstract: At least one first frame of a first data flow can be received and passed to a general processor to inspect the at least one first frame. A flow acceleration request can be received including a set of conditions for accelerated processing, by a network processor, of a set of frames in the first data flow subsequent to the at least one first frame. At least one subsequent frame in the set of frames can be processed, using the network processor, in connection with forwarding of the subsequent frame to at least one remote network node, where processing of the subsequent frame is accelerated relative to processing of the at least one first frame and based, at least in part, on the set of conditions included in the flow acceleration request.Type: GrantFiled: June 14, 2011Date of Patent: February 3, 2015Assignee: Cisco Technology, Inc.Inventors: Bhagatram Yaugand Janarthanan, Imnaz Meher Jilani, Robert A. Mackie, Tzu-Ming Tsang, Walter Dixon
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Patent number: 8948042Abstract: Disclosed is a technique for predictively caching IP content data for a mobile device. In the mobile device, a content request is sent to an intelligent cache server over an IP network, the content request indicative of recurring IP content data of interest to the mobile device. The intelligent cache server retrieves the requested IP content data from content servers and queues the requested IP content data in a buffer associated with the mobile device. A notification message is sent to the mobile device indicating that the requested IP content is queued. The mobile device determines whether it is connected to a non-cellular IP network access point and automatically downloads the queued IP content data from the intelligent cache server when connected to a non-cellular IP network. The IP content data is stored in a cache memory in the mobile device. Other embodiments are disclosed.Type: GrantFiled: July 21, 2014Date of Patent: February 3, 2015Assignee: Bandwidth.com, Inc.Inventors: James Mulcahy, Sai Rathnam
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Patent number: 8948193Abstract: Methods, devices, and media for intelligent NIC bonding and load-balancing including the steps of: providing a packet at an incoming-packet port of a gateway; attaching an incoming-port identification, associated with the incoming-packet port, to the packet; routing the packet to a processing core; passing the packet through a gateway processing; sending the packet, by the core, to the operating system of a host system; and routing the packet to an outgoing-packet port of the gateway based on the incoming-port identification. Preferably, the gateway processing includes security processing of the packets. Preferably, the step of routing the packet to the outgoing-packet port is based solely on the incoming-port identification. Preferably, an outgoing-port identification, associated with the outgoing-packet port, has an identical bond-index to the incoming-port identification.Type: GrantFiled: August 19, 2008Date of Patent: February 3, 2015Assignee: Check Point Software Technologies, Ltd.Inventors: Amnon Perlmutter, Benzi Waisman
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Patent number: 8942249Abstract: A synchronization method, a communication handover method, a radio network, and a RAN node are disclosed. The interface information synchronization method includes determining whether a condition for initiating interface information update is fulfilled. Information about the S1 interface between the RAN node and the core network node, is sent. In addition, or alternatively, information about the X2 interface between the RAN node and the neighboring RAN node is sent to the neighboring RAN node if the condition for initiating interface information update fulfilled.Type: GrantFiled: July 2, 2012Date of Patent: January 27, 2015Assignee: Huawei Technologies Co., Ltd.Inventor: Yong Qiu
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Publication number: 20150023367Abstract: An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD.Type: ApplicationFiled: March 25, 2011Publication date: January 22, 2015Inventors: Coke S. Reed, David Murphy
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Patent number: 8937966Abstract: Base modules are provided over a backplane network for high availability control of industrial processes or machines. The base modules may include, for example, an I/O base module, which may control the industrial processes or machines and which may releasably receive an I/O function card, an adapter base module, which may communicate with an industrial controller over a separate control network, and a bus expansion base module, which may provide coupling to another bank of base modules. The base modules may be arranged side-by-side via electrical and mechanical connections. Logic of the I/O base module may detect the presence or absence of the I/O function card to allow coupling or bypassing of the I/O function card with respect to the backplane network.Type: GrantFiled: April 14, 2014Date of Patent: January 20, 2015Assignee: Rockwell Automation Technologies, Inc.Inventors: Robert J. Kretschmann, David S. Wehrle, Gerald R. Creech
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Patent number: 8937959Abstract: A distributed switch may include a hierarchy with one or more levels of surrogate sub-switches (and surrogate bridge elements) that enable the distributed switch to scale bandwidth based on the size of the membership of a multicast group. When a sub-switch receives a multicast data frame, it forwards the packet to one of the surrogate sub-switches. Each surrogate sub-switch may then forward the packet to another surrogate in a different hierarchical level or to a destination computing device. Because the surrogates may transmit the data frame in parallel using two or more connection interfaces, the bandwidth used to forward the multicast packet increases for each surrogate used.Type: GrantFiled: December 7, 2012Date of Patent: January 20, 2015Assignee: International Business Machines CorporationInventors: Claude Basso, Todd A. Greenfield, Bruce M. Walk
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Patent number: 8937965Abstract: A switch unit, which is connected to one or more computers and one or more storage systems, comprises an update function for updating transfer management information (a routing table, for example). The storage system has a function for adding a virtual port to a physical port. The storage system migrates the virtual port addition destination from a first physical port to a second physical port and transmits a request of a predetermined type which includes identification information on the virtual port of the migration target to the switch unit. The transfer management information is updated by the update function of the switch unit so that the transfer destination which corresponds with the migration target virtual port is the switch port connected to the second physical port.Type: GrantFiled: November 8, 2011Date of Patent: January 20, 2015Assignee: Hitachi, Ltd.Inventors: Norio Shimozono, Shintaro Ito
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Publication number: 20150016468Abstract: A line processing unit and a switch fabric system are disclosed. The line processing unit includes an FIC and an FE. The FIC is connected to the FE through a first connection line. In embodiments of the present application, an LPU and a switching capability can be configured in demand.Type: ApplicationFiled: September 30, 2014Publication date: January 15, 2015Inventor: Yongsheng Wang
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Patent number: 8934335Abstract: An approach is provided for improving network restoration by enhancing loop free alternative coverage. A loop-free alternate (LFA) procedure is initiated for a failed link of a network including a plurality of nodes. A state of incomplete loop-free alternate coverage for the nodes is determined. A shortest path in the network exclusive of the nodes associated with the failed link is determined. Each node along the determined shortest path is set as an explicit route object to create a bypass label switched path for the network.Type: GrantFiled: August 30, 2011Date of Patent: January 13, 2015Assignee: Verizon Patent and Licensing Inc.Inventors: Ning So, William F. Copeland, Fengman Xu
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Patent number: 8934495Abstract: Systems and methods are disclosed that allow for improved management and control of packet forwarding in network systems. Network devices and tool optimizers and a related systems and methods are disclosed for improved packet forwarding between network sources and destination tools in a network monitoring environment. The network devices and tool optimizers disclosed can include a graphical user interfaces (GUIs) through which a user can create and modify filters and select associated filter criteria for forwarding packets from input ports to output ports. The network devices and tool optimizers can also automatically generate filter rules and apply them to the appropriate filter engines so that packets are forwarded as desired by the user. The GUI can be configured to provide other features as well.Type: GrantFiled: July 31, 2009Date of Patent: January 13, 2015Assignee: Anue Systems, Inc.Inventors: Gregory S. Hilton, Ronald A. Pleshek, Charles A. Webb, III, Keith E. Cheney, Himanshu M. Thaker
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Patent number: 8934344Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.Type: GrantFiled: January 29, 2014Date of Patent: January 13, 2015Assignee: Intel CorporationInventors: Mazhar I. Memon, Steven R. King
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Publication number: 20150010013Abstract: According to an example, port negotiation between FCFs is implemented through initiation of a negotiation to an opposite party corresponding to a VFC port on a FCF within a VLAN corresponding to each VSAN supported by the VFC port on the FCF. The port negotiation also includes a determination of an intersection of the VSAN and the VLAN supported by the VFC port and the VSAN and the VLAN supported by the opposite party corresponding to the VFC port on the FCF and performance of an ELP negotiation within the intersection of the VSAN and the VLAN.Type: ApplicationFiled: March 29, 2013Publication date: January 8, 2015Applicant: Hangzhou H3C Technologies Co., Ltd.Inventor: Changjun Zhang
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Publication number: 20150010014Abstract: A switching device comprising a plurality of ingress ports and a plurality of egress ports. The switching device is arranged to receive data packets through said ingress ports and to forward received data packets to respective ones of said egress ports. The switching device is further arranged to: determine a first time at which a first cell of a selected data packet is to forwarded to one of said egress ports, determine a further time at which a respective further cell of the selected data packet is to be forwarded to said one of said egress ports, store data indicating that said respective further cell is to be forwarded at said determined further time, forward said first cell at said first time, and forward said further cell of said selected data packet at said determined further time.Type: ApplicationFiled: September 23, 2014Publication date: January 8, 2015Inventor: Stephen John Marshall
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Patent number: 8929363Abstract: A network switch including a port receiving a first frame. A memory includes first buffers available to store frames and second buffers reserved for the port. A pointer module stores first pointers for the first buffers. A reserve module includes a counter, requests from the pointer module some of the first pointers, and increments the counter to count a number of pointers reserved for the first port. The pointers received from the pointer module are deemed reserved and as a result the first buffers, pointed to by the pointers received from the pointer module, are included in the second buffers. An ingress module stores the first frame in some of the second buffers and determines a destination channel for the first frame. The counter is incremented for each of the second buffers used to store the first frame. An egress module transmits the frame on the destination channel.Type: GrantFiled: January 27, 2014Date of Patent: January 6, 2015Assignee: Marvell International Ltd.Inventor: Hugh M. Walsh
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Patent number: 8923320Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a network interface and a processor. The network interface may include a plurality of physical ports, each physical port configured to be coupled to a corresponding switch interfacing between the physical port and a switching fabric comprising one or more virtual local area networks. The processor may be configured to receive workload requirements defining operational parameters for one or more virtual network interface controllers and automatically assign each of the one or more virtual network interface controllers to a partition of one of the plurality of physical ports based on the operational parameters.Type: GrantFiled: December 10, 2012Date of Patent: December 30, 2014Assignee: Dell Products L.P.Inventors: Pallavi Dasari, Sudhir Shetty
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Publication number: 20140376549Abstract: A packet processing method includes receiving a forwarding decision made for an input packet; and creating a packet processing list of the input packet according to the forwarding decision. When the forwarding decision indicates that the input packet is required to undergo first packet processing operations, each including a common processing operation and an individual processing operation, to generate first output packets forwarded via first egress ports, respectively, first information indicative of the first egress ports is recorded in an egress port field of a first session of the packet processing list; second information indicative of the common processing operation shared by all of the first packet processing operations is recorded in a common processing field of the first session; and third information indicative of individual processing operations of the first packet processing operations is recorded in an individual processing field of the first session.Type: ApplicationFiled: May 1, 2014Publication date: December 25, 2014Applicant: MEDIATEK INC.Inventor: Kuo-Cheng Lu
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Publication number: 20140376557Abstract: Layout-aware modular decoupled crossbar and router for on-chip interconnects and associated micro-architectures and methods of operation. A crossbar and router architecture called MoDe-X (Modular Decoupled Crossbar) is disclosed that supports 5-port routing for use in 2D mesh interconnects and is implemented through use of decoupled row and column sub-crossbar modules in combination with feeder wiring and control logic that enables routing between ports on the row and column sub-crossbar modules. The corresponding MoDe-X router supports 5-port routing between various router input and output port combinations while reducing both router area and power consumption when compared with a conventional 5×5 crossbar design and implementation. The MoDe-X micro-architecture can be configured to support both single and dual local port injection configurations.Type: ApplicationFiled: February 9, 2012Publication date: December 25, 2014Inventors: Dongkonk Park, Aniruddha Vaidya, Akhilesh Kumar, Mani Azimi
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Publication number: 20140376566Abstract: The PCS and FEC layers are combined into a single layer and the number of lanes is set at four lanes. The combination allows removal of many modules as compared to a serial arrangement of a PCS layer and an FEC layer. The reduction in the number of lanes, as compared to 100 Gbps Ethernet, provides a further simplification or cost reduction by further reducing the needed gates of an ASIC to perform the functions. Changing the lanes in the FEC layer necessitates changing the alignment marker structure. In the preferred embodiment a lane zero marker is used as the first alignment marker in each lane to allow rapid sync. A second alignment marker indicating the particular lane follows the first alignment marker.Type: ApplicationFiled: June 18, 2014Publication date: December 25, 2014Inventors: Anil Mehta, Scott Kipp
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Patent number: 8917742Abstract: A network interface that connects a computing device to a network may be configured to process incoming packets and determine an action to take with respect to each packet, thus decreasing processing demands on a processor of the computing device. The action may be indicating the packet to an operating system of the computing device immediately, storing the packet in a queue of one or more queues or discarding the packet. When the processor is interrupted, multiple packets aggregated on the network interface may be indicated to the operating system all at once to increase the device's power efficiency. Hardware of the network interface may be programmed to process the packets using filter criteria specified by the operating system based on information gathered by the operating system, such as firewall rules.Type: GrantFiled: July 13, 2011Date of Patent: December 23, 2014Assignee: Microsoft CorporationInventors: Osman N. Ertugay, David G. Thaler, Mahender Hari, Andrew J. Ritz, Alireza Dabagh
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Patent number: 8917746Abstract: A method and apparatus embodying some aspects of a packet processing communication system. The packet processing communication apparatus comprises a packet processor and a microprocessor. The packet processor is configured to process packets belonging to a certain flow through a plurality of processing stages of a programmable data-path. The microprocessor is in communication with the packet processor and is configured to process a user-defined function in the programmable data-path on designated packets belonging to the certain flow. The packets of respective flows to be processed by the microprocessor are designated in a mapping. The designated packets processed by the microprocessor are returned to one of the processing stages of the packet processor for further processing.Type: GrantFiled: March 20, 2013Date of Patent: December 23, 2014Assignee: Broadcom CorporationInventor: Gal Sitton
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Publication number: 20140369361Abstract: A method of communications in a network interconnecting at least two power generators, each power generator being connected to said network by means of at least one interfacing device capable of sending and receiving communications frames, said frames comprising at least one piece of supervision data and at least one piece of information data. The method may include a step for sending during which the same pieces of information data are sent at least twice, two operations for sending frames to be sent that comprise identical pieces of information data being separated in time by a predetermined time interval, and a step for receiving, implementing a systematic elimination of one of the frames received when two frames comprising identical pieces of information data have been received.Type: ApplicationFiled: June 17, 2014Publication date: December 18, 2014Inventor: Jean François de Sallier Dupin
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Patent number: 8913630Abstract: An apparatus comprising a data framer configured to frame an external protocol extension message for transmission, the external protocol extension message comprising a header that indicates an external protocol extension and at least one type-length-value (TLV) comprising a type field, a length field, and a value field, wherein a format of the TLV is specified by a specific organization, and wherein the value field comprises information related to protocol functions external to the network. Also included is an apparatus comprising at least one component configured to implement a method comprising compiling an external protocol extension message comprising a plurality of TLVs and a header that indicates an external protocol extension, and transmitting the external protocol message.Type: GrantFiled: February 28, 2012Date of Patent: December 16, 2014Assignee: Futurewei Technologies, Inc.Inventors: Frank J. Effenberger, Bo Gao, Wei Lin
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Patent number: 8913620Abstract: A distributed switch may include a hierarchy with one or more levels of surrogate sub-switches (and surrogate bridge elements) that enable the distributed switch to scale bandwidth based on the size of the membership of a multicast group. When a sub-switch receives a multicast data frame, it forwards the packet to one of the surrogate sub-switches. Each surrogate sub-switch may then forward the packet to another surrogate in a different hierarchical level or to a destination computing device. Because the surrogates may transmit the data frame in parallel using two or more connection interfaces, the bandwidth used to forward the multicast packet increases for each surrogate used.Type: GrantFiled: March 14, 2012Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Claude Basso, Todd A. Greenfield, Bruce M. Walk
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Patent number: 8913615Abstract: A shared network interface controller (NIC) interfaces a plurality of operating system domains as part of the load-store architecture of the operating system domains. A bus interface couples the NIC to a load-store domain bus (such as PCI-Express), using header information to associate data on the bus with an originating operating system domain. Transmit/receive logic connects the NIC to the network. Association logic allows the NIC to designate, and later lookup which destination MAC address (on the Ethernet side) is associated with which operating system domain. Descriptor register files and Control Status Registers (CSR's) specific to an operating system domain are duplicated and made available for each domain. Several direct memory access (DMA) engines are provided to improve throughput. Packet replication logic, filters (perfect and hash) and VLAN tables are used for looping back packets originating from one operating system domain to another and other operations.Type: GrantFiled: May 9, 2012Date of Patent: December 16, 2014Assignee: Mellanox Technologies Ltd.Inventor: Christopher J. Pettey
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Patent number: 8913624Abstract: A synchronization method, a communication handover method, a radio network, and a RAN node are disclosed. The interface information synchronization method includes determining whether a condition for initiating interface information update is fulfilled. Information about the S1 interface between the RAN node and the core network node, is sent. In addition, or alternatively, information about the X2 interface between the RAN node and the neighboring RAN node is sent to the neighboring RAN node if the condition for initiating interface information update fulfilled.Type: GrantFiled: July 2, 2012Date of Patent: December 16, 2014Assignee: Huawei Technologies Co., Ltd.Inventor: Yong Qiu
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Patent number: 8908748Abstract: An interface circuit includes an interface terminal, a voltage detection device, an output driver and an enable logic. The interface terminal is configured to connect to an interface line. The voltage detection device is configured to detect a voltage present at the interface terminal. The output driver is configured to apply an output signal to the interface terminal. The enable logic is configured to generate an enable signal for the output driver based on an evaluation signal output by the voltage detection device, wherein the enable signal affects an enabling of the output driver if the evaluation signal shows that the voltage present at the interface terminal meets a given condition.Type: GrantFiled: October 15, 2012Date of Patent: December 9, 2014Inventors: Klaus Buchner, Klemens Kordik, Christian Unhold
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Publication number: 20140355610Abstract: A method, an apparatus, and a computer program product for power line communication (PLC) are provided. The apparatus receives a first packet, selects a bus from a plurality of PLC buses, each PLC bus isolated from other buses of the plurality of buses, and forwards the first packet to a destination PLC modem connected to the selected bus. A method and system for switched power line communication (PLC) is also provided. The system provides power to a plurality of PLC buses via a main circuit breaker, receives a first signal for communicating to a PLC bus, selects a PLC bus from the plurality of buses based on the first signal, communicates a second signal to the selected PLC bus, the second signal based on the first signal, and filters the second signal communicated to the selected PLC bus to prevent the second signal from passing through the main circuit breaker.Type: ApplicationFiled: May 31, 2013Publication date: December 4, 2014Inventors: Feng GE, Jinder WANG, Vincent D. PARK, Junyi LI
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Patent number: 8902915Abstract: A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.Type: GrantFiled: September 24, 2012Date of Patent: December 2, 2014Assignee: Intel CorporationInventors: Dinakar Munagala, Hong Jiang, Bishara Shomar, Val Cook, Michael K. Dwyer, Thomas Piazza
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Patent number: 8902922Abstract: This invention is a low level programmable logic that can communicate with Media Independent Interface (MII) (Ethernet) interface in a highly configurable manner under the control of a CPU. This invention is highly configurable for various existing and new Ethernet based communication standards, programmable in an easy to learn assembly language, low power and high performance.Type: GrantFiled: January 4, 2013Date of Patent: December 2, 2014Assignee: Texas Instruments IncorporatedInventors: Maneesh Soni, William C. Wallace
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Publication number: 20140348178Abstract: A switching device in a network system for transferring data includes one or more source line cards, one or more destination line cards and a switching fabric coupled to the source line cards and the destination line cards to enable data communication between any source line card and destination line card. Each source line card includes a request generator to generate a request signal to be transmitted in order to obtain an authorization to transmit data. Each destination line card includes a grant generator to generate and send back a grant signal to the source line card in response to the request signal received at the destination line card to authorize the source line card to transmit a data cell to the destination line card.Type: ApplicationFiled: August 7, 2014Publication date: November 27, 2014Inventors: Pradeep S. SINDHU, Philippe LACROUTE, Matthew A. TUCKER, John D. WEISBLOOM, David B. WINTERS
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Patent number: 8897313Abstract: An out-of-band to optical conversion component is provided that uses a transmit disable signal and a receive loss of signal (LOS) signal built into optical small form-factor pluggable transceiver and cable to pass the out-of-band protocol between serial attached SCSI enclosures. The transmit disable signal, when asserted, turns off the optical output, while the receive LOS signal detects the loss of signal. The out-of-band to optical conversion component sits in line on the serial attached SCSI data traffic and strips off the out-of-band signals from the serial attached SCSI expander so that only data flows over the optical cable. The out-of-band to optical conversion component sends the out-of-band signals to the other enclosure using the transmit disable pin on the small form-factor pluggable transceiver and cable. The other enclosure receives the message on the receive LOS signal and transmit it back onto the serial attached SCSI receive data pair.Type: GrantFiled: January 31, 2007Date of Patent: November 25, 2014Assignee: International Business Machines CorporationInventors: Brian James Cagno, John Charles Elliott
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Patent number: 8897186Abstract: Methods and apparatus for communicating with the Internet via a gateway are disclosed. The gateway may be a Radio Access Network (RAN) gateway. The gateway may communicate data with at least one user equipment (UE). The gateway may route the data via one or more interfaces. The data may be routed by bypassing a core network.Type: GrantFiled: April 29, 2013Date of Patent: November 25, 2014Assignee: Signal Trust for Wireless InnovationInventors: Prabhakar R. Chitrapu, Narayan Parappil Menon, Fatih M. Ozluturk, Brian Gregory Kiernan
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Patent number: 8897314Abstract: Aspects of the disclosure can provide a network switch having reduced power consumption. The network switch can include a plurality of ports that are configured to receive and transmit network traffic. The plurality of ports can be configured in a power-on mode and a power-off mode. Further, at least a first port among the plurality of ports can be configured to remain in the power-on mode and to receive power control instructions. In addition, the network switch can include a power controller. The power controller can change the power modes of selected ports among the plurality of ports in response to the power control instructions received through the first port.Type: GrantFiled: December 18, 2012Date of Patent: November 25, 2014Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Denis Krivitski, Youval Nachum