Centralized Switching Patents (Class 370/422)
  • Patent number: 5872822
    Abstract: A method and apparatus for delaying frames received asynchronously from a fiber channel port until receive memory is properly sequenced for storing the delayed frames in which a circular buffer is positioned on the data path between the fiber channel port and the receive memory for delaying the frames in accordance with control signals generated by a sequencer having knowledge of the receive memory sequence count.
    Type: Grant
    Filed: October 26, 1995
    Date of Patent: February 16, 1999
    Assignee: McData Corporation
    Inventor: Dwayne R. Bennett
  • Patent number: 5864537
    Abstract: A media information distribution service system, such as a video-on-demand service system, is disclosed which, even if the capacity of a line is small and the number of lines connected to a media server, such as a video server, has to be increased accordingly, permits an uneconomical increase in the number of line circuits in the media server to be checked. In the system, a subscriber group that a distributor accommodates can be associated with a plurality of distributor-side paths on a distributor-side line. Each of the distributor-side paths is connected to a respective one of server-side paths on separate server-side lines connecting the media server and an exchange. In sending media information to a subscriber group, an in-server path control unit installed in the media server is permitted to select a free one out of server-side paths on server-side lines allocated for that subscriber group and activates a line interface corresponding to the free server-side path.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: January 26, 1999
    Assignee: Fujitsu Limited
    Inventors: Toshiyuki Hijikata, Tetsuo Tachibana, Toshio Irie, Tatsuru Nakagaki, Masayuki Yamanaka, Katsutoshi Inoko, Takashi Hatano
  • Patent number: 5864553
    Abstract: A multiport frame exchange system is disclosed having a plurality of input and output lines and which outputs frame data inputted from these input and output lines to desired input and output lines based on frame header information. This multiport frame exchange system is composed of input frame buffers provided for each input line that store inputted frames; output frame buffers provided for each output line that store and output output frames; a header processor that processes the headers of frames; and a self-routing section that connects the input frame buffers, the output frame buffers, and the header processor.
    Type: Grant
    Filed: January 8, 1997
    Date of Patent: January 26, 1999
    Assignee: NEC Corporation
    Inventor: Toshiya Aramaki
  • Patent number: 5859849
    Abstract: A modular switch element (12) is programmable to operate in conjunction with varying numbers of other modular switch elements in a shared memory switch fabric (10). A single modular switch element type can be used to construct a range of shared memory switch fabrics operable over a wide range of bandwidth requirements.
    Type: Grant
    Filed: May 6, 1997
    Date of Patent: January 12, 1999
    Assignee: Motorola Inc.
    Inventor: Charley Michael Parks
  • Patent number: 5859844
    Abstract: A switching unit of a cross connecting device is expanded with no momentary interruption, while data loss and data overlapping is eliminated. To achieve such an expansion, a cross connecting device comprises a base set having a switching unit for determining an output channel based on virtual path information for cell data that is input and for outputting the cell data. An expanded set has a switching unit for receiving the cell data from the base set and cell data from another base set, and for determining an output channel based on virtual path information for both inputs of cell data and for outputting the cell data. A filter prevents the transmission, to the expanded set, of cell data for which the output channel is determined by the switching unit of the base set.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: January 12, 1999
    Assignee: Fujitsu Limited
    Inventors: Keiichi Kanno, Ryuichi Kondo, Koya Sakurai, Toshifumi Fujimoto
  • Patent number: 5859845
    Abstract: A control signal generated as a result of the actuation of each of control switches of a control section is multiplexed by a multiplexing section, and the thus multiplexed signal is sent to a multiplex transmission line. Load control sections receive the multiplexed control signal sent over the multiplex transmission line. The load control sections then control the electric power fed to a corresponding one of loads on the basis of the received control signal. Control data, representing the form of output control of the corresponding load which is controlled as a result of the actuation of the control switch, are stored according to the control switches. Control means control the electric power fed to the load on the basis of the control signal using the control data.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: January 12, 1999
    Assignee: Yazaki Corporation
    Inventors: Tatsuaki Oniishi, Akiyoshi Kanazawa, Nobuhiro Imaizumi
  • Patent number: 5844904
    Abstract: A digital message switching system includes at least one digital message switching unit and a plurality of subordinate units each being coupled to the respective switching unit through a respective transmission link. In order to signal a request of a subordinate unit to transmit, that unit first sends at least one message of meaningless content to a higher-ranking unit and only then sends messages of meaningful content.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: December 1, 1998
    Assignee: Siemens Aktiengesellschaft
    Inventors: Yousif Ammar, Gerald Hoefer, Michael Alger-Meunier
  • Patent number: 5841775
    Abstract: A N input and N output, scalable switching network (80) is implemented with an array of log base x of N rows and N/x columns of routers (40-68); where each router has 2x ports and where the rows of routers are connected to each other via a blocking compensated cyclic group mapping interconnect (49 and 59). A N input and N output, bi-directional scalable switching network (90) is implemented with an array of log base x of (N/2) rows and (N/2)/x columns of routers (40-68); where each router has 2x ports, and where the rows of routers are connected to each other via a blocking compensated cyclic group mapping interconnect (49 and 59). The routers provide destination routing. The levels of blocking compensated cyclic group mapping interconnect provide connectivity between the rows of routers.
    Type: Grant
    Filed: July 16, 1996
    Date of Patent: November 24, 1998
    Inventor: Alan Huang
  • Patent number: 5838684
    Abstract: An plesioasynchronous and asynchronous router circuit communicates with neighboring router circuits and nodes. Each of the router circuits includes a plurality of input ports for receiving frames of data and a plurality of output ports for transmitting frames of data. Each router circuit further includes a plurality of input buffers for storing frames of data received at an input port, and an arbiter system for choosing one of several input buffers associated with a particular one of said output ports. The arbiter system includes a plurality of arbiter subsystems associated with corresponding ones of said plurality of output ports. The plesioasynchronous and asynchronous router circuit further includes a crossbar switch for connecting an arbiter selected input buffer with a particular one of said output ports.
    Type: Grant
    Filed: February 22, 1996
    Date of Patent: November 17, 1998
    Assignee: Fujitsu, Ltd.
    Inventors: Thomas M. Wicki, Jeffrey D. Larson, Albert Mu, Raghu Sastry
  • Patent number: 5818823
    Abstract: A slot assign system has a central station and a plurality of peripheral stations, and the communication between them is made through an artificial satellite. The central station stores pre-assign slot information of each of the peripheral stations, and multiplexes slot assign information to be changed at a next frame over the pre-assign slot information. The peripheral station, on receipt of the slot assign information, transmits the next frame using a slot assigned to itself. The central station sends a vacant slot with no pre-assignment as a non-assign information signal, and the peripheral station recognizing the vacant slot transmits, using the slot assigned to itself, a reservation request for using the vacant slot. The central station transmits a frame next to the frame to which the slot has been assigned.
    Type: Grant
    Filed: March 5, 1996
    Date of Patent: October 6, 1998
    Assignee: NEC Corporation
    Inventor: Hiroaki Nakanishi
  • Patent number: 5768361
    Abstract: The Flexible Enhanced Signaling Subsystem (FESS) performs table-driven processing of incoming and outgoing messages and also handles multiple message types and trunk groups. A message received by the FESS is first processed by an incoming signaling module which performs all necessary transformations to the message to enable the existing switch processing to handle any incoming message. The incoming signaling module, being table-driven, can be easily modified to handle any new message types which may be created. The message is then processed by an intermediate signaling module which includes the existing call processing, The intermediate signaling module may pass through messages, or it may generate new messages. In either case, an outgoing signaling module performs all necessary transformations to messages output from the intermediate signaling module to enable the outgoing trunk, downline switch or downline network to handle the message properly.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: June 16, 1998
    Assignee: MCI Corporation
    Inventor: George A. Cowgill
  • Patent number: 5754550
    Abstract: A switching system comprises a time division switch for forming a fixed path through which a line circuit and a trunk circuit are connected to each other. Both the line circuit and the trunk circuit have a discrimination function and a transfer function. For example, when the trunk circuit receives system data packets including predetermined system data packets from a call processor, the trunk circuit discriminates the predetermined system data packets from the system data packets using an identifier of each packet. The predetermined system data packets are transferred to the line circuit through the fixed path of the time division switch. Receiving the predetermined system data packets from the trunk circuit, the line circuit stores the predetermined system data as well as system data for the trunk circuit received from the call processor into a memory thereof.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: May 19, 1998
    Assignee: NEC Corporation
    Inventor: Koji Endo
  • Patent number: 5740175
    Abstract: A LAN network switch includes a RAM forwarding database which contains the address-to-port mappings for all the workstations or other devices connected to the switch's plurality of ports and further includes at least one CAM-cache connected to respective one or more of the switch's ports. The CAM-cache, having an access time much faster than that of the forwarding database, stores selected ones of the address-to-port mappings. When it is desired for the switch to forward a packet, the destination address is extracted and the CAM-cache is accessed and searched. If the correct mapping is contained in the CAM-cache, the packet is immediately forwarded to the destination port without accessing the much larger and slower forwarding database. Only if the CAM-cache does not contain the correct mapping is the forwarding database accessed to retrieve the correct mapping.
    Type: Grant
    Filed: October 3, 1995
    Date of Patent: April 14, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Laurence N. Wakeman, Roy T. Myers, Jr.
  • Patent number: 5724353
    Abstract: The object of the invention is to provide a method and a circuit for a crosspoint buffer-type self-routing switch circuit in an ATM switch that allows a switch of higher speed and greater efficiency with a more compact hardware construction and without complicated circuit configuration or operation.
    Type: Grant
    Filed: December 14, 1995
    Date of Patent: March 3, 1998
    Assignee: NEC Corporation
    Inventor: Tsugio Sugawara
  • Patent number: 5724348
    Abstract: A data switch is described with a multi-port data switching element, one or more input/output adapters for receiving user data cells from outside the switch and for transmitting cells switched through the switching element to a network outside the switch, and a control element including a control processor. To reduce the complexity of the data switch, the single control processor is used to control operations of hardware modules on both the the control element on which the processor is located and on the input/output adapters. The control is provided by means of control cells which generally traverse the same data paths as user data cells and generally conform to the format of user data cells, at least within the data switch. Both the control processor and the hardware modules are capable of generating control cells and transmitting them toward a target, either the control processor or hardware modules.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: March 3, 1998
    Assignee: International Business Machines Corporation
    Inventors: Claude Basso, Jean Calvignac, Mathieu Girard, Daniel Orsatti, Michel Susini, Fabrice Verplanken
  • Patent number: 5715247
    Abstract: Disclosed is a method of sending and receiving setting information and monitoring information between a monitoring controller and units which construct the multiplexing section of a communication apparatus. In a case where setting information is transferred from the monitoring controller to a prescribed unit, the monitoring controller time-division multiplexes the setting information for the unit and enters the information into a time switch via an incoming line. The time switch switches the time slot position of the setting information and sends the setting information to an outgoing line corresponding to the unit. The unit drops the setting information from the time slot. Further, in a case where monitoring information is transferred from a unit to the monitoring controller, the unit time-division multiplexes the monitoring information to a predetermined time slot and enters the monitoring information into the time switch from a prescribed line.
    Type: Grant
    Filed: March 18, 1996
    Date of Patent: February 3, 1998
    Assignee: NEC Corporation
    Inventors: Hiroichi Nara, Jinichi Yoshizawa
  • Patent number: 5610904
    Abstract: A packet-based telecommunications architecture is disclosed that, like virtual-circuit networks, preserves the sequential order in which packets are presented to the network, but does not require node-by-node call set-up or tear-down, unlike virtual-circuit networks. Further, the packet switches which compose the architecture can be more simple than those used in datagram or virtual-circuit networks. An illustrative embodiment of the present invention comprises determining the topology of a network of packet switches that are connected by communication links, associating at least two names with at least one of the packet switches, and populating the router tables in the packet switches so that for each name the packet switches and communication links form a elemental network with the topology of a sink tree with the named packet switch at the root of the tree.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: March 11, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Kai Y. Eng, Mark J. Karol, Malathi Veeraraghavan