Abstract: A set of piconets and corresponding methods and computer programs may reduce contention time between piconets. In one embodiment, a seven-length code architecture may be used with group(s) of bands so that contention time cannot exceed 1/7 of the time. Up to seven different bands can be used within each group. When less than seven bands are used (e.g., three or six), at least one of the bands may be assigned to more than one dwell time during a time span. Alternatively, each dwell time within the time span may be assigned to a different band. The state may be changed as needed or desired. Substitution of extra bands may also be used. Using either scheme (repeated bands or changing states), a prime-number architecture can be used with a non-prime number of different bands. Simultaneous communications using at least two bands within a piconet may be used.

Abstract: A mobile station in a TDMA network can perform automatic frequency using burst in all or any slot in a control channel. This is achieved by identifying the training sequence of an arbitrary set of or all received bursts.

Abstract: A Media Access Control (MAC) protocol scheme for binding a response to a frame that requested the response. The response specifies a portion of the frame check sequence contained in the frame. The specified portion of the frame check sequence serves to identify the response as belonging to that frame.

Abstract: A method and apparatus for processing packetized data spanning multiple clock cycles includes at least one comparator, for comparing a present clock cycle count to a reference clock cycle count, wherein the reference clock cycle values may be anywhere within the packet and may be non-contiguous with other reference clock cycle values. At least one word recognizer, compares a presently clocked word to a reference word, and an output circuit provides an indication of a favorable word comparison that occurred in response to a favorable clock cycle count comparison.

Abstract: A method, apparatus and software program is provided for scheduling and admission controlling of real-time data packet traffic. Data packets are admitted or rejected for real-time processing according to throughput capabilities of a packet scheduler. A delivery deadline is determined for each payload data packet at the packet scheduler and packets are sorted into a time-stamp-based queue. Deadline violations are monitored and an adaptation of payload data packets can be triggered on demand in order to enter a stable state.

Abstract: Described are a system, method and device to synchronize block data received in a data stream where the data stream is received on set data word increments. A synchronization header in each of a plurality of consecutive data word increments may be detected in a common location of a set portion or window of each consecutive fixed word increment. The data stream may be slipped by a fixed bit quantity in response to detecting an absence of the synchronization header in the common location of the set portion of a received data word increment.

Abstract: This invention adds one extra bit which can be viewed as a shadow of most significant bit of the serial register. This extra register bit is referred as buffer_flop. When the receive data is coming in, the data bits keep shifting into the serial register of the serializer block bit by bit. The first bits enters into the most significant bit of the serial register and is shifted towards the least significant bit of the serial register. When a whole block of bits (32 bits) are received, the serializer is full and is read into the VBUS clock domain. The first bit of next block of bits is stored in the buffer flop. The second bit is stored in the most significant bit of the serializer and the buffer flop bit is copied into the second most significant bit of the serializer. Subsequent bits are received and right shifted by one.

Abstract: A method and system for performing initial cell search is disclosed. Step 1 processing is preformed to detect a peak primary synchronization code (PSC) location (i.e. chip offset or chip location). Step 2 processing is performed to obtain the toffset and code group. Step 3 processing is performed to identify the midamble of a base station with which the WTRU performing the initial cell search may synchronize with.

Abstract: An apparatus (200) and method (300) for receiving a communications signal. A spread spectrum signal demodulator (210) is adapted to demodulate a packet header (110) of a data packet (102) that is communicated by a wireless communications signal. The packet header (110) is modulated with a spread spectrum technique and the spread spectrum signal demodulator (210) produces a packet header detection signal 220 representing a successful detection of a predefined packet header value. A non-spread spectrum signal demodulator (212) is communicatively coupled to the spread spectrum signal demodulator (210) and demodulates, in response to the packet header detection signal (212), a non-spread spectrum modulated data payload within the data packet. A data output select (234) produces demodulated data produced by either one of both the spread spectrum signal demodulator (210) or the non-spread spectrum signal demodulator (212).

Abstract: A method for receiving at a receiver having a variable filter a transmitted signal that includes a periodic training signal. The method includes (a) receiving and sampling the transmitted signal at the receiver to produce a digital complex baseband signal; (b) filtering the digital complex baseband signal with the variable filter; (c) detecting the periodic training signal in the filtered digital complex baseband signal; (d) determining a desired channel impulse response based on the detected periodic training signal; (e) calculating filter coefficients required by the variable filter to achieve the desired channel impulse response; and (f) adjusting the variable filter according to the calculated filter coefficients. A receiver for implementing the method is also provided.

Abstract: A wireless device may select shorter preambles that enable the use of a newly defined Zero Length Inter-Frame Space (ZIFS). The shortened or zero length preambles may be inserted into a Physical Layer Convergence Protocol (PLCP) preamble as determined by the PHY while maintaining packet/frame synchronization.

Abstract: A method is provided for synchronizing a receiver with a transmitter, wherein a first synchronization signal with a multiplicity of second synchronization signals is transmitted from the transmitter to the receiver, a set of second synchronization signals is subdivided into used code sets and at least one unused code set in such a way that the maximum in the peak values of the cross-correlation functions of the second synchronization signals, which are determined by a used code set, with a first synchronization signal is minimal.

Abstract: A wireless device generates a peak profile for a primary synchronization channel (PSCH), and has a synchronization stage for performing code group identification and scrambling code identification. A first peak from the peak profile is chosen. The first peak has a first path position. The synchronization stage is handed the first path position to obtain a first code group number and a first code number associated with the first peak. A multi-path search window is then opened in the peak profile around the first path position. A second peak within the multi-path search window is selected, and a verification procedure is performed on this second peak to determine if the second peak has a code number that is identical to the first code number. The first code group number is assigned to the second peak if the code number of the second peak is identical to the first code number.

Abstract: A digital information mapper and method for mapping sequences of information characters into a SONET (synchronous optical network) payload in such a manner that there can be an arbitrary mixture of control and/or data values in those sequences. Each information character comprises 9 bits consisting of an 8 bit information byte, being either a control byte or a data byte, and one octet type bit identifying the byte as control or data. A processor applies a mapping algorithm of a mapping module to the input information characters. The mapping algorithm is applied to sequences of eight input information characters, the algorithm being operable to map the information bytes of each sequence of eight information characters to eight of a sequence of nine contiguous SPE octets. The algorithm then maps the octet type bits for the eight mapped information bytes of the character sequence to the ninth octet of the contiguous SPE octets of the SPE octet sequence.

Abstract: A system for receiving and handling a scrambled input data signal that includes a preamble with a start of frame delimiter (SFD) initiates an SFD search on the scrambled input data, thereby attempting to save an initialization period. The initialization period may be of the order of 7 uS, and its saving results in improved timeline management enabling antenna diversity and the possible use of high performance algorithms. The system may use two parallel paths for signal processing, each having an SFD detector and a descrambler. If the detected SFD is short, then the second path is disabled, and if it is long, then the first parallel path is disabled. Alternatively, the first path can be used for a finite period of time (for e.g., 40 symbols) and if the SFD is still not detected, the first path is disabled, and the system uses only the second path.

Abstract: A timing control circuit includes a synchronous detecting portion which detects a synchronous pattern data of a received signal which has been demodulated based on a first control signal and generates a detection result, a first counter portion which generates a first signal at each first cycle based on the detection result, a second counter portion which generates a second signal at each second cycle based on the detection result, and a first control portion which generates the first control signal based on the first and second signals.

Abstract: In a first step, slot synchronization may be obtained by setting in correlation the received signal with a primary sequence, which represents the primary channel, and storing the received signal. During a second step, the correlator may be re-used for correlating the received signal with a secondary sequence corresponding to the secondary synchronization codes. The correlator may include a first filter and a second filter connected in series, which receive a first secondary sequence and a second secondary sequence, which may include Golay sequences. Architectures of parallel and serial types, as well as architectures designed for reusing further circuit parts are also disclosed. The invention is particularly applicable in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95, and WBCDMA.

Abstract: A mobile station includes a timing controller for adjusting a frame transmit timing so that a unique word detection position at a base station is always located on a predetermined position. Even when frequent changes in the distance between the base station and mobile station occur due to movement of the mobile station, synchronization between the stations can be established, and this synchronization can be maintained.

Abstract: Techniques for establishing TTR indication in ADSL Annex C based communication systems are disclosed. The techniques enable, for example, hyperframe alignment and synchronized initialization procedures (e.g., G.hs).

Abstract: A method of transmitting timing critical data via an asynchronous channel without changing any datum to be transmitted. The timing critical data can be an MPEG transport stream. The asynchronous channel can be a computer or telephone network, a digital storage media such as a digital VCR, or a digital interface. The method involves tagging each transmission unit of the data stream, before inputting to the channel, with timing information, and using the timing information at the output end of the channel to recreate the proper data timing, Various schemes are described for packing the timing information tags with each or a plurality of transmission units.

Abstract: A radio terminal unit and a radio communication system, enabling power savings, the improvement of the quality of real-time communication, and the reduction of transmission delays. An operation mode determination section determines whether real-time processing is necessary or unnecessary based on parameters of all active communication applications set by a communication application section. When real-time processing is necessary, a communication control section transmits a PS-Poll as a control packet for requesting delivery of packets to a radio base station, and turns on the power of a radio interface section so as to receive packets buffered by the radio base station. When real-time processing is unnecessary, the communication control section turns off the power of the radio interface section, and carries out intermittent receiving operation based on beacons transmitted from the radio base station.

Abstract: An apparatus and method for measuring and compensating for delay between a main base station and a remote base station interconnected by an optical cable. The main base station inserts a test pattern into an overhead part of an SDH frame to transmit the SDH frame to the remote base station, receives the SDH frame looped back by the remote base station to detect the test pattern, and measures propagation delay according to the test pattern. At least one frame alignment word (FAW) is detected at a predetermined position in the received SDH frame, and a delay error is calculated according to FAW detection information. The measured propagation delay with the delay error is compensated and produces propagation delay caused by the optical cable. A modulator/demodulator (MODEM) compensates for delay of a baseband signal to be transmitted to the remote base station.

Abstract: A method and system for providing signaling byte resiliency across a telecommunications network. Embodiments of the invention create copies of original signaling bytes and transports the copies in addition to the original signaling bytes. Testing is performed at each node in the network to determine the validity of the original signaling bytes, i.e. if the signaling bytes have been corrupted. If original signaling bytes are found invalid, then the copies of the signaling bytes are used as a valid replacement for the corrupted signaling bytes.

Abstract: A method and apparatus are provided in which control data for a generator system is multiplexed onto a synchronization signal.

Abstract: A VSB communication system or transmitter for processing supplemental data packets with MPEG-II data packets includes a VSB supplemental data processor and a VSB transmission system. The VSB supplemental data processor includes a Reed-Solomon coder for coding the supplemental data to be transmitted, a null sequence inserter for inserting a null sequence to an interleaved supplemental data for generating a predefined sequence, a header inserter for inserting an MPEG header to the supplemental data having the null sequence inserted therein, a multiplexer for multiplexing an MPEG data coded with the supplemental data having the MPEG header added thereto in a preset multiplexing ratio and units. The output of the multiplexer is provided to an 8T-VSB transmission system for modulating a data field from the multiplexer and transmitting the modulated data field to a VSB reception system.

Abstract: With audio data reduction on the basis of ISO/IEC standard 11172-3, a frame length varying by 8 bits is used at a sampling frequency of 44.1 kHz in order to arrive, on average, at a particular fixed data rate. The lengthening of a data frame is signalled by a padding bit in the header of the frames. The invention dispenses with evaluation of the padding bit. Instead, the mean frame length L is calculated, L is rounded down to the next integer, for the subsequent frame it is first established whether the expected sync word for this frame appears, and, if this is so, this frame is decoded without taking into account the padding bit, but if the expected sync word for this frame does not appear, the decoding of the frame is started one 8-bit later without taking into account the padding bit.

Abstract: A packet stream multiplexer may include one or more control loops (e.g., digital phase locked loops) for tracking the source clock frequency associated with a packet stream. A first control loop may slowly drive an error between a received timestamp and an estimated timestamp to zero. A second control loop may more quickly drive a first derivative of the error to zero. The second control loop may include a set of digital filters ordered according to tracking speed. The output of the slowest filter is initially selected for updating the source clock frequency estimate. As time progresses, the faster filters are selected in succession. The estimated source clock frequency is used to restamp packets of the packet stream as they are sent out onto an output channel.

Abstract: Synchronization and impairment estimations can be performed jointly, thereby saving valuable time for decoding of the received packet. An initial synchronization in a TDMA system can be performed. Using this synchronization, the frequency offset choices and timing offset choices can be advantageously bounded within predetermined ranges. At this point, an algorithm can find the minimum error that gives the best frequency offset choice and timing offset choice combination over their respective ranges, together with the estimates of the signal magnitude and phase and at least one of a DC offset magnitude and phase, and a spur magnitude and phase.

Abstract: Disclosed is a method and apparatus for synchronizing data in a number of separate integrated circuits. In one embodiment, the apparatus includes a first integrated circuit configured to receive first data, and a second integrated circuit coupled to the first integrated circuit configured to receive second data. The second integrated circuit is separate from the first integrated circuit. The second integrated circuit is further configured to synchronize the second data with the first data. In another embodiment, the apparatus includes a first integrated circuit configured to receive first data, and a second integrated circuit coupled to the first integrated circuit configured to receive second data. The second integrated circuit is separate from the first integrated circuit. The second integrated circuit is further configured to detect when the second data is out of synchronization with the first data.

Abstract: A mobile communication apparatus including a base station and at least two mobile stations, having multiple antennas, respectively is provided. In the mobile communication apparatus, the base station restores from feedback signals transmitted from the mobile stations weight information determined in the mobile stations, generates from the restored weight information downlink control information ensuring maximum throughput to each of the mobile stations, and selects from among data of all of the mobile stations data of a desired mobile station(s) to be transmitted, based on the downlink control information. Each of each of the mobile stations has at least one mobile station antenna, the base station has at least two base station antennas, and the downlink control information includes mobile station selection information, an optimal basis matrix index, and optimal gain indices. As a result, nominal peak throughput in multi-antenna mobile communications can be efficiently achieved at low costs.

Abstract: A method of timing in a multi-cell system requiring synchronization of frames in transmission is provided. Transceivers of a wired data interface between a central controller and multiple base stations are synchronized to a frame timing clock up to a difference in propagation delays between the central controller and multiple base stations. The propagation delays are considered as constants, are measured, and are stored in each base station. A unique word is regularly inserted in the data transmitted by the central controller, at a fixed interval. When this unique word is detected by the base station within a fixed period of the frame timing clock, a frame signal delay is initiated at the next rising edge of each frame timing clock. This frame signal delay is equal to the period of the frame timing clock minus the propagation delay. At the end of the frame delay, the frame data is transmitted, and all frames are simultaneously transmitted from different base stations.

Abstract: A method for handling data between a clock and data recovery system CDR and a data processing unit DP of a telecommunications network node TNN of an asynchronous communications network, using a bit rate adaptation circuit BAS, the bit rate adaptation system BAS including a memory unit MEM with a write process circuit Wp controlled by the recovered clock Rclk and a read process circuit Rp controlled by the local clock Lclk where the bit rate adaptation system BAS also includes a pointer synchronization controller PSC which, depending on the data detected on the input data signal DIb1 of the bit rate adaptation system BAS, sets the read and write pointers to a fixed initial address value. A Clock and Data Recovery system and a telecommunications network node TNN of an asynchronous network, which include a bit adaptation circuit BAS according to the invention, are also disclosed.

Abstract: A method of a receiver determining the timing of a signal transmitted in a time-slotted manner, the signal comprising a sequence of information which is repeated at a known interval and has at least a known minimum length. The method performs correlation operations between groups of received slots of information, the groups spaced by the known interval. The groups are moved through the received signal, adding and removing slots, to locate a maximum correlation value sum for the group which should correspond to the timing of the slot. The method also can be used to determine a frequency offset at the receiver and/or an initial phase.

Abstract: An encoder and method for efficient synchronization channel encoding in UTRA TDD mode by: producing a codeword a, where a=dG+z modulo-2, where d represents a predetermined code group to be encoded, G represents a predetermined generator matrix, and z represents a function of the code group number and a row of the generator matrix; producing values sk=2a2k+1+ak;k=0, 1, 2, 3, and associated values b0,b1,b2; and producing a value Sssc associated with the code group, where Sssc=(b0c?(0),b1c?(1),b2c?(2)), c? represents a code within the code group, and b0,b1,b2?(±1,±j). This provides an efficient encoding architecture for the synchronization channel in UTRA TDD mode; and, in addition, by simple manipulation of the generation matrix, a higher chip rate signal may be signalled while still preserving the signalling information for the lower chip rate.

Abstract: In a data processor, a pickup head reads the data from a memory medium. Such data transferred in a plurality of parallel bits in synchronization with the clock signal to a controller unit from a read channel unit. The controller unit detects the predetermined mark for detecting synchronization included in the data in order to establish the synchronization of a series of data to be received from the read channel unit in order to demodulate the data other than the predetermined mark for detecting synchronization. The mark detecting unit in the controller unit detects the predetermined mark for detecting synchronization from the parallel data received with the shift register.

Abstract: To obtain frame synchronization and identify the cell codegroup in a cellular communication system (such as a system based upon the standard 3GPP FDD), there are available the synchronization codes organized in chips or letters transmitted at the beginning of respective slots. Slot synchronization is obtained previously in a first step of the operation of cell search. During a second step, there are acquired, by means of correlation or fast Hadamard transform, the energy values corresponding to the respective individual letters with reference to the possible starting positions of the corresponding frame within the respective slot. Operating in a serial way at the end of acquisition of the aforesaid energy values of the individual letters, or else operating in parallel, the energies of the corresponding words are determined. Of these energies only the maximum word-energy value and the information for the corresponding starting position are stored in a memory structure.

Abstract: A method for generating a preamble sequence in an OFDM (Orthogonal Frequency Division Multiplexing) communication system that uses A sub-carriers in a frequency domain and uses N Tx (Transmission) antennas, includes the steps of: generating N sequences, each having a length of ‘B/N’, by dividing B sub-carriers from among the A sub-carriers by the ‘N’ indicative of the number of the Tx antennas; and mapping, for each of the N sequences, individual components of the sequence to the B/N sub-carriers from among the A sub-carriers on a one by one basis in order to assign the components of the sequence to the B/N sub-carriers, and assigning null data to remaining sub-carriers other than the B/N sub-carriers from among the A-sub-carriers, such that a preamble sequence of a corresponding Tx antenna is generated.

Abstract: The invention relates to an apparatus and a method for ascertaining and correcting the optimum sampling time for an oversampled input bit stream. This involves feeding the data bit blanked with the current sampling phase into the comparative sequence and using the data bit to ascertain a new, corrected sampling phase. This decision-based approach enables the sampling phase to be continuously corrected.

Abstract: A single-wire communication bus couples a transmitting device to a UART in a receiving device. Flow control circuitry in the UART fills a transmit memory buffer with remote data. The UART supplies a remote start bit onto the single-wire bus for each byte of remote data written into the transmit memory buffer. After detecting a remote start bit on the single-wire bus, the transmitting device supplies initial data bits and a stop bit, which together form an RS232 character. Data flow is controlled when the UART supplies a subsequent remote start bit only after data has been read out of the UART freeing up bytes in a receive memory buffer. After the transmitting device detects the subsequent remote start bit, the transmitting device supplies subsequent data bits onto the single-wire bus. In another embodiment, flow control circuitry functionality is performed by flow control code in the receiving device operating system.

Abstract: A method is for decoding a bit stream from a waveform representing the bit stream, having a first synchronization mark, data, and a second synchronization mark. Digitized samples are decoded to form a reconstructed bit stream. The reconstructed bit stream is then stored. At least one of the first synchronization mark and the second synchronization mark are then extracted from the reconstructed bit stream. Finally, the data are extracted from the reconstructed bit stream using an iterative decoding process, in accordance with at least one of the first synchronization mark and the second synchronization mark. As such, loss of the data between the first synchronization mark and the second synchronization mark, if there is a problem with the first synchronization mark, is avoided.

Abstract: In some embodiments, a method includes detecting a tone in each data frame of a sequence of telephony signal data frames. A first data frame of the sequence of telephony signal data frames may be transmitted immediately after detecting the tone therein. Transmission of a last one or last ones of the sequence of telephony signal data frames may be deferred. It may then be determined whether the tone is present in a next data frame that immediately follows the sequence of telephony signal data frames. If it is determined that the tone is not present in the next data frame, the last one or ones of the sequence of data frames and the next data frame may be transmitted. If it is determined that the tone is present in the next data frame, a respective replacement data frame may be transmitted in place of each one of the last one or last ones of the sequence of data frames and in place of the next data frame.

Abstract: A bit synchronization circuit composed of a multiphase data sampling unit for converting each received burst data sets to multiphase data trains, a phase determination unit for generating a control signal indicating an optimum phase data train, an output data selector for selectively passing optimum phase data train indicated by the control signal, and a data synchronization unit for converting the optimum phase data train to a data train in synchronization with a reference clock. The phase determination unit repeatedly detecting the optimum phase data train during the same burst data set is received. When optimum phase varies, the output data selector dynamically switches the optimum phase data train to be supplied to the data synchronization unit.

Abstract: A system receives input data frames that are configured according to a SONET or an SDH standard. The input data is converted to parallel data. The system provides groups of bits along parallel signal lines. In each group of bits, N contiguous bits in the group form a complete word of input data. The system identifies the boundary between complete words in the input data by comparing subsets of the bits to predefined framing patterns. The system then aligns the input data based on the location of each word using the boundary information. The output data of the system includes data that is word aligned. The system can also detect boundaries between the frames.

Abstract: A received synchronization pattern is compared against first and second known synchronization patterns. If the received pattern is of the first known pattern, the payload is processed as voice; and if the received pattern is of the second known pattern, the payload is processed as non-voice. In an alternative, the received pattern is compared against first and second known synchronization patterns. If the received pattern is of the first known pattern, a first operating mode is selected, and if the received pattern is of the second known pattern, a second operating mode is selected.

Abstract: A method of controlling timing for an uplink synchronous transmission scheme is disclosed, including combining time alignment bit (TAB) information transmitted received during a predetermined period, determining a timing renewal value based on the combination, and controlling the transmission timing according to the timing renewal value. Thus, the TAB information transmitted by a base station may be used to synchronize the uplink transmissions of mobile communication devices.

Abstract: In a wireless communications system, transceivers transmit short bursts to a base station, which determines timing corrections from the time of receipt of the burst and transmits the timing corrections to the respective transceivers. In one aspect, the base station indicates to the transceivers a plurality of time slots, each transceiver selects one of the time slots at random, formats a burst including an indicator of the selected time slot and transmits the burst in that slot. In another aspect, the base station transmits to each transceiver a timing uncertainty value, which determines how the timing correction will be modified by the tranceiver as the interval since last receiving a timing correction increases. Data bursts are transmitted in a format comprising a first unique word, a content field and a second unique word, in that order. The bursts are transmitted in a TDMA channel format which can accommodate both short and long bursts in a block format of constant periodicity.

Abstract: A data sync signal detecting device for detecting a sync signal having sync signal detection errors. The detecting device applies the output data of a most-likelihood decoder to shift register bit cells. The data is sequentially shifted and held in the bit cells of the shift register. The bit cell outputs are separated into odd-numbered and even-numbered bit string and applied to first and second pattern matching circuits. The odd-numbered bit string is matched with “01001” by a first pattern matching circuit. The even-numbered bit string is matched with “01011” by a second pattern matching circuit. First and second matching results are applied to a coincidence number adder/majority decision circuit. When coincidence occurs, the matching result is “1”, and when non-coincidence occurs, the matching result is “0”. The coincidence number adder/majority decision circuit produces a sync signal detection output when the first or second matching result is “1”.

Abstract: It is proposed that currently unused portions of transport overhead in frames sent on a high-speed outgoing channel be used to carry error count information from each of four low-speed input channels. At a 4:1 combiner, error monitoring bytes are extracted from transport overhead of frames received on each of the four input channels. Error counts are determined and accumulated for each input channel before being passed to a transport overhead generator for the outgoing channel, where they are inserted as bit patterns in unused portions of the transport overhead. At a receiving demultiplexer, the error counts are extracted from the transport overhead of incoming frames. The extracted error counts are then used to alter the error monitoring bytes included in the transport overhead of frames sent on each of four outgoing channels such that, at the far end of those outgoing channels, a correct number of errors for the three part path may be determined.

Abstract: A system and method are disclosed for parallel compression and decompression of a bitstream. For compression, the bitstream is separated into a plurality of components, and the components are encoded using a compression algorithm. Packets are then constructed from the encoded components. At least one packet is associated with each encoded component and comprises header information and encoded data. The packets are combined into a packetized encoded bitstream. For decompression, the packets are separated from the packetized encoded bitstream using the header information. The packets are then decoded in parallel using a decompression algorithm to recover the encoded data. The plurality of components are reconstructed from the recovered encoded data and combined to-recover the bitstream.

Abstract: Orthogonal sequences can be developed and used for use training and synchronizing in CDMA and TDMA systems. In particular, once a sequence is developed that has the length of the product of the channel length and the number of transmit antennas, the sequence is offset by a different amount for each transmit antenna. For example, each sequence could be offset by a multiple of the channel length for each transmit antenna, where the multiple ranges from 0 to N?1, where N is the number of transmit antennas. Furthermore, by not using exactly the same amount of offset shifting for each transmit antenna, e.g., not having each signal offset by the channel length, but keeping the overall total shifting the same, e.g., the average of each shift is the channel length, it is possible to determine at a receiver from which transmit antenna a particular signal originated.