Abstract: A clock data recovery circuit includes a phase detector circuit, a majority voter circuit, and a phase shift circuit. The phase detector circuit is operable to compare a phase of a periodic signal to a phase of a data signal to generate a phase error signal. The majority voter circuit includes a shift register circuit. The shift register circuit is operable to generate an output signal based on the phase error signal. The majority voter circuit is operable to generate a majority vote of the phase error signal based on the output signal of the shift register circuit. The phase shift circuit is operable to set the phase of the periodic signal based on the majority vote generated by the majority voter circuit.

Abstract: A wireless communications device may include a portable housing and a temperature-compensated clock circuit carried by the portable housing. The device may further include a wireless receiver carried by the portable housing for receiving timing signals, when available, from a wireless network, and a satellite positioning clock circuit carried by the portable housing. A clock correction circuit may be carried by the portable housing for correcting the temperature-compensated clock circuit based upon timing signals from the wireless network when available, and storing historical correction values for corresponding temperatures. The clock correction circuit may also correct the temperature-compensated clock circuit based upon the stored historical correction values when timing signals are unavailable from the wireless network, and correct the satellite positioning clock based upon the temperature-compensated clock circuit.

Abstract: Precision Timing Protocol (PTP) related functions for use in packet communications carried in part by a microwave communications link include setting of time of day values across the microwave link and providing transparent clock functions. The PTP functions may be used for synchronizing radio base stations in a cellular network. The transparent clock can bridge Ethernet switches associated with microwave stations providing the microwave communications link.

Abstract: Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system.

Abstract: An apparatus and method for detecting and analyzing spikes in network jitter and the estimation of a jitter buffer target size is disclosed. Detected spikes may be classified as jump spikes or slope spikes, and a clipped size of detected spikes may be used in the estimation of the jitter buffer target. Network characteristics and conditions may also be used in the estimation of the jitter buffer target size. Samples may be modified during playback adaptation to improve audio quality and maintain low delay of a receive chain.

Abstract: A method and system in which a Digital Subscriber Line Access Multiplexer (DSLAM) that is part of a DSL (Digital Subscriber Line) system is able to provide synchronous services to end user equipment connected to the DSLAM via a DSL link and Customer Premises Equipment (CPE). A sniffer device having direct or indirect access to a Primary Reference Clock (PRC) of the DSL system calculates the phase difference between the PRC and the DSLAM's Local Timing Reference (LTR). The phase difference is sent to the CPEs requiring accurate reference clock frequency. The CPEs are able to derive the PRC from the phase difference information transmitted by the sniffer device thus enabling synchronous end user equipment operation.

Abstract: A method for frame number synchronization in a wireless communication network may be implemented by a base station. The method may include determining a current time from a timing source that is common to multiple other base stations. The method may also include determining a time offset between the current time and a reference time, wherein the base station and the multiple other base stations use the same reference time for determining the time offset. The method may also include determining a current frame number based on the time offset.

Abstract: The present invention relates to a method and a user equipment arranged to communicate with at least a second user equipment in a VoIP service data transmission in a wireless communication system using a VoIP service, provided by an application server. The method comprises the steps of: receiving transmissions in form of a media stream from the at least one second user equipment; storing the data of the media stream; detecting whether an interruption of said transmissions having at least a minimum length has occurred during the VoIP service data transmission or expecting that an interruption of said transmissions having at least a minimum length will occur during the VoIP service data transmission, and if such an interruption is detected or expected, using a non-normative playout rate of the data at playout, thereby obtaining a more efficient interactivity in the user communication.

Abstract: A receiver and reception method for estimating a channel in an Orthogonal Frequency Division Multiple Access (OFDMA) system is provided. The receiver includes a delay estimator for estimating, from a signal received from a transmitter through multipaths, at least one of an average time delay of the multipaths and a time delay of one of the multipaths having a maximum power among the multipaths, a rotator for circular-rotating the received signal using the estimated delay, and a channel estimator for estimating a channel impulse response of the circular-rotated signal.

Abstract: A packet flow side channel encoder and decoder embeds and extracts a side channel communication in an overt communication data stream transmitted over a network. The encoder selects more than one group of related packets being transmitted on the network, relates a packet of one group to a packet of another group to form a pair of packets; and delays the timing of at least one packet from each pair of packets The decoder determines inter-packet delays that are the difference in timing between two packets in a pair of packets; determines at least one inter-packet delay difference between two or more determined inter-packet delays; and extracts a bit using the at least one interpacket delay difference.

Abstract: In one embodiment, receiving an Ethernet signal over a channel, the Ethernet signal comprising a preamble frame, an idle frame, and a data frame, the preamble frame comprising one or more preamble codes; synchronizing to the Ethernet signal based on the preamble frame; replicating the one or more preamble codes; and training a decision feedback equalizer (DFE) based on the one or more replicated codes, the training enabling the DFE to use decision values at the DFE output to track channel variations.

Abstract: The data processing unit (15) for a receiver of signals carrying information (1) includes a clock and data recovery circuit (16) on the basis of a data signal (DOUT), and a processor circuit (17) connected to the clock and data recovery circuit. The clock and data recovery circuit is clocked by a local clock signal (CLK) and includes a numerical phase lock loop, in which a numerically controlled oscillator (25) is arranged. This numerically controlled oscillator generates an in-phase pulse signal (IP) and a quadrature pulse signal (QP) at output. The frequency and phase of the pulse signals IP and QP are adapted on the basis of the received data signal (DOUT). The processor circuit is arranged to calculate over time the mean and variance of the numerical input signal (NCOIN) of the numerically controlled oscillator (25), so as to determine the coherence of the data signal if the calculated mean and variance are below a predefined coherence threshold.

Abstract: A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data.

Abstract: A CAN communication system of the present invention includes: a transmission apparatus that transmits transmission data instead of the bit data protocol, the transmission data being data in which a stuff bit having an inverted value of the same logical value has been inserted next to the predetermined number of continuous bits having the same logical value in the bit data; a reception apparatus that synchronizes transmission and reception of the transmission data to and from the transmission apparatus according to detection of an edge from the second logical value to the first logical value in the transmission data transmitted from the transmission apparatus. The transmission apparatus has a transmission control unit that rewrites to the first logical value any of the predetermined number ?1 of bits continuing from the predetermined number of continuous bits having the first logical value in the bit data.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract: Both a first profile that represents relationships between delay times premeasured over transmission paths and occurrence frequencies of the delay times and measurement periods of time for which the delay times over the transmission paths are measured are stored such that the first profile and the measurement period of time are correlated; a measurement period of time correlated with the first profile is obtained from the storage section if a second profile that represents relationships between delay times measured to obtain the measurement period of time and occurrence frequencies of the delay times is the same profile as the first profile; the delay times over the transmission paths are measured; and a mean value of the delay times measured for the measurement period of time is computed.

Abstract: A decoder arrangement comprising a receiver input for parameters of frame-based coded signals and a decoder arranged to provide frames of decoded audio signals based on the parameters. The receiver input and/or the decoder is arranged to establish a time difference between the occasion when parameters of a first frame is available at the receiver input and the occasion when a decoded audio signal of the first frame is available at an output of the decoder, which time difference corresponds to at least one frame. A postfilter is connected to the output of the decoder and to the receiver input. The postfilter is arranged to provide a filtering of the frames of decoded audio signals into an output signal in response to parameters of a respective subsequent frame.

Abstract: In one embodiment, a battery-operated communication device “quick-samples” a frequency hopping sequence at a periodic rate corresponding to a substantially low duty cycle, and is discovered by (e.g., attached to) a main-powered communication device. During a scheduled sample, the main-powered communication device transmits a control packet to be received by the battery-operated communication device, the control packet containing timing information and transmitted to account for worst-case clock drift error between the two devices. The battery-operated communication device responds to the control packet with a link-layer acknowledgment containing timing information from the battery-operated communication device. Accordingly, the two devices may re-synchronize their timing based on the timing information in the control packet and acknowledgment, respectively.

Abstract: An integrated circuit having a corresponding method comprises one or more ports to transmit and receive packets of first data; and a forwarding engine to transfer the packets of the first data between the ports; wherein at least one of the ports comprises a packet generator to originate a first packet of the first data comprising second data representing a time of transmission of the first packet of the first data, a network transmit interface to transmit the first packet of the first data, and a network receive interface to receive a second packet of the first data transmitted in reply to the first packet of the first data; and a controller to calculate a network delay based on the second data representing the time of transmission of the first packet of the first data and the second packet of the first data.

Abstract: Embodiments of a dual-master mode Ethernet node are provided herein. The dual-master mode Ethernet node includes a first multiplexer configured to select between a local oscillator signal and a primary reference source (PRS) signal to provide a reference clock signal, a digital phase-locked loop (DPLL) configured to generate a master clock signal based on the reference clock signal, a phase rotator configured to rotate a phase of the master clock signal based on a frequency error between the master clock signal and an extracted clock signal to generate a slave clock signal, and a second multiplexer configured to select between the master clock signal and the slave clock signal to provide a transmit clock signal. The dual-master mode Ethernet node can dynamically generate the transmit clock based on either the extracted clock or the PRS without re-performing the auto-negotiation process.

Abstract: A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.

Abstract: A method of operation in a receive circuit is disclosed. The method comprises entering an initialization mode followed by receiving training data from a lossy signaling path. The training data originates from a transmit circuit. The received training data is sampled and minimax transmit equalizer coefficients are generated based on the sampled data. The minimax transmit equalizer coefficients are then transmitted back to the transmit circuit. The initialization mode is exited and an operating mode initiated, where transmit data precoded by the minimax transmit equalizer coefficients is received.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for an adaptive subscriber buffering policy with persistent delay detection for live audio streams. In one aspect, a method includes decoding frames of multimedia data received from a first network; storing the decoded frames of multimedia data in a buffer; monitoring the buffer to determine a level of delay; and providing an output, based on the monitoring of the buffer, to cause a reduction in the level of delay during retrieval and encoding of the stored frames of multimedia data.

Abstract: In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.

Abstract: Provided is a media player comprising a connector to which a cable for transmitting a media signal from an external source is connected, and a user manipulator, the media player including a signal processor for processing the media signal transmitted through the cable; a UI generator for generating a setting menu for setting characteristics of the cable; and a controller for controlling the signal processor to process the media signal on the basis of the set characteristics of the cable inputted through the setting menu by the user manipulator. The media player and a control method thereof provides a user interface (UI) allowing a user to input information about cable characteristics, and process a signal according to the cable characteristics inputted by a user.

Abstract: Systems and methods are disclosed for direct passive monitoring of packet delay variation and time error in network packet communications. Packets traversing between slave and master clocks are monitored to provide direct results of the actual conditions without the need to rely upon inference determinations. Certain embodiments provide tap configurations to monitor packet flows, while certain other embodiments provide in-line configurations to monitor packet flows. Certain further embodiments provide multiple monitoring devices that can be used for passive monitoring purposes, such as passive monitoring to test boundary clock. These multiple monitoring devices can be configured to be within a single or different test instruments. Other variations are also described.

Abstract: As a digitized representation of an intermediate frequency television signal moves through a demodulator it undergoes a number of processes, including conversion from an analog signal to a digitized data, digital signal processing of the digitized data, and the like. The rate at which the digitized data moves through the digital signal processor of the demodulator for processing is referred to as the data rate of the DSP. The demodulator can vary the data rate based on a selected television channel, thereby reducing the level of interference at the demodulator resulting from noise.

Abstract: A technique includes determining a first difference between a time that a first network element of a seismic acquisition network receives a first frame pulse from a second network element of the seismic acquisition network and a time that the first network element transmits a second frame pulse to the second network element. The technique includes determining a second difference between a time that the second network element receives the second frame pulse and a time that the second network element transmits the first frame pulse. The technique includes determining a transmission delay between the first and second network elements based on the first and second time differences.

Abstract: A method for automatic management of a timestamp-based synchronization protocol within a packet-based network to synchronize a slave within a synchronization topology including a plurality of masters, the slave clock being locked to a master clock at an initialization time, said method comprising an assessment step of end-to-end packet delay variation on the basis of the slave clock accuracy, over a plurality of (slave, path, master) combinations, each path linking the slave to a master.

Abstract: A method for receiving a signal having a succession of symbols, transmitted by a digital modulation, each symbol transmitted having a phase and an amplitude belonging to a set of values in finite number, the method includes evaluating a phase error (PHE) on a received symbol (S), resulting from a signal transmission noise, correcting the phase of the received symbol according to the phase error evaluated, demodulating the symbol corrected in phase, and modeling the transmission noise by a Gaussian component not correlated with the signal received and defined by a power and an interference component defined by an amplitude and which phase is substantially uniformly distributed, the phase error of the received symbol evaluated on the basis of the power of Gaussian component and the amplitude of the interference component.

Abstract: A timing recovery controller capable of performing timing recovery for a data sequence at twice a symbol rate includes a sampler, a timing base device, a timing error detector and a timing lock detector. The timing error detector includes a first delay unit and a second delay unit, for delaying a data sequence to output a first delay data sequence and a second delay data sequence, respectively, and a timing error calculating module, for generating a timing error value, to adjust a time base. The timing lock detector includes a third delay unit, for delaying the data sequence to output a third delay data sequence, and a timing lock determination module, for generating a timing lock determination result.

Abstract: A streaming communication device accurately estimates a packet which will be lost in the future. A streaming communication device which transmits or receives a stream via a router over a packet-switched network includes: accumulating unit configured to accumulate a one-way delay that is a time period between transmission and reception of a packet which includes a small segment of the stream; a detecting unit configured to detect a sign of a packet loss by identifying a tendency toward an increase in the one-way delay accumulated in the accumulating unit; and an estimating unit configured to estimate, when the sign is detected, a loss packet from a degree of the increase in the one-way delay accumulated in the accumulating unit, the loss packet being a packet which will be lost.

Abstract: A packetized streaming media delivery network carries many “streams” of differing media content. They often are from multiple sources and of different media types. The invention consists of a scalable hardware and/or software computing element resolving the network traffic into its individual streams for focused, simultaneous, and continuous real-time monitoring and analysis. The monitoring and analysis consists of delay factor and media loss rate which measure the cumulative jitter of the streaming media within the delivery network and the condition of the media payload. These measurements form a powerful picture of network problem awareness and resolution. The delay factor objectively indicates the contribution of the network devices in the streams' path, allowing for both problem prediction and indication. In one example, tapping a packetized network at various locations allows for correlation of the same-stream performance at various network points to pinpoint the source(s) of the impairment(s).

Abstract: “A process of scheduling stream packets for output from a multiplexing network device involves prioritizing the output of packets first according to stream priority, and within a particular priority, by stream ID.

Abstract: A method of operation of a network system including a network line terminal coupled to a slave network unit and a master network unit over a first network includes: calculating a master round trip time between the network line terminal and the master network unit; sending a master message to the slave network unit, the master message having the master round trip time and a master local time; and calculating a slave local time based on the master round trip time and the master local time.

Abstract: A method of compensating for jitter in a packet stream is described. The method comprises placing undecoded frames extracted from packets in the packet stream into a jitter buffer while decoding frames from the jitter buffer and placing the decoded frames into a sample buffer at a rate determined using an average playout delay. The average playout delay is the running average of the playout delay calculated for each packet as each packet becomes available. The playout delay for each packet is the sum of a sample buffer delay and a jitter buffer delay. As each packet is received, the average playout delay is adjusted based on a comparison of the playout delay associated with the received packet to the current average playout delay.

Abstract: A signal multiplexing device includes a selector (1) that selects one of input data (4) and a complementary signal (16), a clock recovery circuit (30a) that adjusts the phase of a recovered clock (7) to the timing of the output signal of the selector (1), and a flip-flop circuit (3) that performs identification/recovery of the output signal of the selector (1) based on the recovered clock (7). The frequency of the complementary signal (16) is an integral submultiple of the frequency of the recovered clock (7). The selector (1) selects the complementary signal (16) during part of the no-signal period of the input data (4).

Abstract: A system and method for discarding or inserting audio frames in a jitter buffer is described. The system and method provides improved audio quality as compared to conventional jitter buffer management systems. In one embodiment, buffer control logic determines whether to discard audio frames to be stored in a jitter buffer or to insert audio frames among audio frames to be output from a jitter buffer based not only on the number of audio frames currently stored in the jitter buffer but also based on the power of the current audio frame to be stored in or output from the jitter buffer. The system and method is generally applicable to any wireless or wired communication system in which audio signals are transmitted between entities operating in different clock domains.

Abstract: A communications network includes multiple distributed nodes that are coupled by a circuit-switched network. To improve efficiency, a plurality of the nodes are associated with a single source synchronization block that injects timing messages over circuits in the circuit-switched network to the plurality of nodes. Each of the plurality of nodes is associated with a timing extraction and recovery block that extracts information from the timing messages injected by the source synchronization block to synchronize a local clock in each node to the frequency and phase of a clock received by the source synchronization block.

Abstract: A technique for characterizing a communications interface includes determining a voltage margin and a timing margin of the interface based on data sampled by a sampling device of a receiver of the interface. In at least one embodiment of the invention, a method for determining margin associated with a receiver circuit of an integrated circuit includes periodically sampling a signal over a time period by a receiver sampling circuit of the receiver circuit to generate a sampled version of the signal. The method includes incrementally varying a value of the parameter associated with the signal. The varying of the parameter is through a range of values of the parameter over the time period. The method includes determining a margin value of the receiver circuit associated with the parameter based, at least in part, on the sampled version of the signal.

Abstract: According to one embodiment, a frequency offset compensation apparatus includes a first estimation unit, a second estimation unit, a setting unit, a synthesis unit and a compensation unit. The first estimation unit estimates a first rotation. The second estimation unit estimates a second rotation. The setting unit sets a weighting factor for the second rotation to a first value if a received power is less than a threshold value, and sets the weighting factor for the rotation to a second value being smaller than the first value if the received power is not less than the threshold value. The synthesis unit calculates a compensation value. The compensation unit compensates for a frequency offset.

Abstract: A mobile station establishes UL synchronization by the use of downlink preamble messages, and by monitoring timing drift within the downlink signalling and by updating the UL synchronization value responsive to the magnitude of the timing drift exceeding a threshold value. Tx power values can also be updated as a function of the updated synchronization value.

Abstract: Clock phase errors are detected and adjusted in a network with loop back connections for clock signals. In one embodiment, a method is performed in a ring network with slave clock nodes. A timing packet is sent from the master clock node to a first slave clock node of the ring. A timing packet is received from a last slave clock node of the ring. A phase alignment offset is determined by comparing a recovered time from the received timing packet with the time of the master clock node local clock and a phase correction value is determined for the slave clock nodes based on the determined phase alignment offset. A phase correction packet including the phase correction value is then sent from the master clock node to at least one of the slave clock nodes.

Abstract: A first PHY may be coupled to a second PHY via a network link. The first PHY may transition from a role of timing master for the network link to a role of timing slave for the network link. During a first time interval subsequent to the transition, the PHYs may communicate half-duplex over the link while the first PHY synchronizes to a transmit clock of the second PHY. During a second time interval, the PHYs may communicate full-duplex while the second Ethernet PHY synchronizes to a transmit clock of the first PHY. Also during the second time interval, the first PHY may determine that the first PHY and the second PHY are synchronized. Subsequent to the determination, the PHYs may begin full-duplex communication of data on the network link.

Abstract: In a field control system in which a plurality of field equipments that are operated in a previously set schedule and constitute a control loop perform a packet communication via a network, there is provided a configurator for collecting measured result packets to which a time stamp of each field equipment is affixed respectively, grasping at least any one of communication times between respective field equipments based on the time stamp, and adjusting operation schedules of respective field equipments in response to the communication times.

Abstract: A method includes receiving at a receiver a voice signal in the form of a sequence of data packets, and using an automatic level control (ALC) component of the receiver to detect that one of the received packets is a silence packet or a noise packet. The method further includes receiving at a jitter delay control circuit from the ALC component a signal or signals to indicate that the one of the received packets is a silence or a noise packet, and dropping the one of the received packets in response to the signal or signals received from the ALC component. The ALC component includes a gain adjustment block and a level estimation and active voice detector block. The gain adjustment block is controlled by the level estimation and active voice detector block to adjust a gain applied by the gain adjustment block to an audio signal.

Abstract: Time synchronization between a control center and transmitters in a single frequency network is provided by generating and receiving a first reference time signal with a high time and frequency accuracy in a short and long time horizon and a second reference time signal supplied to the control center with a low time and frequency accuracy in the short time horizon and a high time and frequency accuracy in the long time horizon. A transport data stream is generated and supplied to the transmitters with a time-variable data rate through the control center corresponding to a frequency of the second reference time signal. Time displacement of the transport data stream received from the control center is performed by a respective transmitter until the data packets of the transport data stream each containing a transmission time are transmitted at a correct transmission time.

Abstract: According to a first aspect, the invention proposes a method for processing a transport stream (TS) received as an input transport stream in a processing device (SDR), the transport stream comprising a plurality of elementary streams (ES), each elementary stream (ES) being a set of transport stream packets having the same Packet IDentifier (PID), at least one of these elementary streams being time-sliced so as to be sent in bursts, timing information indicating within a burst the time to the beginning of the next burst, characterized in that it comprises the steps of: applying a filtering operation to the input transport stream so as to filter out from the input transport stream part or all of one or more time-sliced elementary streams; modifying the bursts scheduling of the input transport stream so as to generate a DVB-H compliant output transport stream from the filtered input transport stream.

Abstract: A mobile station performing a voice communication by using a radio resource, including a determination unit configured to determine whether an inputted packet is in a talk-spurt state or in a silent state; a message generating unit configured to generate a resource release request, when the determination unit determines that the inputted packet is in the silent state; and a transmitting unit configured to transmit the resource release request to a radio base station.

Abstract: A network entity and computer program for detecting occurrence of transmission resynchronizations in a network carrying packets subject to variable delays, and adaptively varying the play out time of data packets. The method may include that the packets are received at a network entity and forwarded by delaying them by a jitter protection time, and determining for a predetermined time period a set of arrival time jitter values. A peak to peak value may be determined indicating the largest difference among the values included in the determined set of arrival time jitter values and detecting an out of range condition. The peak to peak value may be compared with the jitter protection time when the out of range condition is detected and detecting that a resynchronization occurred on the basis of the comparing.