Abstract: A phase selector capable of tolerating jitters is applied in a clock and data recovery circuit. The phase selector includes a comparing module, a weighting circuit, and a predictor. The comparing module compares a phase-detecting signal and a phase-selecting signal corresponding to the last cycle so as to generate an error signal. The weighting circuit calculates a weighting error signal according to the error signal and a weighting parameter. The phase predictor compares the weighting error signal and predetermined threshold values so as to generate the phase-selecting signal corresponding to the present cycle. When the received input data stream of the clock and data recovery circuit has a small jitter, the phase selector rapidly locks the phase so as to generate the correct phase-selecting signal. When the received input data stream of the clock and data recovery circuit has a large jitter, the phase selector stably generates the phase-selecting signal.

Abstract: A method for receiving a signal having a succession of symbols, transmitted by a digital modulation, each symbol transmitted having a phase and an amplitude belonging to a set of values in finite number, the method includes evaluating a phase error (PHE) on a received symbol (S), resulting from a signal transmission noise, correcting the phase of the received symbol according to the phase error evaluated, demodulating the symbol corrected in phase, and modeling the transmission noise by a Gaussian component not correlated with the signal received and defined by a power and an interference component defined by an amplitude and which phase is substantially uniformly distributed, the phase error of the received symbol evaluated on the basis of the power of Gaussian component and the amplitude of the interference component.

Abstract: Systems and methods that facilitate on-chip testing are provided. An integrated circuit can include a transmitter configured to transmit a communications signal via a communications channel. The integrated circuit can also include a receiver configured to receive the communications signal via the communications channel. A jitter creation module also can form part of the integrated circuit and can introduce jitter into the system thereby allowing for on-chip jitter testing. The jitter creation module can form either part of the transmitter or receiver and can introduce the jitter by phase interpolation.

Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

Abstract: Techniques for controlling diversity beamforming antenna array is disclosed. One aspect of the techniques is to utilize low-power and low area circuits to achieve combining gains, mitigate the effects of multipath fading, provide spatial suppression and diversity gains to a single input receiver. The device is radiofrequency transparent yet provides antenna gain by selective three G and four G code acquisition and tracking of a desired downlink channel.

Abstract: Systems and methods for controlling transmission of signals are described. A camera-side modem is configured to receive two signals from a video camera and to extract a received passband signal from a transmission line. A detector in the camera-side modem generates an enable signal when the received passband signal is identified. The enable signal is used to control transmission of at least one of the baseband video signal and the passband video signal. The passband signal may be identified by an estimate of mean square error in a quadrature amplitude demodulator, a measurement of reliability provided by a constellation detector, a measurement of reliability based on a sequence of frame synchronizations and/or an estimate of mean square error in an equalizer. The detector may monitor a gain factor in an automatic gain control module of the camera-side modem and/or a magnitude of the received passband signal.

Abstract: The present invention provides a method for generating random jitter test patterns by generating a sequence of maximum-size asynchronous packets according to the P1394b standard and transmitting the sequence to the device under test. The present invention provides a method for generating jitter test patterns by disabling the transmitter data scrambler of the second device; clearing the port_error register of the device under test; and sending a test pattern to said device under test. The present invention provides for a method for generating supply noise test patterns comprising: transmitting a test pattern to the DUT comprising a maximum length asynchronous packet containing alternate 0016 and FF16 bytes.

Abstract: A method for compensating the frequency dependent phase imbalance in a receiver is provided. The receiver downconverts an input signal to generate the signal r(t). The signal r(t) has an in-phase component rI(t) and a quadrature component rQ(t). A first test signal with a first carrier frequency is applied as the input signal of the receiver to obtain a first phase imbalance I. A second test signal with a second carrier frequency is applying as the input signal of the receiver to obtain a second phase imbalance. An IQ delay mismatch ?t of the receiver according to the difference of the second and the first phase imbalances and the difference of the second and the first carrier frequencies is obtained. The in-phase component rI(t) and the quadrature component rQ(t) of the signal r(t) corresponding to other input signal is compensated according to the obtained IQ delay mismatch ?t.

Abstract: An apparatus for correcting a phase error is provided. The apparatus includes an error estimating module and a correcting module. The error estimating module receives a phase-shift keying signal, and calculates a phase error according to the phase-shift keying signal, a plurality of known candidate signals and Bayesian estimation. The correcting module corrects the phase-shift keying signal according to the phase error.

Abstract: A method and a measuring device for synchronizing measuring channel assemblies are provided. A reference signal is produced by a reference signal source. The reference signal is supplied to the individual measuring channel assemblies of the measuring device. A clock signal generator is used to produce a clock signal at a low frequency, the clock signal generator being connected to each measuring channel assembly by a respective connecting line of the same length. The clock signal is supplied through a phase corrector element for the purpose of correcting the phase of the reference signal in each measuring channel assembly to the phase of the clock signal.

Abstract: A method for performing delay locked looping upon a received signal which reduces the asymmetry of auto-correlation function resulting from sampling is provided. The received signal is a spread spectrum code signal, and the method includes: generating a plurality of replica spread spectrum code signals according to an estimated code phase delay and phase spacing, the replica spread spectrum code signals having phases respectively different from the phase of the received signal; calculating a spread spectrum code error statistics signal according to the replica spread spectrum code signals and the received signal; and adjusting the estimated code phase delay according to the spread spectrum code error statistics signal and a phase difference between a sampled point of at least one replica spread spectrum code signal and a corresponding signal transition point.

Abstract: This disclosure relates systems and methods for a high bandwidth modulation and transmission of communication signals.

Abstract: A radio system having multi-standard mixed mode radios is described. The mixed mode radios are used to support combining of digital baseband from a first and a second radio equipment controller. A primary clock associated with the first radio equipment controller and a secondary clock associated with the second radio equipment controller is provided. The quality of the primary clock is evaluated and the primary clock is referenced to the first radio equipment controller if the clock is determined to have appropriate quality factors. The quality of the secondary clock is then evaluated and the secondary clock is referenced to the second radio equipment controller if the secondary clock is determined to have appropriate quality factors. The second radio equipment controller is then referenced to the primary clock once the primary and secondary clocks are aligned.

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract: A transmitter-only integrated circuit (IC) chip for performing an external loopback test without an additional receive pin in a chip and an external loopback test method include drivers, mounted on the transmitter-only IC chip, for transmitting data through transmit pads that are installed in correspondence to a plurality of channels; and a loopback test circuit for receiving data as external loopback data through one of the transmit pads set as a receive pad for a test, the data being transmitted through one of the remaining transmit pads, and then comparing the received external loopback data with original transmit data.

Abstract: Embodiments of a system for determining and optimizing the performance a signaling system are described. During operation, the system captures or measures a single-bit response (SBR) for the signaling system. Next, the system constructs an idealized inter-symbol-interference-free (ISI-free) SBR for the signaling system which is substantially free of inter-symbol-interference (ISI). The system then calculates an ISI-residual from the captured SBR and the idealized ISI-free SBR. Next, the system constructs a calibration bit pattern for the signaling system that is based substantially on the ISI-residual. Finally, the system uses the calibration bit pattern to calibrate, optimize and determine an aspect of the performance of the signaling system.

Abstract: A communication system includes a first communication device and a second communication device that performs power line communication with the first communication device via an electric power line, wherein the first communication device transmits an initial packet signal added with an error detection code in each zero crossing period including zero crossing timing while changing transmission timing within the zero crossing period. The second communication device specifies optimum communication timing out of a plurality of pieces of transmission timing within the zero crossing periods based on a result of error detection on each initial packet signal, and transmits an ACK signal including timing information on the optimum communication timing. Then, the first communication device transmits a data packet signal in the optimum communication timing within the zero crossing period, which is specified based on the timing information.

Abstract: Disclosed is an apparatus and a method for multiport amplification configured to amplify a signal input to a multi-input port and output the amplified signal to a multi-output port in order to normally transmit/receive a signal in a communication system. The apparatus and the method are configured to: amplify an input signal input through a multi-input port, detect a phase error and an amplitude error of the input signal, and then calculate a phase error value and an amplitude error value of the input signal; correct the phase error and the amplitude error of the input signal through the phase error value and the amplitude error value of the input signal; and then amplify the input signal of which the phase error and the amplitude error are corrected, and output the input signal to a multi-output port.

Abstract: A wireless transmitter is disclosed that is capable of pre-compensating for oscillator phase noise. In the transmitter, an undesired phase noise being generated by a voltage-controlled oscillator can be detected by comparing the output of the voltage-controlled oscillator to a reference oscillator output. The phase can then be detected by calculating a desired number of zero crossings over a given time period, and comparing this value to an actual number of zero crossings detected in the signal generated by the voltage-controlled oscillator over the same period. From this, the phase component can be determined and digitally pre-compensated in a data signal.

Abstract: Apparatuses, methods and systems of receive signal detection of a multi-carrier signal are disclosed. One method includes receiving a multi-carrier signal, determining a characteristic of each sub-carrier of the multi-carrier signal, and selecting a one of a plurality of receive signal detection techniques for each sub-carrier of the multi-carrier signal based on the determined characteristic of the sub-carrier.

Abstract: According to one embodiment, a channel phase estimation apparatus includes a phase memory, subtractor, multiplier, and adder. The phase memory is configured to store a first phase estimation value up to a (k?1)-th (for k=1, 2, . . . , K) symbol. The subtractor is configured to calculate a difference value between a phase value of one carrier of a k-th symbol and the first phase estimation value. The multiplier is configured to multiply the difference value by a weight. The adder is configured to add a value output from the multiplier and the first phase estimation value to output a second phase estimation value up to the k-th symbol.

Abstract: In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained 1T resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with 1T resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.

Abstract: Transmitter waveform dispersion penalty (“TWDP”) is decreased in a transmitter. A binary data signal is received for transmission over a channel that exhibits TWDP. The data signal is shifted less than a full clock cycle to generate at least one post cursor signal. The post cursor signal is subtracted from the data signal to generate a transmitter output data signal for transmission over the channel. In addition to decreasing TWDP, data dependent jitter is also reduced for data transmission across a channel that exhibits a multi-pole transmission characteristic. A main data signal and at least one cursor signal, which is shifted at least a portion of a clock period from the main data signal, is generated. The cursor signal is filtered to filter out effects based on the second pole of the multi-pole transmission characteristic. The main data signal is subtracted from the filtered cursor signal to generate the transmitter output data signal.

Abstract: A receiver may comprise: a symbol receiver configured to receive a first modulated symbol at a first resolution and thereafter a second modulated symbol at a second resolution greater than the first resolution; an output path coupled to the symbol receiver and configured to forward the first modulated symbol; a decision device coupled to the symbol receiver and configured to determine a most probable symbol represented by the first modulated symbol; a phase detector coupled to the decision device and configured to compare the first modulated symbol and the most probable symbol to generate a phase error value; and a phase modifier coupled to the decision device and configured to determine a phase correction value based on the phase error value and to adjust the phase of the second modulated symbol based on the phase correction value.

Abstract: The present disclosure is directed at a method and apparatus for generating a metric for use in any one or more of lock detection, SNR estimation, and modulation classification. To generate the metric, an input angle in the form of a symbol phase or a difference in symbol phases is used to evaluate a base function. The base function relates possible metrics to possible input angles using a triangle wave having its maxima or minima at ideal input angles, and the other of its maxima or minima at angles midway the ideal input angles. Described are embodiments that are one or more of non-data aided; that may be implemented relatively efficiently in hardware; that can function using one sample/symbol; that can achieve relatively good detection certainty using relatively few estimates; and that can be used to implement modulation classifiers, lock detectors, and SNR estimators that are resilient to imperfections in automatic gain control.

Abstract: A communication terminal includes first and second transmitters, which are coupled to produce respective first and second Radio Frequency (RF) signals that are phase-shifted with respect to one another by a beamforming phase offset, and to transmit the RF signals toward a remote communication terminal. The terminal includes a reception subsystem including first and second receivers and a phase correction unit. The first and second receivers are respectively coupled to receive third and fourth RF signals from the remote communication terminal. The phase correction unit is coupled to produce, responsively to the third and fourth RF signals, a phase correction for correcting an error component in the beamforming phase offset.

Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.

Abstract: Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system.

Abstract: The present invention relates to a receiver being arranged to estimate a received signal. The receiver comprises demodulator means arranged to demodulate received signal data symbols of a higher constellation order such that a demodulated signal is obtained. The demodulator means comprises a main carrier recovery Phase-Locked Loop 9 arranged to demodulate 17 the data and pilot symbols. The demodulator means further comprises phase calculation means 5 arranged to provide 16 phase information from the pilot symbols of lower constellation order to the main carrier recovery PLL 9. The invention is particularly characterized in that the phase calculation means further comprises a pilot PLL 18 arranged to extract 15 the phase information from the pilot symbols. The invention also relates to a method in the receiver for estimating the received signal.

Abstract: A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.

Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.

Abstract: An IQ imbalance correction method includes transmitting a plurality of pairs of RF training signals in installments by pairing RF training signals symmetric with respect to a center frequency on a frequency axis; setting a reception local frequency to change to a frequency that is suitable to receive, via an internal path, each of the plurality of pairs of RF training signals transmitted in installments, and suitable to convert the each of the plurality of pairs of RF training signals into IF training signals; and performing quadrature demodulation on the IF training signals, respectively, in a digital circuit area to generate BB training signals.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: Receiving a modulated carrier signal that is modulated using a reference signal, wherein an acquisition by a digitizer is synced to the reference signal such that the modulated carrier signal has known timing with respect to a start of an acquisition within the digitizer. Further including routing the modulated carrier signal through a receiver system to generate a processed signal, receiving the processed signal at the digitizer, digitizing the processed signal at the digitizer, and determining a delay of the modulated carrier signal routed through the receiver system based on the timing of the processed signal.

Abstract: To provide a signal generator, a signal generating system, and a signal generating method capable of repeatedly generating an arbitrary waveform and making the phases of the head and tail of the generated waveform continuous with each other, without changing the frequency of the waveform. A signal generator (10, 11, 12) includes phase shift means (30) that receives waveform data which is repeatedly output n times, shifts the phase of each sample data item in an n-th waveform data item by a phase shift amount ?n corresponding to the number of times n the waveform data is repeatedly output, and outputs the waveform data to D/A conversion means.

Abstract: Systems and methods that provide clock jitter compensation architectures that improve the performance of direct radio frequency (RF) receivers by injecting a calibration tone into the received radio frequency (RF) signals in order to help identify and then compensate for the clock jitter noise. After injecting the tone, the jitter noise going through the direct RF bandpass sampling receiver is estimated using a narrow bandwidth filter, and the received signals are further processed and demodulated depending on the Nyquist zone of the received signal. The relative modulation factor for the modulation is computed and then applied to the Nyquist zone to de jitter that particular Nyquist zone.

Abstract: A method for estimating timing in a wireless communication comprises the steps of receiving a plurality of symbol bursts corresponding to a plurality of time slots and selecting a subset of symbols from a first symbol burst of the plurality of symbol bursts. The subset comprises a first midamble symbol. The method further comprises the steps of calculating, for each symbol in the subset, a corresponding midamble estimation error, and determining the lowest calculated midamble estimation error to determine a timing for the first symbol burst. The method further comprises the steps of processing the first symbol burst utilizing the timing determined for the first symbol burst, and processing a second symbol burst of the plurality of symbol bursts utilizing the timing determined for the first symbol burst.

Abstract: An integrated circuit (“IC”) includes circuitry for use in testing a serial data signal. One such IC includes circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. One such IC also includes circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. Such an IC provides output signals indicative of results of its operations. One such IC operates in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

Abstract: A synchronization processing apparatus includes: a jitter amount calculating section that calculates a jitter amount on the basis of a synchronization packet including time information; and a frequency synchronization determining section that calculates an accumulation value of the jitter amounts, and determines whether frequency synchronization is present from the accumulation value.

Abstract: Systems and methods are disclosed for detecting temporary high level impairments, such as noise or interference, for example, in a communications channel, and subsequently, mitigating the deleterious effects of the dynamic impairments. In one embodiment, the method not only performs dynamic characterization of channel fidelity against impairments, but also uses this dynamic characterization of the channel fidelity to adapt the receiver processing and to affect an improvement in the performance of the receiver. For example, in this embodiment, the method increases the accuracy of the estimation of the transmitted information, or similarly, increases the probability of making the correct estimates of the transmitted information, even in the presence of temporary severe levels of impairment. The channel fidelity history may also be stored and catalogued for use in, for example, future optimization of the transmit waveform.

Abstract: A receiver circuit detects an eye margin within a differential signal having a true component and a complement component. A transmitter circuit adjusts a phase between the true component and the complement component of the differential signal, based on the eye margin, to improve the eye margin. Improving the eye margin results from a reduction in common mode noise within the differential signal.

Abstract: Modern digital signals include framing. A known sequence of transmission symbols (Unique Word (UW)) included in the transmitted signal may be used by a receiver for framing synchronization. A receiver configured to receive such a signal may be configured to detect the UW even when the signal is received with some frequency uncertainty (e.g. offset or error). A method is presented for fast acquisition of symbol and/or frame timing of a signal, including in the presence of frequency uncertainty. In some embodiments, the presented method may be used for determining a frequency offset of the received signal and a location of a unique word (UW) within a frame of the received signal, wherein said determining is based on a two-dimensional search map.

Abstract: An integrated circuit (IC) having a radio receiver configured to perform a jitter self-test is disclosed. In one embodiment, an IC includes a radio receiver and a pulse generator. The pulse generator is configured to generate a pulse train based on a first periodic signal received from the radio receiver. The radio receiver is configured to use the pulse train to determine an amount of phase noise generated by a local oscillator of the radio receiver. The pulse generator and the radio receiver are implemented on the same IC die.

Abstract: A system includes a polyphase multirate filter and a controller which, responsive to detecting a data stream: measures a current phase relationship between a current resampling filter input clock signal and a current multirate output clock signal; identifies, based on a mapping of the measured phase relationship within a pre-generated quantized mapping table, an initial polyphase filter coefficient index corresponding to the measured phase relationship; selects, based on the initial polyphase filter coefficient index identified, a corresponding polyphase filter component from within the multirate filter; configures the multirate filter to pass data from the data stream through the corresponding polyphase filter component to generate an initial output data sample; updates the initial polyphase filter coefficient index to a calculated next polyphase filter coefficient index value, in response to a request for generation of a next output data sample; and self-corrects the multirate filter responsive to a pre-ide

Abstract: The present specification describes techniques and apparatus for reducing eye monitor data samplers in a receiver. A single eye monitor data sampler is used for multiple normal data samplers in a receiver.

Abstract: By a simple computation, orthogonal errors from an orthogonal modulator and an orthogonal demodulator are separately corrected. Based on the amplitude of a demodulated signal, an orthogonal-error detection unit (320) detects orthogonal errors from an orthogonal modulation unit (140) and an orthogonal demodulation unit (230). Specifically, according to the distribution of transmission signal points on an I-Q plane, demultiplexers (321 and 322) in an orthogonal-error detection unit (320) separate a demodulated signal into a signal on the I-axis and a signal on the Q-axis. Zero-crossing detection units (325 and 326) detect the amplitudes of the separated signals at the intersection of the I- and Q-axes. The orthogonal-error detection unit (320) detects the orthogonal errors based on results from comparing the amplitudes at said intersection.

Abstract: A symbol error detector can be configured to detect symbol errors of a Bluetooth enhanced data rate (EDR) packet without relying solely on a CRC error detection mechanism. After a phase of a current symbol is demodulated to determine a demodulated current symbol, the phase of the demodulated current symbol can be subtracted from the phase of the current symbol prior to demodulation to yield a phase error. The phase error can be compared against a phase error threshold to determine a potential unreliability of the demodulated current symbol. The phase error being greater than the phase error threshold can indicate that the demodulated current symbol may be unreliable. Accordingly, a symbol error notification can be generated to indicate that the demodulated current symbol may be unreliable.

Abstract: An encoder (10) includes a sensor (1) configured to illuminate light on a single scale (100) to detect two phase signals having periods different from each other, an error signal generator (2) configured to arrange accumulated amounts of phase changes of the two phase signals when the scale (100) and the sensor (1) are relatively displaced from each other by a predetermined displacement so as to obtain two accumulated phase signals and to obtain a difference between the two accumulated phase signals so as to generate an error signal that is obtained by removing an accumulated phase component corresponding to the predetermined displacement, and an interpolation error detector (3) configured to average the error signal by using at least one of periods of the two phase signals so as to detect an interpolation error contained in at least one of the two phase signals.

Abstract: A first transform unit transforms clock change point information which indicates the change timing of a clock signal into information with respect to the frequency domain thereof so as to generate first clock change point frequency information. A digital filter performs filtering of the first clock change point frequency information so as to generate second clock change point frequency information. A second transform unit inverse-transforms the second clock change point frequency information into information with respect to the time domain so as to generate second clock change point information. A judgment unit evaluates a DUT based upon difference data between the change timing represented by the data change point information and the change timing represented by the second clock change point information in increments of phases.

Abstract: A method for detecting offset signal corresponding to transmission leakage signal is disclosed, whereby reception sensitivity can be improved by accurately offsetting a leakage signal in transmission signal mixedly inputted into the reception signal in a radio transceiver, and an offset signal corresponding to a transmission leakage signal can be rapidly detected in the radio transceiver to rapidly offset the transmission leakage signal included in a reception signal.