Abstract: A switched capacitor integrator particularly suitable to realize low-pass filters without inducing noise on the nodes of the reference potentials of the integrator, is provided by halving the input capacitance during an operating phase, and by transferring the electric charge between the input switched capacitance and the capacitor of integration of one and the other feedback branch of the differential amplifier, in a direct manner, that is, not referred to a fixed common potential. A unique current path is established, thus averting the effects caused by inevitable mismatches between the integrated capacitors.

Abstract: A One Bit Digital Quadrature Vector Modulator (DQVM) and a method of generating single sideband output signals are useful for a wide range of radio frequency, signal processing and wireless applications. The DQVM simplifies the necessary digital multiplication by using noise shaped one bit versions of both the baseband IB and QB signals to be modulated and the ILO and QLO modulating signals. The one bit DQVM enables a much faster digital implementation of the digital quadrature vector modulation function than can be achieved with conventional multi-bit digital techniques. In addition the single sideband upconversion of the DQVM achieves high suppression of the unwanted sideband by applying an offset to one of the low speed input samples. Digital vector modulators are an improvement over conventional analog vector modulators as they are not subject to the amplitude and phase matching problems inherent in analog vector modulators.

Abstract: A 1-bit nth order Delta Sigma Modulator where n is at least one comprises a linear signal processing section (50) which processes the 1-bit signal and produces a p bit output, a filter (52) which filters the p bit signal, an adder (53) a quantizer Q coupled to the output of the adder (53) to quantize a p bit signal to a 1-bit output signal, and a noise shaping section 51 which feeds the 1-bit output signal back to the adder 53.

Abstract: The present invention, generally speaking, achieves a highly efficient line driver for high crest-factor signals such as DMT/ADSL signals. In an exemplary embodiment, a digital signal produced by a digital signal processor or the like is processed by a sigma-delta modulator (SDM) to produce one or more binary signal pairs. The signals of a signal pair are low-pass filtered, if necessary, and applied across the winding of a transformer. The transformer has a single secondary winding connected to the line and may has as many primary windings as the number of signal pairs. The transformer may have a unity turns ratio or may have a turns ratio for accomplishing voltage step-up. For one signal pair, the number of possible resulting signals levels on the secondary side is three, for two signal pairs five, etc. Using more than two signal levels, it becomes possible to recreate from the digital signals the corresponding analog waveform with the required accuracy.

Abstract: A signal processing device uses a &Dgr;&Sgr; modulator having varying effective orders to ensure an S/N ratio by selecting a high order when a 1-bit music signal is output via the &Dgr;&Sgr; modulator. The signal processing device prevents a noise during switchover by shifting to a low order just before the &Dgr;&Sgr; modulator is bypassed if this occurs. The present invention provides a digital signal processing device which can switch between an original sound signal and a &Dgr;&Sgr; modulation signal, and yield a sufficient S/N ratio for a reprocessed &Dgr;&Sgr; modulation signal. If any 1-bit original sound signal is input, little switching noise is generated.

Abstract: A variable-mode digital logic circuit for accepting a parallel data word of a plurality of data bits wide as input and serializing the word such that the word may be transmitted as output from the circuit over as few as a single one-bit wide trace is provided. The variable-mode digital logic circuit comprises, a plurality of parallel data traces for passing input data to the circuit, each trace dedicated to the transmission of a single bit of the word, a plurality of select-capable MultiPlexor circuits for sequentially activating certain ones of the parallel data traces to pass data thereto and for multiplexing the received data such that the data is serially output therefrom, a ring counter for controlling frequency of specific operations performed within the circuit and at least one additional MultiPlexor circuit array for receiving data output from the plurality of select-capable MultiPlexor circuits as input and for further serializing the received data for output on as few as a single one-bit wide trace.

Abstract: A tunable bandpass sigma-delta modulator analog-to-digital converter (A/D converter or ADC) utilized in conjunction with a digital signal processor (DSP) to eliminate the analog frequency synthesizer in a radio design is disclosed. The sigma-delta ADC greatly reduces the analog circuitry requirements and ensures that the circuitry is suitable for very large scale integration (VLSI). The all-digital DSP ensures the highest level of VLSI and provides for high performance frequency synthesis and translation completely in the digital domain.

Abstract: A system for reducing sensitivity of an integrated circuit chopper-stabilized amplifier to intermodulation applies a pseudo-random sequence signal (11A) to an LSB of a first input of a first adder. An error feedback signal (18) is applied to a second input of the first adder and a first input of a second adder (16). A 1-bit quantization signal (&phgr;CH) is produced as an MSB of an output of the first adder and applied to an LSB of a second input of the second adder (16). An error signal (16A) representing the difference between the quantization signal (&phgr;CH) and the error feedback signal (18) is produced by the second adder (16). The error signal (16A) is delayed a predetermined amount to produce the error feedback signal (18), wherein energy of the quantization signal (&phgr;CH) is spread over a broad frequency spectrum between DC and FS/2. A pair of out-of-phase, non-overlapping chopping signals from the quantization signal (&phgr;CH).

Abstract: A conversion (20, 120, 220) system for converting an analog signal (18, 118, 218) to a digital signal (54, 154, 254) in a communications system (10), the conversion system (20, 120, 220) including an oversampled analog-to-digital converter modulator (24, 124, 224) for receiving an oversampling-clock signal (29, 129, 229) and a transmitted analog signal (18, 118, 218), the oversampled analog-to-digital converter modulator (24, 124, 224) operable to sample the analog signal (18, 118, 218) and to convert the analog signal (18, 118, 218) to a first digital signal (32, 132, 232), a time adjustor (41, 141, 241) coupled to the oversampled analog-to-digital converter modulator (24, 124, 224) for receiving the first digital signal (32, 132, 232) and a first adjustment signal (48, 148, 248), and for producing an output digital signal (54, 154, 254), and a digital signal processor unit (56, 156, 256) coupled to the time adjustor (41, 141, 241) for receiving the output digital signal (54, 154, 254) and performing timing

Abstract: A signal processor for 1-bit signals comprises a nth order Delta-Sigma Modulator, where n is greater than or equal to 2. The Delta-Sigma Modulator comprises a first input 4A for receiving a first 1-bit signal and a second input 4B for receiving a second 1-bit signal. A quantizer Q quantises a p bit signal to 1-bit form, the requantized signal being the output signal of the processor. A plurality of signal combiners are provided. A first combiner (A1, 61, c1 b1, 71) forms the integral of the sum of the input signals and the output signal multiplied by coefficients A1, B1 and C1. At least one intermediate combiner forms the integral of the sum of the first and second input signals and the output signal multiplied by coefficients A2, B2, C2 together with the output of the first combiner. The final combiner a4, b4, 64 forms the integral of the sum of the first and second signals multiplied by coefficients A4 and B4 together with the output of the preceding intermediate combiner.

Abstract: According to the present disclosure, aperiodic data is applied to parallel register (500). When a predetermined relationship between an aperiodic load signal and a periodic oversample clock signal occurs, the aperiodic data is latched to the output (506) of the parallel register as substantially periodic data. The substantially periodic data is loaded into a sigma-delta DAC (502) for processing. The sigma-delta DAC (502) is driven by a periodic oversample clock to produce a 1-bit oversampled, time averaged representation of the substantially periodic data.

Abstract: A switching device for switching between a 1-bit digital signal .SIGMA..DELTA. modulated by a first sampling frequency and a 1-bit digital signal .SIGMA..DELTA. modulated by a second sampling frequency lower than the first sampling frequency. The 1-bit digital signal .SIGMA..DELTA. modulated by the second sampling frequency is transiently converted to the 1-bit digital signal .SIGMA..DELTA. modulated by the first sampling frequency. The converted 1-bit digital signal or the 1-bit digital signal .SIGMA..DELTA. modulated by the first sampling frequency is switched by cross-fading processing for realizing switching with suppressed noise generation at the time of switching.

Abstract: A low power passive .SIGMA..DELTA. converter for baseband applications and with a built in mixer for direct conversion. For direct conversion, low power consumption is achieved by adopting a passive loop filter for the .SIGMA..DELTA. converter together with merging the sampling and mixing functions together utilizing a specially designed mixer. With a passive loop filter, the only gain element in the loop is a high gain, high speed, low noise comparator. The mixer can be located outside of the feedback loop, although according to one aspect of the present invention, the mixer is incorporated inside the feedback loop. For baseband applications, the same design is utilized with a simple sampling switch instead of a mixer for processing baseband signals with low power consumption.

Abstract: A frequency synthesizer has a phase locked loop, a .DELTA..SIGMA. modulator, and a filter. The phase locked loop includes a frequency divider that controls the frequency of the phase locked loop output signal. The output of the .DELTA..SIGMA. modulator is fed through the filter and the output of the filter is used to control a division factor in the frequency divider. Compensation may be performed at the input to the .DELTA..SIGMA. modulator in order to compensate for the filtering performed between the .DELTA..SIGMA. modulator and the frequency divider. The filter may be used to reduce quantization noise in an input to the frequency divider, and thereby reduces phase noise in an output of the phase locked loop.

Abstract: A signal processing system receives and mixes a plurality of analog input signals having a maximum frequency. Each analog input signal is connected to an input of a modulator producing a high frequency oversampled digital signal. Each high frequency oversampled signal is connected to an input of a first decimation filter which produces an intermediate frequency oversampled multiple bit signal. Each of the intermediate frequency oversampled signals is connected to a respective input of a first digital mixer which produces a single mixed multiple bit output signal. The single mixed multiple bit output signal is connected to a second decimation filter which produces a final digital output signal, at a frequency suitable for representing the mixed analog input signals.

Abstract: Systems and method for monitoring and generating key pad status messages in a telecommunications network. A resistor ladder network is provided to generate distinct DC-level analog voltage signals in response to the pressing of any one of a plurality to keys of a key pad. A combiner circuit is employed to combine the DC-level analog voltage signals with an analog voice signal received from an audio transducer to form a composite analog signal, and a coder/decoder circuit is provided to convert the composite analog signal into a composite digital signal. A digital signal processing circuit executes a subtractive sample delta filtering algorithm to determine whether data indicative of a key press is included within the composite digital signal, and generates status messages indicative of a key press upon determining that a key has been pressed.

Abstract: The transition time of power switching devices ultimately limits the rate at which such devices can be switched. Because the occurrence of unacceptably narrow pulses is relatively rare in an oversampled, noise-shaping signal processor, the elimination of such narrow pulses is introduced through the use of circuitry in the modulator loop which constrains the time between transitions to be greater than or equal to some minimum time period which, in turn provides for a smooth interface to power switching devices. However, because of the delay introduced by this pulse qualification circuitry, the modulator loop sampling frequency is increased to deal with any resulting instability. Thus, an oversampled, noise shaping signal processor is described having at least one integrator stage in a feedback loop. A sampling stage in the feedback loop is coupled to the at least one integrator stage. The sampling stage samples an analog signal at a sample frequency.

Abstract: A delta sigma pulse width modulator control circuit uses a delta sigma modulator as a first stage to create a sequence of pulses representing an input control signal. A pulse width modulator accumulates the sequence of pulses and defines a pulse width modulated output signal from the accumulated pulses. The pulse width modulated signal is given a randomly generated offset to the time of pulse value transition and an adjacent pulse value matching technique is used to reduce harmonically related noise generation.

Abstract: Apparatus for determining a complexity measure of a data signal is disclosed which includes an encoder, having an input terminal responsive to a data input signal and a data output terminal producing a coded output signal representing the data input signal at a constant bit rate. The encoder includes a variable quantizer, responsive to the data input signal, for producing a quantized signal, representing the data input signal, having a quantizing step size defined in response to a quantizing step size control signal. A bit rate regulator produces the quantizing step size control signal in response to the bit rate of the coded output signal and a quota input signal. A complexity analyzer generates a complexity representative signal related to the quantizing step size and the bit rate of the coded output signal.

Abstract: An A/D converter apparatus comprising a negative feedback loop having a main signal line supplied with an input signal of a predetermined frequency and a feedback signal line passing through a feedback signal, a A/D converter connected to the main signal line for frequency-converting the input signal to a signal having a frequency different from that of the input signal to output a converted signal, a D/A converter connected to the feedback signal line for frequency-converting the feedback signal to a signal having a frequency substantially equal to that of the input signal, and a subtracter for subtracting the feedback signal from the D/A converter from the input signal to supply a subtraction result signal to the A/D converter.

Abstract: A high-quality transmission apparatus for a 1-bit digital signal. The 1-bit digital signal is transmitted via a phase modulator arranged upstream of a transmission route and demodulated by a phase demodulator arranged downstream of the transmission route for suppressing the jitter caused by power source variations and radiation noise during transmission.

Abstract: A delta modulation type data converter is adapted to carry out signal processing by sequentially comparing in cycles an inputted signal with a reference voltage set according to the results of previous comparisons and includes a plurality of current sources, switch circuits for setting a current value by appropriately selecting one or more of these current sources, an integrator circuit for generating the reference voltage according to a specified current value, and a control circuit for controlling the switch circuits to make an appropriate selection of these current sources according to the result of a comparison between the reference voltage and the inputted analog signal. The control circuit controls the switch circuits such that, if the result of comparison is the same as in the precious cycle, a selection from the current sources is made such that the current value will be increased, provided such selection is possible.

Abstract: An analog modulator employing .DELTA.-.SIGMA. transformation and comprising timings generator, at least a single operational-amplifier (OP-amplifier) filter of Biquadratic transfer function and saturation detection circuit, is provided. This novel approach solves the stability issue by controlling the switching timings of the single operation-amplifier biquadratic filter in the .DELTA.-.SIGMA. modulator. During normal operation, this high-order .DELTA.-.SIGMA. modulator constructed by the single OP-amplifier biquadratic filter functions a third-order or fourth-order modulator. As unstable condition occurs, via the saturation detection circuit and timings generator, the third-order or the fourth-order modulator functionally converts into and performs as a stable .DELTA.-.SIGMA. modulator of second-order.

Abstract: A communication receiver (600) utilizes a band-pass sigma-delta converter (100) for receiving a radio signal. The band-pass sigma-delta converter (100) includes a comparator (106) coupled to an adder-filter (101) for making a comparison between a predetermined reference level (110) and an intermediate signal (125), and for generating a comparison result signal (114) responsive to the comparison. A storage element (108) is used for storing the comparison result signal (114) for a predetermined delay period, thereby producing a clocked output signal (118). The adder-filter (101) is coupled to an analog signal (103) and to the clocked output signal (118) for subtracting the clocked output signal (118) from the analog signal (103) to produce a difference signal (120) that is filtered by a commutating filter (400) for generating the intermediate signal (125) responsive to the difference signal (120).

Abstract: A mixing circuit for synthesizing plural .DELTA..SIGMA. modulated data generated simultaneously with a bit rate F to single mixed data includes a slot determining section for dividing time length corresponding to 1-bit period of the .DELTA..SIGMA. modulated data into a number N which is of the same number as the plural .DELTA..SIGMA. modulated data, and a time division multiplex section for assigning in order the plural .DELTA..SIGMA. modulated data to the 1-bit period at a bit rate N*F on a time shared basis. The obtained mixed data can be converted to linear PCM data with a single decimation circuit. By increasing the bit rate of the mixed data by N times the bit rate F of the .DELTA..SIGMA. modulated data, a total gain can be maintained at a constant value irrespective of a change in the number of data to be synthesized.

Abstract: A sigma-delta signal converter is implemented using switched capacitor switching elements in which a first switch (31) serves as a mixer (11). The output of the mixer is directed to the second input of an adder (16), and its second input is the feedback signal (f1) of the sigma-delta signal converter, which is also directed into a base-frequency output signal through a decimator (14) and low-pass filtering (15).

Abstract: A circuit configuration for converting a one-bit digital signal at a given sampling frequency into an analog signal, includes a multiplication device having one input receiving the digital signal, another input receiving a reference signal and an output. A delay device receives the digital signal, delays the digital signal by one period of a sampling frequency and has an output. A further multiplication device has one input connected to the output of the delay device, another input receiving the reference signal and an output. An adding device has inputs each being connected to the output of a respective one of the multiplication devices and an output at which the analog signal is available.

Abstract: A signal processing apparatus in which the effective dynamic range information for maintaining linearity of an output signal is appended to a transmitted 1-bit digital signal as ancillary data. When the 1-bit signal is converted into a multi-bit digital signal, the gain of the 1-bit signal is adjusted on the basis of the effective dynamic range information.

Abstract: Digital signal receivers for detecting BPSK modulation of a suppressed carrier transmitted through the same channel as an analog television signal are described, in which the detected BPSK is digitized with an oversampling analog-to-digital converter prior to digital comb filtering for separating the BPSK from interfering analog television signal remnants. This is done to get an increased number of bits resolution from a relatively inexpensive flash converter so that the BPSK, which is of relatively low amplitude compared to maximally interfering analog television signal remnants, is not overwhelmed by quantizing noise. The oversampling analog-to-digital converter can be of sigma-delta type.

Abstract: The present invention discloses method and apparatus for offset and phase correction in multiplexed delta-sigma modulators. According to the invention, offsets and phases of input signals to multiplexed delta-sigma modulators are corrected by a simple and low cost method. The invention utilizes a novel switching technique during different sampling periods to eliminate the effect of DC offsets present in multiplexed input signals. The invention also uses a delay introduced by a FIFO or a shift register to individually correct for phase shifts present in individual multiplexed input signals. The invention accomplishes these objectives without introducing a significant quantization noise, and without requiring overlapping FIR filters.

Abstract: An electronic arrangement for generating a modulated carrier signal in a transmitter includes a sigma-delta (one-bit) signal converter and a mixer. The sigma-delta converter includes, in a closed signal loop, an adder, a low pass filter, and a pulse shaper driven with a specific sample rate. The mixer is driven with a carrier frequency fc and has an input coupled with an output of the pulse shaper. The carrier frequency fc is equal to or an integer multiple of the half sample rate.

Abstract: A delta modulator automatically adjusting the slewing rate is disclosed. In the absence of a transition in the output data of a delta modulator, a parameter used for the integrator of the delta modulator is increased. When the comparator of the modulator indicates that the feedback signal of the modulator has overshot the input signal, the parameter is decreased or reversed until the two signals are approximately equal as signalled by a 50% duty cycle.

Abstract: A method of cascading sigma-delta modulators includes the step of feeding the input to the quantizer of each modulator stage to the subsequent stage. Therefore, the signal which is fed to each of the subsequent stages is the difference between the output and the quantization noise of the previous stage. The method also includes the step of removing the quantization noise of the first two stages, as well as the output of the first two stages, so that the final output of the cascaded modulators is a delayed version of the input, plus a scaled version of the last stage which has been shaped with a fourth-order high pass function.

Abstract: In a noise shaper comprising integrators of three or more stages, a quantizer and a feedback circuit, there are provided a circuit for subtracting from an output of each of the integrators a result obtained by delaying the output of the same integrator by one sample and multiplying it by a constant number, so as to output the result of the subtraction to an integrator at the subsequent stage, and a circuit for feeding back a result obtained by delaying an output of the quantizer by one sample and multiplying it by any constant number value, to an input of each of the integrators.

Abstract: A system and method for cascading three sigma-delta modulators involves applying an error signal representing the quantization error of a preceding modulator to a subsequent modulator. The error signal is scaled by a factor before being applied to a subsequent modulator. The quantized error signal of the subsequent modulator is then scaled by the reciprocal of the original scaling factor before being combined with the quantized outputs of the previous modulators. Combining the quantized outputs of the three modulators is performed so as to cancel the quantization error of the previous stages while shaping the noise at the last stage so that most of the noise is placed at high frequencies.