Abstract: Digital video data is transmitted from a video source (61) to a video sink (62) as a group of three multilevel symbols (611, 612, and 613) per pixel color with each associated symbol being sent at a rate of three times the pixel clock (601). When eleven levels are used per symbol (611) and undesirable symbol groups having excess DC residual or minimal energy are eliminated, and a built-in-test symbol group is added for pixel alignment; there results a one-to-one correspondence between the remaining symbol groups available and the two-hundred and sixty possible states that are used in the TMDS physical layer that is in widespread commercial use.

Abstract: In a high-speed serial link, an eye finder diagnostic circuit has improved performance by being on-chip with the existing capture latch(es) of a receive equalizer. The eye finder circuit employs an additional capture latch with its input tied to the same input node as the existing capture latch(es) of a receive equalizer. The additional capture latch has a clock input and reference voltage input. The clock input is adjusted through a phase interpolator (or variable delay line) while the reference voltage input is adjusted by a voltage generator. A digital post processing circuit then compares the output of the additional capture latch with the output of the other existing capture latch(es), in order to determine the receive eye opening. The horizontal eye opening is measured by changing the phase of the additional capture latch through the phase interpolator, while the vertical eye opening is measured by changing the reference voltage of the voltage generator of the additional capture latch.

Abstract: An apparatus and method for frequency synchronization is proposed to obtain the pilot tones and evaluate the frequency offset and time offset for frequency synchronization. The frequency synchronization method has the following steps: filtering a baseband signal of a frequency correction burst by using multiple pre-filters; measuring the baseband signal and the signals output from the pre-filters to produce the first power value and the second power values respectively; normalizing the maximum second power value by using the first power value so as to produce the first detection value; using the samples of the baseband signal at different time points and a predetermined mathematical function to produce the second detection value; combining the first and second detection values to produce the third detection value; and using the third detection value to determine whether the frequency correction burst is received or not.

Abstract: Chronologically synchronizing a unique positing signal generated by a positioning-unit device at a known location with a reference positioning signal generated by a reference transmitter at a known geometric distance. The positioning-unit device receives and interprets a reference positioning signal. It then generates and transmits a unique positioning signal, wherein the unique positioning signal is aligned with a frequency steerable clock. The positioning-unit device then receives the unique positioning signal. The positioning-unit device then adjusts the frequency of the frequency steerable clock by an amount derived from a measured frequency difference. The positioning-unit device then determines a reference positioning signal propagation delay between the reference transmitter and the positioning-unit device. At this stage, a time difference is measured between the received reference positioning signal and the received unique positioning signal.

Abstract: A method for implementing a flexible sampling-rate encoder, comprising the steps of (A) sampling an input signal at a regular time-interval to produce sampled data, (B) generating a pseudo-random bit sequence having a plurality of bits, wherein each bit corresponds to a different sampling time, (C) encoding a first set of the sampled data to generate an encoded stream when any bit in the pseudo-random bit sequence is equal to a first value, wherein each bit in the encoded stream corresponds to one of the sampling times defined in step (B), and (D) determining the different sampling time for each sample in the encoded stream.

Abstract: According to an aspect of an embodiment, a communication system includes a transmission apparatus with a coding section that generates multi-level-coded signals and transmits the multi-level-coded signals; and a deskew signal generation section that generates and transmits a deskew signal related to the multi-level-coded signals. The communication system also includes a receiving apparatus with a decoding section that decodes the multi-level-coded signals to generate decoded signals, and a deskew processing section that performs deskew processing for compensating skew among the decoded signals of the multiple channels. The deskew signal generation section generates the deskew signal that has been framed by extracting a part of the data from each of the channels of the input signals, adding framing data for enabling a receiving apparatus to recognize which channel the extracted data has been extracted from, and performing rate conversion.

Abstract: Provided is a system and method for terrestrial digital broadcasting service using a single frequency network without additional equipment. The system and method synchronizes input signals into transmitting stations by inserting a transmission synchronization signal into a header of TS periodically, and solves the problematic ambiguity of the trellis encoder by including a trellis encoder switching unit separately and initializing a memory of the trellis encoder. The terrestrial digital broadcasting system includes: a broadcasting station for multiplexing video, voice and additional signals into transport stream (TS) and transmitting the TS to the transmitting stations and a transmitting stations for receiving the TS and broadcast the TS to receiving stations through a single frequency network.

Abstract: Systems and methods of edge calibration for synchronous data transfer between clock domains are disclosed. An exemplary method may comprise comparing a drive clock signal to a receive clock signal, generating a select clock signal, and configuring a data path based a least in part on the select clock signal for synchronous data transfer between clock domains so that data arrives in an early clock domain at the desired logical clock cycle.

Abstract: Presented herein are systems and methods for clock rate determination. A bitstream is sampled by sampling a transmitted clock signal at a rate corresponding to a receiver clock signal, and measuring an average number of consecutive samples that have a same state selected from a first state and a second state.

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract: An automatic frequency correction phase-locked loop (PLL) circuit includes an analog control circuit and a digital control circuit. The digital control circuit includes a High-side comparator and a Low-side comparator which receive an analog control voltage, a state monitor circuit, and a counter and decoder circuit. At least one of the High-side comparator and the Low-side comparator includes a threshold switching circuit which selectively provides a first threshold voltage and a second threshold voltage, the first and second threshold voltages having different magnitudes. When the analog control voltage remains stable between the High-side threshold voltage and the Low-side threshold voltage and the threshold switching circuit is providing the first threshold voltage, the state monitor circuit switches the threshold switching circuit from the first threshold voltage to the second threshold voltage, thereby expanding the interval between the High-side threshold voltage and the Low-side threshold voltage.

Abstract: A method for synchronizing receivers that receive turbo encoded signals to a received signal. Turbo encoding may enable signals to be decoded at a much lower signal to noise ratio than previously practical. A traditional method of synchronizing a receiver to an incoming signal is to use a slicer to determine a received symbol and then to compare the determined symbol to the incoming waveform, in order to adjust the phase of the slicer with respect to the incoming signal. At signal low levels, at which turbo encoded signals may be decoded, this slicing method may be prone to errors that may disrupt the synchronization of the receiver to the incoming signal. By replacing the slicer by a Viterbi decoder with zero traceback (i.e. one which does not consider future values of the signal only past values) a prediction as to what the incoming signal is can be made.

Abstract: An apparatus for transmitting a signal in a semiconductor integrated circuit includes a multilevel transmission control block that outputs a plurality of bits of an input signal in serial or parallel according to whether a multilevel transmission operation is performed or not, and a signal processing block that selectively performs the multilevel transmission operation according to a form of the input signal, which are output in serial or parallel from the multilevel transmission control block.

Abstract: A method of synchronizing a receiver with a transmitter. The method includes determining number of bits, j, for adjusting a bit stream, where the bit stream is generated from n tones and is dividable into codewords having a codeword length of N bytes, and the number of bits for adjusting the bit stream is determined based upon n and N. The method includes detecting a loss of synchronization indication. In response to detection of the loss of synchronization indication, the method includes adjusting the bit stream by j bits. The method includes determining whether synchronization has been regained. When synchronization has not been regained, the method includes adjusting the bit stream again by j bits. When synchronization has been regained, the method includes terminating adjustment of the bit stream.

Abstract: Method and apparatuses for broadcasting and receiving a programme are presented. A programme is broadcast from a broadcasting system. Broadcast programme-associated data is transferred from a server to a cellular radio network. The broadcast programme-associated data is transmitted from a base station of the cellular radio network at a specific frequency defined for the cellular radio network in such a manner that the transmission of the broadcast programme-associated data is synchronized with the broadcasting of the programme. The programme and the broadcast programme-associated data is received with a subscriber terminal of the cellular radio network in such a manner that a programme receiver of the subscriber terminal receives from the broadcasting path of the broadcasting system the programme and a cellular radio network transceiver of the subscriber terminal receives the broadcast programme-associated data at a specific frequency.

Abstract: A circuit for single or parallel digital fractional interpolation of data samples has a fractional interpolator filter, an oscillator for outputting timing signals to the fractional interpolator filter, and a detector loop with a strobe feedback from the oscillator for outputting a frequency adjustment to the oscillator. Three different approaches are shown to determine the frequency adjustment. One approach is to generate a pulse based on the symbol clock, and measure the differences between the pulse and the strobe and between the strobe and the pulse. The smaller is the frequency adjustment. Another approach is to adjust the strobe period to match the symbol clock period. A third approach is to add an oscillator-driven clock to the symbol clock and integrate the sum over a symbol clock period to generate the frequency adjustment.

Abstract: A clock recovery circuit samples an incoming data stream that includes sequences of signal transitions. A transition detector categorizes the received signal transitions into various types, such as those associated with 2PAM and 4PAM signaling schemes. Select logic control circuitry analyzes the signal-transition types to determine which of the transition types is best suited for clock recovery. This determination relies upon a number of factors, including for example whether the received signal is a 4PAM signal or a 2PAM signal, the existence of a pattern within the received data, or the relative abundance or scarcity of certain types of transitions.

Abstract: A bit synchronization circuit composed of a multiphase data sampling unit for converting each received burst data sets to multiphase data trains, a phase determination unit for generating a control signal indicating an optimum phase data train, an output data selector for selectively passing optimum phase data train indicated by the control signal, and a data synchronization unit for converting the optimum phase data train to a data train in synchronization with a reference clock. The phase determination unit repeatedly detecting the optimum phase data train during the same burst data set is received. When optimum phase varies, the output data selector dynamically switches the optimum phase data train to be supplied to the data synchronization unit.

Abstract: Clock recovery of a multi-level (ML) signal can be performed in a two-step process. First, the transitions within the ML signal can be detected by a novel transition detector (TD). And second, the output of the TD circuit can comprise a pseudo-non-return-to-zero (pNRZ) signal that can drive a conventional OOK clock recovery (CR) IC. The TD circuit can convert the edges of the ML signal into the pseudo-NRZ (pNRZ) signal. The TD circuit can capture as many transitions as possible to allow the conventional NRZ clock recovery (CR) chip to optimally perform. The TD circuit can differentiate the ML signal in order to detect the ML signal's transitions.

Abstract: A digital serial interface connects a transmitting device with a receiving device for communicating both data bits and synchronization signals via the serial interface. The transmitting device include a primary transmitter for converting a serial sequence of the data bits into successive data signal levels, and further includes a secondary transmitter for converting synchronization signals into synchronization signal levels different from the levels employed for the data signals. The receiving device has a primary receiver for the data signal levels for converting a sequence of data signal levels into a serial sequence of data bits, and further includes a secondary receiver fir the synchronization signal levels for converting synchronization signal levels into synchronization signals.

Abstract: A receiver in which sync data detection logic detects unencoded sync data at block boundaries of blocks encoded symbols received over a communications channel. Based on the detection of the sync data, the sync data detection logic determine synchronization information for one or more components of the receiver. It may also determine one or more system parameters by counting the number of symbols between successive instances of the sync data.

Abstract: A method for selecting a modulation detector in a receiver and a receiver which includes a first and a second modulation detector, mechanisms for determining at least one cross-correlation value between the stored training sequence and at least one training sequence of the received signal, and mechanisms for selecting the detector used for the detection of a signal to be received in response to the determined at least one cross-correlation value.

Abstract: A signal compensation circuit compensates for direct-current offset of an input signal by amplifying the input signal with an amplifier having a variable direct-current offset. A low-speed negative feedback loop charges and discharges a capacitor in an integrating circuit according to the direct-current component of the amplified signal. A high-speed negative feedback loop charges and discharges the same capacitor at a faster rate when the amplified signal goes outside an allowable amplitude range. The capacitor potential is used to control the direct-current offset of the amplifier. The allowable amplitude range is adjusted according to the amplitude of the amplified signal. High-speed compensation can thus be combined with a tolerance for runs of identical code levels in the input signal.

Abstract: The invention relates to a method for synchronization of clock sources in a communications system, in particular a radio communications system, having a large number of devices (PSTN, MSC, RNM, BSi, MSi, OMC) which communicate directly or indirectly with one another and have reference clock sources (Cs) for their operation. In order to overcome aging effects or timing errors in the clock sources (C), the invention proposes the clock sources (C) of one or more communicating devices (MS, BS, RNM) be synchronized by means of asynchronous signaling from at least one reference clock source (Cs). This even allows devices with clock sources that are becoming old to be operated reliably. Furthermore, in particular, there is no need for every device to have its own high-precision clock source (CS). Use is particularly advantageous in communications systems in which no reference clock is transmitted via a landline network.

Abstract: A timing error detection circuit capable of detecting a timing error of symbols in a signal with a simple and small-sized configuration, comprising a sampling circuit for sampling a signal including symbols arranged at a predetermined symbol cycle at a frequency equal to four times of a symbol rate, an amplitude detection circuit for detecting an amplitude of a position subjected to said sampling in said signal, a difference detection circuit for detecting a timing error indicating deviation of the symbol included in the signal from a conceivable timing based on difference of said detected plurality of amplitudes, and a timing error signal generation circuit.

Abstract: A switching circuit is for switching an output thereof to one of a plurality of N input clock signals which are delayed relative to one another. The switching circuit includes at least one circuit responding to a control signal to enable the transmission, on an output signal, of a new signal of the plurality of input signals. The new signal is advanced or delayed relative to a current signal of the plurality of input signals which is currently transmitted on the output signal. The at least one circuit enables the transmission of the new signal before disabling the transmission of the current signal on the output signal. This substantially prevents the production of false signals during the switching of the output signal from one of the clock signals to another.

Abstract: A method of baseband/passband digital modulation for a data transmission system wherein a plurality of data symbols is transmitted over a transmission channel at a symbol rate. The method comprises the following steps: (1) generating a plurality of I and Q components of symbols by mapping an input bit stream comprising a plurality of digital codewords into a QAM constellation; (2) selecting a passband or a baseband mode; and (3) generating an analog output signal in the passband or baseband mode. The step of selecting the passband or the baseband mode depends on the complexity of QAM constellation. If QAM constellation includes less than 64 QAM plant points, the passband mode is selected, and if QAM constellation includes more than 64 QAM plant points, the baseband mode is selected.

Abstract: Circuits and methods align an internal signal with an external signal. A phase lock loop network receives the external signal to generate phase lock loop signals. A programmable ratio decoder provides a code. An alignment unit generates the internal signal based on at least one of the phase lock loop signals. The alignment unit aligns internal signal with the external signal based on the code.

Abstract: The invention concerns a method of checking the synchronization between at least two nodes Ni?1, Ni, with i=1, . . . , n in a network, each of said nodes having respectively an internal clock having a respective clock frequency Fi?1, Fi, wherein said method includes the following steps: a) transmitting the frequency Fi?1 of the internal clock from the node Ni?1 to the node Ni, b) comparing the frequency Fi?1 of the internal clock of the node Ni?1 transmitted to the node Ni with the frequency Fi of the internal clock of said node Ni, c) checking the synchronization between the nodes Ni?1 and Ni using the result of the comparison between the frequencies Fi?1 and Fi.

Abstract: A system and method for reducing transmit carrier wander in a DSL communication system are disclosed. A network timing reference unit provides an automatic embedded solution for synchronizing DSL frames to an external communication system reference clock. The network timing reference unit applies or removes bits to adjust the length of a DSL frame in response to a sliding window state table. A sliding window is selected in response to the relative position of the DSL frame to a system clock reference point over a number of DSL frames. A network timing reference unit in accordance with the present invention may comprise a counter, a network timing latch, a synchronization word detector, a DSL frame latch, a lead/lag comparator, a sliding window buffer, a sliding window state table, a DSL frame state recorder, and a sensitivity buffer. The present invention provides a method for reducing transmit carrier wander in a DSL transceiver.

Abstract: A receiver in which sync data detection logic detects unencoded sync data at block boundaries of blocks encoded symbols received over a communications channel. Based on the detection of the sync data, the sync data detection logic determine synchronization information for one or more components of the receiver. It may also determine one or more system parameters by counting the number of symbols between successive instances of the sync data.

Abstract: A method for recovering a reference clock from a composite clock signal is provided. The method includes receiving the composite clock signal. First and second intermediate clock signals are generated from the composite clock signal. The first and second intermediate clock signals are combined to recover the reference clock signal.

Abstract: Phase-locked-loop based data and clock extraction comprising a phase detector that generates up and down pulses. Down pulses are maintained in width approximately equal to 1.5 unit intervals of a local sampling clock. Up pulses are allowed to vary with the phase relationship between the local sampling clock and an incoming encoded bit stream. The up pulses are allowed to vary between 1 and 2 unit intervals of the local sampling clock. The up and down pulses drive a charge pump D/A converter that generates a control voltage. The control voltage sets the frequency of the local sampling clock generated by a voltage controlled oscillator. Shift register controlled by a state machine and clocked by the local clock allows reception of complex data packets arriving by the encoded bit stream.

Abstract: Clock recovery of a multi-level (ML) signal can be performed in a two-step process. First, the transitions within the ML signal can be detected by a novel transition detector (TD). And second, the output of the TD circuit can comprise a pseudo-non-return-to-zero (pNRZ) signal that can drive a conventional OOK clock recovery (CR) IC. The TD circuit can convert the edges of the ML signal into the pseudo-NRZ (pNRZ) signal. The TD circuit can capture as many transitions as possible to allow the conventional NRZ clock recovery (CR) chip to optimally perform. The TD circuit can differentiate the ML signal in order to detect the ML signal's transitions.

Abstract: A phase lock loop is provided for recovering timing information from a received data signal in a 100Base-TX receiver. The phase lock loop includes a phase encoder (803) for generating a reference phase error. An output phase value on a bus (809) is subtracted from the reference phase value on line (805) with a subtraction block (813) to generate a phase error. This phase error is averaged and decimated over a predetermined number of potential symbol transitions in the received signal. The output phase error is provided from a block (815) on a line (817) to a loop filter. This output is provided only once for each decimation operation such that the loop filter can operate at a lower clock rate. The phase error output is then utilized to select one of multiple clocks that correspond to the phase error, these being incremental phase clocks referenced to a master clock. This utilizes a clock multiplexer (1427) to select one of the multiple clock inputs which are delayed in phase off of the master clock.

Abstract: The method of transmitting data as a sequence of high bits and low bits over a transmission line from a transmitting device to a receiving device includes transmitting synchronization signals over the transmission line and transmitting one and only one high bit or one and only one low bit over the transmission line at an end of each synchronization signal. When the predetermined voltage levels for the high bit, low bit and synchronization signals are different from each other, the method is implemented in an especially simple manner. The interfaces for the receiving and transmitting devices for performing the method are also described.

Abstract: The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.

Abstract: In transmitting ten-bit word string data including synchronous word data converted, at a transmitting side, from eight-bit word string data, representing signal information data synchronization required for reproducing the signal information is reliably established at a receiving side. An additional word data group containing eight-bit synchronous word data is inserted between words of the eight-bit word string data. Then, 8B-10B conversion is performed on the eight-bit word string data, thereby obtaining ten-bit word string data. In this case, the additional word data group is selected so that a running disparity of the ten-bit synchronous word data contained in the additional word data group of the composite ten-bit synchronous word data is consistently positive or negative.

Abstract: A method of detecting the loss-of-signal condition at the input of a transmission line interface when the input signal is coded. The input signal decoding includes an additional procedure allowing the detection of loss-of-signal condition. Since the pseudo-random sequence of the input signal transitions includes sequences of code violations, the additional procedure, over a certain threshold error rate, corresponding to a number of code violations in a unit of time, detects the loss-of-signal condition.

Abstract: A method and apparatus utilizing a data processing system are disclosed for multi-level data communication providing self-clocking. A first digital signal is input which includes a series of digital bits. One of a plurality of output levels is associated with each group of data bits for each of the plurality of the digital bits included within the first digital signal. A particular output level is associated with a clock output level. An output signal is generate which includes a transmission of the output level for each of the groups of digital bits and includes multiple transmissions of the clock output level, where a clock output level is transmitted after each transmission of an output level for each of the groups of digital bits.

Abstract: Apparatus, and an accompanying method, for transmitting a frame synchronization signal and a data signal simultaneously through a serial transmission medium (170). Specifically within a data transmitter (105), a frame synchronization signal, a clock signal and a data signal, are encoded to form a single bi-phase mark signal having the frame synchronization signal incorporated into the bi-phase mark signal as a phase-shift. The bi-phase mark signal is then transmitted through a suitable serial transmission medium. A receiver (175), connected to the transmission medium, receives and amplifies an incoming bi-phase mark signal appearing on the medium, and, in turn, synthesizes the clock, frame synchronization, and data signals from this bi-phase mark signal.

Abstract: A network for transferring data packets has at least two basic networks, each with a central station and a limited number of user stations. The respective central station connects the associated basic network to other basic networks. The data packets are transferred over a set of channels with the frequency-hopping method and the channels are in this context selected for data transfer in accordance with at least one frequency-hopping pattern in temporal succession. A separate frequency-hopping pattern that is orthogonal to the frequency-hopping patterns of immediately adjacent basic networks is processed in each basic network.

Abstract: A selective call receiver unit (700) capable of reducing data distortion and improving simulcast reception includes a selective call receiver (20), a demodulator (30) coupled to the selective call receiver and a circuit (36 and 300) coupled to the demodulator for reducing data distortion received at a selective call receiver. The circuit includes a detector (350) for detecting a simulcast signal, a filter (351) for windowing the symbol edge area in the simulcast signal providing a windowed symbol edge area, and a clipping circuit (36) for clipping the windowed symbol edge area.

Abstract: A bit synchronizing circuit is arranged by a bit synchronization counter constructed of an up/down counter or an adding/subtracting counter; an edge detector for detecting an edge of an input NRZ signal to output an edge detection pulse; two sets of edge number counters for counting total numbers of edge detection pulses outputted from the edge detector during a 1 cycle of the counting operation by the bit synchronization counter; and two sets of registers for fetching the count value of the bit synchronization counter at the time instant every time the edge detector outputs the edge detection pulse, and also for storing an accumulation value of the count values fetched during the 1 cycle of the counting operation by the bit synchronization counter. Both the two edge number counters and the two registers are operated with shifts of a half cycle, respectively.

Abstract: A symbol synchronizer (10) for use in a communication device. The symbol synchronizer (10) comprises a sampling circuit (100) which samples the demodulated signal at a plurality of sampling events for each symbol period to generate three sample values at each sampling event. An eye pattern detector circuit (200) generates eye pattern characteristic information based on the three sample values, and outputs a symbol pulse in response to detecting eye pattern characteristic information consistent with a symbol center. A synchronization noise mask circuit (400) filters symbol pulses that occur during a predetermined period of time after a first symbol pulse is detected for each symbol period. A synchronization adjust circuit (500) generates a synchronization pulse during each symbol period at a particular instant of time during the symbol period based on a history of the occurrences of symbol pulses for a current symbol period and for prior symbol periods.

Abstract: A selective call receiver (800), including a receiver circuit (101) and a processor (810), is used for synchronizing an internal reference to symbol edges of a plurality of symbols in a multi-level radio signal transmitted by a radio communication system. To perform this function the processor (810) is adapted to cause the receiver circuit (101) to demodulate the multilevel radio signal to in-phase and quadrature signals (108, 106), convert the in-phase and quadrature signals (108, 106) to a sequence of state transitions representative of the plurality of symbols, detect at least one same state transition from the sequence of state transitions, and synchronize the internal reference to the at least one symbol edge of the plurality of symbols based on the at least one same state transition.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.