Abstract: A method and arrangement for estimating a DC offset for a signal received in a radio receiver. The received signal includes a digitally modulated signal component, a DC offset component, and a noise component. When the signal is of a known type, such as a Gaussian Minimum Shift Keying (GMSK)-modulated signal with constant amplitude in a GSM/EDGE cellular radio system, the method exploits the known characteristics of the statistical distribution for the known type of signal to obtain a better estimate of the DC offset. The statistical distribution of the received digitally modulated signal component is first analyzed. That statistical distribution is then compared to the known statistical distribution for the known type of signal to identify differences. The differences are then used to estimate the DC offset. Additional iterations may be performed to further improve the DC estimate.

Abstract: A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device.

Abstract: In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation.

Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.

Abstract: Demodulator includes reception quality evaluation circuit for evaluating the quality of a received signal by comparison with a first reference value, and outputting an evaluation signal; and driving circuit receiving the evaluation signal. If reception quality evaluation circuit evaluates that the quality of the received signal is acceptable, power supply from driving circuit to DC offset control loop is stopped. This offers a high-frequency receiver that reduces power consumption.

Abstract: The present invention relates to a direct current (DC) offset suppression circuit to suppress DC offsets occurring when a communication circuit where a complex filter is adopted performs self-mixing. The DC offset is suppressed by a DC feedback circuit adopted by a filter which is substituted for a complex filter in the communication circuit. But, the DC offset cannot be suppressed when a complex filter is used in the communication circuit. It is because phase changes of the complex filter cause output signal fed back to the input of the complex filter to generate phase differences. The present invention includes a phase compensation unit and a DC feedback unit. The phase compensation unit compensates a change in frequency between input and output of the complex filter for phase compensation. The DC feedback unit inverses and feeds back the compensated phase to an input of the complex filter.

Abstract: A hybrid structure circuit for the cancellation of both Type-I and Type-II DC offsets. It comprises a static compensator in conjunction with a servo-loop feedback amplifier to suppress the undesired DC components present along the path of the base band after the direct conversion mixer. Two mixers are used to down convert a received RF signal directly to a base band signal with two components: in-phase and quadrature-phase. Both in-phase and quadrature-phase branches employ the same circuitry for DC offset cancellation. Miller effect is also utilized in the structure in order to implement the circuit on-chip.

Abstract: An apparatus and method for removing a Direct Current (DC) offset at a receiving terminal in a wireless communication system are provided. In the method, a frame is divided into at least two time resource blocks. Resource allocation information is used to discriminate between at least one time resource block of a data-unmapped interval and at least one time resource block of a data-mapped interval. The DC offset is measured during the data-unmapped interval. The DC offset is compensated during the data-unmapped interval on a time resource block basis by using the measured DC offset.

Abstract: A radio frequency receiver (102) includes at least one amplifier (108, 114 and 122) for amplifying a signal received by the radio frequency receiver, an automatic gain control system (158) for controlling a gain of the at least one amplifier, and a direct current offset correction filter (142) for reducing any direct current component of the signal amplified by the at least one amplifier. The direct current offset correction filter has a bandwidth that is dynamically controlled by a change in the gain of the at least one amplifier. The radio frequency receiver also includes a digital automatic gain control unit (150) having a bandwidth that is dynamically controlled by the change in the gain of the at least one amplifier.

Abstract: A direct-current-offset correction device includes a digital-to-analog converter that converts a digital signal into an analog signal, a modulator that modulates the analog signal to generate a modulated signal, a direct-current-offset correction value calculation unit that calculates a direct-current-offset correction value as a reverse characteristic component of a carrier leak occurring in the modulated signal based on a demodulated signal which is demodulated by feeding back the modulated signal, a direct-current-offset correction unit that corrects a direct-current-offset on the digital signal based on the direct-current-offset correction value, a correction value detection unit that detects whether or not the direct-current-offset correction value is zero or a neighboring value of zero, and an offset generation unit that superimposes a direct-current-offset component on the analog signal based on a detection result of the correction value detection unit.

Abstract: A demodulation apparatus for a Radio Frequency Identification (RFID) reader includes: a direct current (DC) offset cancellation unit for cancelling DC-offset noise contained in a PSK-modulated or ASK-modulated subcarrier tag signal from the tag signal when the tag signal is received; and a subcarrier digital demodulator for eliminating a subcarrier from the tag signal from which DC-offset noise has been cancelled to demodulate the DC-offset noise-cancelled tag signal.

Abstract: The present invention provides a method and apparatus for correcting direct current (DC) offsets in radio output signals. The invention comprises a radio processor and a baseband processor. During a calibration routine, the baseband processor measures DC offset produced by the radio processor, generates a corresponding DC offset correction value, and writes the correction value to a discrete memory in the radio processor via a serial processor interface. During a subsequent normal receive operation, the radio processor reads the DC offset correction value from memory and feeds it into a into a digital to analog converter to produce an analog signal that in turn is fed into a radio receive path to nullify undesired DC offset.

Abstract: The present invention provides a frequency tuning/DC offset canceling circuit for continuous-time analog filter with time division, the frequency tuning/DC offset canceling circuit including: a frequency tuning/DC offset canceling unit for performing frequency tuning by comparing an output voltage with a reference voltage when a frequency tuning control signal is inputted, and canceling a DC offset after terminating the frequency tuning when a DC offset canceling control signal is inputted; and a control signal generator for generating the frequency tuning control signal and the DC offset canceling control signal based on a reference clock in time division.

Abstract: A receiver assembly for use in an optical telecommunications network is provided that automatically generates a reference level for the incoming signal burst based on its preamble without the need to pre-process the entire signal burst. The entire signal burst is fed directly from the TIA into the input of the limiting amplifier. A differential amplifier, tapped from the data and data bar outputs of the limiting amplifier, samples the signal stream to capture the preamble portion of each signal burst. The preamble portion of the signal burst is then passed, post amplification, into a sample and hold circuit. The sample and hold circuit samples the amplitude of this preamble portion of the signal and then holds the sampled level for use as a reference level for the processing of following payload signal.

Abstract: A method of detecting an on-channel signal and synchronizing signal detection with correcting for DC offset errors in a direct conversion receiver is presented. A received signal is digitized, and a state machine operates to detect the presence of an on-channel signal. If the signal is not detected, a mixed mode training sequence is initiated in which the DC offset errors in both an analog and digital received signal path are corrected. While training, processing of the digitized samples by a digital signal processor and a host controller is suspended (while they are put into battery save mode) and the gain provided to subsequently received signals is minimized. The DC offset correction circuitry is bypassed and put into battery save mode at predetermined periods when DC offset correction is not performed.

Abstract: A null detector and its corresponding method are provided. The null detector includes a power detector, a smoother, and an overlapper. The power detector outputs a power level signal according to the power level of a received signal. The smoother is coupled to the power detector for determining according to the power level signal whether the received signal is transmitting a null symbol, and then the smoother outputs a null detection signal at a first state value or a second state value indicating the result of the determination. The overlapper is coupled to the smoother for providing the duration and position of the null symbols transmitted by the received signal according to the null detection signal.

Abstract: A communication receiver includes a mixer, a filter group and an analog-to-digital converter. The mixer is used for mixing an input signal with a local oscillation signal to generate a mixed signal. The filter group is coupled to the mixer, and is used for filtering the mixed signal to generate a filtered signal, where the filter group includes a first one-pole filter, a second one-pole filter, and a complex-pole filter. The analog-to-digital converter is coupled to the filter group, and is used for performing an analog-to-digital converting operation on the filtered signal to generate a digital signal.

Abstract: The invention relates to the field of modulation and demodulation circuits, such as envelope detectors used to demodulate amplitude-modulated (AM) signals and amplitude-shift-keying (ASK) signals. By judiciously coupling an analog circuit comprising one resistor and two capacitors which are judiciously dimensioned to a port of a digital component, an extremely compact envelope detector can be obtained, which achieves demodulation of a binary ASK signal for direct coupling into a digital input port. Accordingly, a very compact envelope detector may advantageously be used in the data receiving part of a sealed device requiring post-manufacturing data transfer, in combination with additional components that provide electromagnetic coupling, such as inductive coupling, capacitive coupling, or radiative coupling. An example of such a device is a credit card sized authentication token, the electrical personalization of which happens after the production of the card-like housing.

Abstract: Receiver circuitry for processing a received Very Low Intermediate Frequency signal wherein the receiver circuitry comprises a main processing path. The main processing path comprises mixing circuitry arranged to mix a received VLIF signal with a frequency down conversion signal to produce a main path signal. The receiver circuitry further comprises a direct current cancellation path comprising mixing circuitry arranged to mix a DC element of the received VLIF signal with the frequency down conversion signal to produce a DC cancellation signal. The receiver circuitry still further comprises signal summing circuitry arranged to add the DC cancellation signal in anti-phase with the main path signal.

Abstract: A method and system of establishing an offset for a receiver. In one embodiment, a method includes receiving an input signal and generating a first signal. The method can further include integrating the input signal and the first signal at a reference node. In addition, the method can include comparing the input signal to a signal at the reference node and generating an output signal, analyzing the output signal to determine whether the output signal contains noise, and modifying the first signal based on the analysis of the output signal.

Abstract: A signal processing apparatus has a plurality of baseline wander correcting units, provided in a processing path in which a predetermined processing is performed on an input signal. At least one of the plurality of baseline wander correcting units includes a correction permission control unit that controls permission or rejection of correction, and baseline wander in the input signal is corrected sequentially by each of the plurality of baseline wander correcting units, based on a control of the correction permission control unit. The baseline wander correcting unit corrects the baseline wander by determining whether or not the baseline correction is to be effected or not, so that the wander of baseline can be efficiently corrected.

Abstract: Proposed are a highly reliable information detecting apparatus and an information detecting method.

Abstract: A circuit that receives input signals from a transmitter via proximity communication, such as capacitively coupled proximity communication, is described. Because proximity communication may block DC content, the circuit may restore the DC content of input signals. In particular, a refresh circuit in the circuit may short inputs of the circuit to each other at least once per clock cycle (which sets a null value). Furthermore, a feedback circuit ensures that, if there is a signal transition in the input signals during a current clock cycle, it is passed through to an output node of the circuit. On the other hand, if there is no signal transition in the input signals during the current clock cycle, the feedback circuit may select the appropriate output value on the output node based on the output value during the immediately preceding clock cycle.

Abstract: Methods and systems are provided for estimating the DC offset distortion in a receiver. A fast Fourier transform is applied to at least a portion of a preamble portion of the received signal; an impact of the DC offset distortion on one or more empty subcarriers is determined; individual DC estimates are derived based on each of the determinations; and each of the individual DC estimates are combined to obtain an overall DC estimate.

Abstract: A multibit quantizer is provided, at its input terminals, with a variable gain circuit and an offset addition circuit to perform tracking control in which for each sampling time, the level of an offset signal of the offset addition circuit is adjusted based on output digital data of an output processing circuit and the preceding control signal of an offset control circuit so that the quantizer operates without causing a saturation operation. As a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time.

Abstract: A method of compensating for dc offset of a received signal transmitted over a channel having a plurality of paths, the received signal comprising a modulated data signal and a modulated known training sequence signal, the method comprising the steps of: constructing (104) from the known training sequence signal a first regression matrix; path-combining (106) the incrementally rotated elements of the first regression matrix to produce the elements of a trend matrix; deriving (108) a neutralized second regression matrix from the first regression matrix and the trend matrix; utilising the neutralized second regression matrix to compensate (110, 112) for dc offset of the received modulated data signal.

Abstract: A DC voltage offset correction circuit that provides for correction of a DC offset voltage of an output of a filter stage of a complex filter circuit includes a DC offset sensing device that is connected to an output of a filter stage of a complex filter to generate an offset presence signal indicating presence of the DC offset voltage at the output of the filter stage. The digital-to-analog converter applies a compensation signal to the output conditional on the offset presence signal. A programming register receives the offset presence signal to perform a binary search to generate a digital signal to force the digital-to-analog converter to apply the compensation voltage to the output of the filter stage. A filter controller sets the compensation voltage level in the programming register to match a programmed gain value of the filter stage.

Abstract: A method of compensating for dc offset of a received signal transmitted over a channel having a plurality of paths, the received signal comprising a modulated data signal and a modulated known training sequence signal, the method comprising the steps of: constructing (104) from the known training sequence signal a first regression matrix; path-combining (106) the incrementally rotated elements of the first regression matrix to produce the elements of a trend matrix; deriving (108) a neutralized second regression matrix from the first regression matrix and the trend matrix; utilising the neutralized second regression matrix to compensate (110, 112) for dc offset of the received modulated data signal.

Abstract: A carrier recovery device for a communication receiver is disclosed. The carrier recovery device includes an A/D converter for converting an analog signal received by the communication receiver to a digital signal, a frequency compensator coupled to the A/D converter for compensating frequency of the digital signal according to a carrier frequency offset value, a filter coupled to the frequency compensator for filtering the digital signal to generate an output signal, and a frequency offset estimator coupled to the filter and the frequency compensator for estimating the carrier frequency offset value according to the output signal and providing the carrier frequency offset value to the frequency compensator for implementing carrier recovery.

Abstract: A system for removing a DC-offset component from an input signal is presented. The system includes a sorter to separate positive samples and negative samples of the input signal. The system further includes a positive sample average generator to calculate a positive sample average according to a number of positive samples in the input signal and a negative sample average generator to calculate a negative sample average according to a number of negative samples in the input signal. A balanced average generator is provided for receiving positive and negative sample averages from the positive and negative sample average generators and for generating a reference signal. The system further includes a subtractor for subtracting the reference signal from the input signal to generate a DC-offset compensated output signal.

Abstract: A system and method are provided for using disparity measurements to control the adjustment of a data slicer threshold. The method receives a serial stream of pseudorandom digital data signals having an average DC value, and compares data signal amplitudes to a slicer threshold value. In response to the slicer threshold value comparison, data signal “1” and “0” values are determined. A first sum of determined “1” values is created, and a second sum of determined “0” values is created. The slicer threshold value is adjusted in response to the comparison of the first and second sums. More explicitly, the slicer threshold value is adjusted to make “1” values more likely in response to the second sum being larger than the first sum. Alternately, the slicer threshold value is adjusted to make “0 ” values more likely in response to the second sum being smaller than the first sum.

Abstract: A received signal delivered through a transmission line can be compensated for CFO and DCO to improve the SNR of the received signal, eventually resulting in an effective improvement in the error rate. In this context, methods for estimating and compensating for CFO and DCO have been studied, for example, using pilot signals or a blind method. However, the methods would require a huge amount of calculations for the estimation of CFO in the presence of DCO, as with the ML method, or never essentially eliminate errors from an estimated value. The received signal has convoluted influences through the transmission line, so that observation of the continual symbols of periodic pilot signals on the frequency axis shows just a phase shift by the CFO. Therefore, the CFO can be analytically found from the continual symbols of periodic pilot signals, thereby allowing the DCO to be estimated and both the CFO and the DCO to be compensated for.

Abstract: A DC offset estimator and removal circuit removes the DC offsets for each of the I and Q signal components in a received signal. A gain imbalance estimator and compensator circuit estimates and compensates for gain imbalances within the I and Q signal components. A phase imbalance estimator and compensator circuit estimates and compensates for phase imbalances within the I and Q signal components to produce a communications signal that is compensated for received DC offsets and gain and phase imbalances within the I and Q signal components.

Abstract: A receiver includes a memory for storing DC offset amounts generated by an analog circuit; an amplifier; a DC offset amount generator for generating a first offset value and a second offset value to be removed from the received signal amplified at the amplifier; a first DC offset component-removing unit for removing the first DC offset value from the received signal before the amplifier; a second DC offset component-removing unit for removing the second DC offset value from the received signal after the amplifier; and an updating unit for updating the DC offset amount stored in the memory in view of the second DC offset value generated by the DC offset amount generator. A maximum value of the second DC offset value is set larger than a multiplication value of a gain of the amplifier by a minimum resolution value of the first DC offset value.

Abstract: A differential radio frequency signal transmitter is provided. The differential radio frequency signal transmitter includes an oscillator, a modulator and an amplifier module. The oscillator generates a pair of differential oscillation signals. The modulator generates a pair of differential modulated signals according to an input signal and the pair of differential oscillation signals. The input signal is a digital signal. When the input signal is at a first state, the modulator outputs the pair of differential oscillation signals as the pair of differential modulated signals, and when the input signal is at a second state, the modulator outputs a constant voltage signal as the pair of differential modulated signals. The amplifier module receives and amplifies the pair of differential modulated signals and generates a pair of differential radio frequency signals, accordingly.

Abstract: Described herein is a method of automatic gain control and simultaneous digital correction of three types of variations in I/Q receivers: gain imbalance, phase imbalance, and DC offset. Three adaptation loops can operate simultaneously and use the output of an analog to digital converter (ADC) as their input, with the output driving digitally controllable analog components. With appropriate knowledge of signal statistics, the algorithm automatically optimally fills the ADC's full input signal range, providing an automatic gain control function and thus maximizing the signal-to-quantization-noise ratio. In so doing, it corrects gain imbalances between I and Q paths, while additional circuitry corrects DC offsets and phase imbalances.

Abstract: A signal processing apparatus sets a discrimination level most suitably, regardless of whether the apparatus is in the minimum receiving system or the maximum receiving system. The apparatus comprises a light receiving unit converting input signal light to an electric signal, and a level detecting unit for detecting a high level component and a low level component of the electric signal from the light receiving unit, along with peak levels on a high-side and a low-side of the electric signal.

Abstract: A frequency offset (CFO) and a direct current component offset (DCO) occur in an OFDM scheme signal. To address this, such a method has been suggested which allows a pilot signal to be mixed with a communicated signal for compensation. However, if the pilot signal has a long duration, then a compensation method without the pilot signal is required to compensate signals during that period. However, no such a method is conventionally available which compensates for both the CFO and DCO without the pilot signal. Using the orthogonality of the OFDM signal, the matrix of a system in which CDO and DCO have occurred is subjected to the singular value decomposition, thereby predetermining the CFO candidate value which allows for demodulating zero from the received signal and an array of numerical values of CFO check data. Then, in a compensation section (17), the received signal is successively multiplied by the numerical values.

Abstract: A system and method for compensating for DC offset and/or clock drift on a wireless-enabled device is described. One embodiment includes a radio module, an A/D converter connected to the radio module, a DC tracking loop connected to the A/D converter, and a multi-hypothesis bit synchronizer.

Abstract: A method for detecting an access code in a receiver that does not require an explicit DC-offset interference correction block, comprising: a) projecting a received signal R onto a subspace orthogonal to the DC; b) projecting the access code Ci onto the subspace; and c) detecting the presence and location of the access code Ci and eliminating any DC offset therein when the frequency offset f0 in the access code Ci is orthogonal to the subspace, and is therefore nulled out.

Abstract: A system for processing signal communications between a frequency translation module and an integrated receiver decoder. According to an exemplary embodiment, the decoder and the frequency translation module comprise a signal processing apparatus comprising an input for receiving an frequency shift keyed modulated signal, an amplifier having negative feedback coupled to said input, wherein said input is further coupled to a first source of reference potential and a second source of reference potential; and a tank circuit coupled between said differential amplifier and an output.

Abstract: A method of reducing d.c. offset comprises comparing the a first variable signal with a second variable signal, producing a control signal in dependence upon the comparison, providing the control signal to a charge pump for generation of a feedback signal, and varying the first signal and/or the second signal in dependence upon the feedback signal thereby reducing any difference between the d.c. level of the first signal and the d.c. level of the second signal.

Abstract: An apparatus and method for canceling a DC offset efficiently removes the DC offset by calculating the DC offset after acquiring synchronization in a terminal receiver used for an orthogonal frequency division multiplexing system. The apparatus for canceling the DC offset includes an adding/averaging unit (130), an accumulator (140), a synchronization determiner (150), and a pulse density modulation signal generator (160). The adding and averaging the added input data signals over one frame. The accumulator (140) outputs a DC offset control value by successively accumulating the DX offsets calculated from the adding and averaging unit. The synchronization determiner (150) determines whether to output the DC offset control value provided by the accumulator (140) based on synchronization information. The pulse density modulation signal generator (160) generates a digital pulse density modulation signal based on a representative value provided by the synchronization determiner (150).

Abstract: A receiver uses a wideband intermediate frequency (IF) in the analog domain and performs low IF down-conversion in the digital domain, using low-power, high-speed, high resolution analog-to-digital converters. The receiver can be integrated into an integrated circuit as one of several receivers. Such an integrated circuit may include multiple transmitters using adaptive non-linear modeling pre-distortion. The non-linear modeling may include memory. Imbalance in intermediate frequency in-phase and quadrature signals may be corrected in the digital domains. DC offsets in the intermediate signal may be corrected in both analog and digital domains. In one instance, the receiver provides a feedback receiver for the adaptive pre-distorter in a transmitter on the integrated circuit.

Abstract: Baseband (BB) input units input baseband received signals. An initial weight data setting unit sets weighting coefficients to be utilized in the interval of a training signal as initial weighting coefficients. A gap compensating unit compensates control weighting coefficients with a gap error signal and outputs the updated weighting coefficients acquired as a result of the compensation. A weight switching unit selects the initial weighting coefficients in the interval of the training signal and selects the updated weighting coefficients in the interval of the data signal. Then the weight switching unit outputs the selected initial weighting coefficients and updated weighting coefficients as the weighting coefficients. A synthesizing unit weights the baseband received signals with the weighting coefficients and then sums them up.

Abstract: In order to compensate for performance degradation caused by inferior low-cost analog radio component tolerances of an analog radio, a wireless communication transmitter employs a control process to implement numerous digital signal processing (DSP) techniques to compensate for deficiencies of such analog components so that modern specifications may be relaxed. By monitoring a plurality of parameters associated with the analog radio, such as temperature, bias current or the like, enhanced phase and amplitude compensation, as well as many other radio frequency (RF) parameters may be implemented.

Abstract: Methods and apparatus are disclosed for DC offset estimation and for DC offset compensation that collectively reduce or eliminate the distortion of subcarriers due to DC offset in an OFDM receiver. The DC offset estimation is obtained by subtracting a sum of time domain samples of an OFDM symbol for two consecutive OFDM symbols or subtracting a known transmitted OFDM symbol and a frequency domain representation of a received version of the known OFDM symbol (at least one of which is adjusted to compensate for channel distortion). The DC offset compensation is accomplished by removing the estimated DC offset from the received signal. The DC estimation process and the DC compensation process can be connected in disclosed feed-forward or feedback configurations.

Abstract: Certain aspects of a method and system for independent in-phase (I) and quadrature (Q) loop amplitude control for quadrature generators may include determining an amplitude voltage associated with an in-phase (I) component and a quadrature (Q) component of a generated signal. A DC reference voltage associated with the I component and the Q component may be determined. The determined amplitude voltage may be compared with the determined reference voltage to generate a control signal. The amplitude mismatch between the I component and the Q component may be compensated by controlling a biasing current of one or more programmable buffers associated with one or both of the I component and the Q component, based on the generated control signal.

Abstract: A device and method for DC offset cancellation device are disclosed. The method includes keeping a high pass module at off state, converting an analog radio frequency signal to a digital baseband signal by a direct down conversion receiving module, detecting a DC offset value during the conversion by an offset compensation module so as to provide an offset compensation signal corresponding to the DC offset value to the direct down conversion receiving module, and determining whether a control condition is reached by a control module so as to timely switch on the high pass module for canceling the residual DC offset in the direct down conversion receiving module. In the present invention, the offset compensation module provides preliminary offset compensation signals and then the high pass module accurately cancels residual DC offset, thereby significantly reducing the reaction time for DC offset cancellation.

Abstract: A method of determining a set of Zero Correlation Zone (ZCZ) lengths, comprises: determining the length of a root sequence, and selecting such a set of ZCZ lengths that, for any cell radius, the maximum number of preambles obtained from a ZCZ length which is selected from the selected set of ZCZ lengths is closest to the maximum number of preambles determined from a ZCZ length which is selected from the set of all integers, wherein the maximum number of preambles is determined from the length of the root sequence and a ZCZ length selected. This disclosure provides a technical solution for selecting a better limited set of ZCZ lengths by which signaling overload is reduced.