Abstract: A method that uses time-domain processing on a spectrally efficient digital modulation scheme to reduce the bandwidth expansion in envelope elimination and restoration (EER) amplifiers is disclosed. The method identifies and localizes sections of the signal responsible for the out of band emissions, or spectral regrowth, using a filter. The detected sections are flagged and extended to allow for introduction of a lower frequency transition in place of the extended section, thus reducing spectral regrowth from the output of an EER amplifier. The method is particularly useful for improving the quality of digital AM radio transmission.

Abstract: A system and method for bit eye center determination is provided. In general, the system samples an incoming data stream to determine where transitions in the data stream occur, selectively offsets the selected samples based on state criteria and the number of transitions in each set of samples, accumulates the offset samples and averages the result to determine the center of the bit eye. The system and method also provides the ability to locate the eye center even in the case of noise in the system, whether the noise is random or deterministic, including odd/even noise.

Abstract: A transmission apparatus, a signal sending apparatus, and a signal receiving apparatus, and a transmission method, a signal sending method, and a signal receiving method capable of solving a problem of metastability and suppressing a delay of a signal when sending and receiving apparatuses having different operation clock frequencies send/receive the signal representative of control information, for example. Included are a sending part that operates in synchronization with a first clock having a first period to output a transmission signal having a signal level that is inverted in response to an input of a first pulse signal corresponding to the first period and a receiving part that operates in synchronization with a second clock having a second period to output a second pulse signal corresponding to the second period in response to inversion of a signal level of the transmission signal.

Abstract: An oversampling data recovery circuit for a receiver comprises a plurality of sampling circuits for sampling an input data upon a plurality of clocks to generate a plurality of sample data, respectively, an edge detector for determining an edge of the input data by monitoring the plurality of sample data, and a state machine for selecting one from the plurality of sample data as an output data of the oversampling data recovery circuit according to the edge of the input data, such that the receiver will have an optimum timing margin.

Abstract: A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase error signal for adjusting the clock signal that is generated from a voltage-controlled oscillator. The phase detector includes a positive-edge detector circuit that generates an edge detection signal P to indicate whether data transitions are present in the input data. The phase detector also includes a lead/lag indicator circuit that generates a lead/lag indicator signal T to indicate whether the clock signal is early or late with respect to the input data.

Abstract: A transmission bit and transmission power distributing method that can reduce the arithmetic amount in a multiantenna-input/multiantenna-output (MIMO) wireless communication system. This method comprises steps of calculating a signal-to-interference-noise ratio (SINR) gain after MIMO detection of each of transport substreams (S601, S602); optimizing, based on the acquired SINR gain, a transmission bit and transmission power distribution in the space domain for all transport substreams on a particular subcarrier in the frequency domain, thereby deciding a transmission bit and transmission power distribution parameters (S603, S604); and optimizing a transmission bit and transmission power distribution for adjacent subcarriers, by sequentially using the transmission bit and transmission power distribution parameters distributed on the subcarrier for which the transmission bit and transmission power distribution parameters have been decided (S605 to S610).

Abstract: A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.

Abstract: The present invention is directed to a method, apparatus and system for detecting the mode and the guard interval of a received orthogonal frequency division multiplexing (OFDM) symbol, which includes a guard interval with length Ng, and a useful part with length Nu. Mode is detected by searching for the maximum correlation or statistics value based on one (for example, the shortest one) guard interval length. Further, guard interval is detected by searching for the maximum correlation value based on all guard interval lengths.

Abstract: A base point of a communication frame is detected by only using a reception signal, and an offset amount from the base point and the like are estimated. A device includes: an extraction unit for extracting self correlation processing signals from a digital communication signal having a signal frame for synchronization by using a pair of correlation processing windows of a variable size; a correlation unit for performing self correlation processing to the self correlation processing signals extracted; a matching unit for performing pattern matching processing between the correlation-processed signal, obtained through the self correlation processing, and a reference signal; and a computation unit for estimating the base point of the signal frame and an offset of the digital communication signal with respect to the base point, based on distance information of the pattern matching processing.

Abstract: An apparatus comprising an optical receiver configured to receive an optical signal, and a combined level and clock recovery circuit coupled to the optical receiver and configured to update a signal threshold and a clock phase substantially simultaneously. Also included is an apparatus comprising at least one processor configured to implement a method comprising recognizing reception of a signal, and adjusting a threshold and a clock phase associated with the signal using a rising time for the signal and a falling time for the signal. Also included is a method comprising receiving a signal, and adjusting a threshold level of the signal to establish level recovery using a clock recovery scheme.

Abstract: Clock signals are supplied, with a phase shift of 1/n cycles between adjacent clock signals. A data acquisition unit acquires serial data at a timing of each of the clock signals. A phase detection unit detects the phase of the transition edge of the serial data using n bits of data. An effective bit number determination unit determines the effective bit number, which is the number of bits to be acquired, based upon the phase of the transition edge of the serial data in the current data-bit acquisition step and the phase of the transition edge of the serial data in the previous data-bit acquisition step. A data-bit output unit outputs the effective bit number of the bits of data acquired at a timing of each clock signal having a predetermined phase relation with the transition edge of the serial data.

Abstract: A system (101) for clock signal synchronization includes a data analyzer (104) and a synchronized clock signal generator (105) coupled to an RC oscillator (103). The data analyzer (104) generates a digital control signal representing the number of cycles of a reference signal of the RC oscillator (103) during an eight-bit period of an incoming token packet. The synchronized signal clock generator (105) uses the digital control signal to lock a clock signal to packets that have the same bit rate as the token packet.

Abstract: A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices.

Abstract: Techniques are disclosed for detecting a packet. One technique includes sampling a received signal to produce a sequence of samples wherein the sequence of samples includes a plurality of subsequences of samples; cross correlating the subsequences of samples with a known form of the subsequence to produce cross correlations; self correlating the cross correlations to produce a plurality of self correlations; summing the self correlations; and processing the sum of the self correlations.

Abstract: The present subject matter is directed to methodologies for measuring jitter spectral content in a sampled signal using continuous time interval analyzers (CTIA) for characterization and test of clock signals and high-speed digital interfaces. The methodology takes advantage of anti-aliasing aspects of random sampling (RS) in a time interval error (TIE) based analysis methodology by randomizing timing of samples relative to signal edges and/or intervals between signal edges.

Abstract: Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some embodiments, each counter or clock has a different speed. A faster counter or clock is used to determine intra-transition position offsets relative to a slower counter or clock.

Abstract: An apparatus and method for detecting leading pulse edges of a signal includes a controller, hysteresis threshold comparators and qualification timers. The controller uses the outputs from the timers in order to determine whether or not a transition of the input signal constitutes a leading pulse edge of the input signal.

Abstract: The invention discloses a signal detection apparatus and method thereof for detecting whether an input signal of a set of serial ATA signals is an out of band (OOB) signal. The signal detection apparatus includes a calibrated clock generation device, a signal processor, and a logic determination device. The calibrated clock generation device generates a sampling clock signal according to a predetermined clock signal. The signal processor generates a plurality of detection results based on the sampling clock signal and the input signal. The logic determination device receives the plural of detection results and determines whether the input signal is the OOB signal.

Abstract: There is provided a multi-carrier transmission device capable of improving a packet error ratio in a system where transmission data is repeatedly multi-carrier-transmitted. In this device, the transmission data is subjected to error correction encoding in an error correction encoding unit (102), modulation in a modulation unit (104), and repetition in a repetition unit (106). A signal after the repetition (repetition bit) is two-dimensionally mapped in the frequency domain and the time domain according to a predetermined pattern in a mapping unit (108). The repetition bit transmission power is controlled so that the total value of the transmission power of repetition bit constituting one bit is identical to all the bits and the repetition bit of preferable reception quality has a large transmission power while the repetition bit of bad reception quality has a small transmission power.

Abstract: A semiconductor memory device includes an aligning signal generator, a data aligning unit, a data transmitting controller and a data transmitter. The aligning signal generator receives a data strobe signal to output aligning signals. The data aligning unit aligns a plurality of data pieces input in succession in response to the aligning signals. The data transmitting controller generates a data transmitting signal synchronized with the transition of the aligning signal. The data transmitter transmits an aligned data output from the data aligning unit to a data storage area in response to the data transmitting signal. A method for driving the semiconductor memory device includes aligning data pieces input in succession as parallel data in response to a data strobe signal, generating a data transmitting signal corresponding to transition of the data strobe signal and transmitting the parallel data to a data storage area in response to the data transmitting signal.

Abstract: A method and apparatus for data multiplexing is capable of high-speed operation with acceptable timing margins and has reduced sensitivity to supply voltage, temperature, manufacturing and other variations. One implementation relates to a data multiplexer that has no significant speed limitation associated with the clock-to-data delay of data latches, flip-flops, etc. In one implementation, clock-to-data delay is compensated for by introducing a delay-compensator in the clock line that drives a selector stage of the multiplexer. In one such implementation, a timing relationship is established between clock and data waveforms by timing the data waveforms with a first in-phase clock and operating the delay-compensated selector clock line with a second clock, which is delayed with respect to the first clock. The second clock can have a quadrature-phase delay with respect to the in-phase clock.

Abstract: A wireless communication device includes an antenna configured to receive electromagnetic energy corresponding to a wireless communication signal outputted using an interrogator and to output electrical energy corresponding to the received electromagnetic energy, communication circuitry coupled with the antenna and configured to sample the electrical energy to process the wireless communication signal, synchronization circuitry coupled with the antenna and the communication circuitry and configured to generate a clock signal to control sampling of the electrical energy using the communication circuitry, wherein the synchronization circuitry is configured to generate a plurality of transitions within the clock signal responsive to a plurality of transitions of the electrical energy during a first data period and wherein the synchronization circuitry is configured to generate a plurality of transitions within the clock signal during a second data period including generating at least one of the transitions indep

Abstract: An adaptive equalization apparatus is provided. The adaptive equalization apparatus includes an equalizer, a monitor circuit, and a control circuit. The equalizer receives a first signal, and equalizes the first signal according to an equalization parameter setting to thereby generate a second signal. The monitor circuit is electrically connected to the equalizer, and monitors edges of the second signal in a real-time manner to thereby generate a detection result. The control logic is electrically connected to the equalizer, and adaptively adjusts the equalization parameter setting according to the detection result.

Abstract: Serially transferred data is over sampled with a multiphase clock signal generated as a result of shifting a predetermined frequency clock signal by a predetermined phase each, to obtain over sampling data; generating clock patterns, having mutually different phase states according to a data phase state of the over sampling data. A first phase pattern generated from the over sampling data is compared with a second phase pattern generated from the clock pattern, and the number of bits to extract from the over sampling data is controlled. A phase error of the over sampling data is detected based on the first phase pattern and the second phase pattern. Bits to extract from the over sampling data is selected to restore the data based on the phase state of the clock pattern and the phase error.

Abstract: An equalization circuit that allows particularly for lowpass filtering by transmission lines comprises a compensating equalizer controlled according to whether the edges between bits in the data waveform are early or late. Adjusting the equalization causes edges to appear in the same place, whereas if the adjustment is incorrect certain edges will be late and certain edges will be early depending on the history of “1”s and “0”s in the data stream. This is an effect of so-called intersymbol interference. The control mechanism includes circuits for recognizing patterns of “1”s and “0”s in the recent history of the data waveform whose occurrence is used to trigger the adjustment of the equalizer.

Abstract: A clock and data recovery circuit comprising a phase detection circuit, first and second oscillators, and a flip-flop. The phase detection circuit outputs a detection signal according to a significant transition of an input signal. Each oscillator receives the detection signal and operates alternately in a clock and data recovery mode and a phase-locked mode. When the first oscillator operates in the clock and data recovery mode and outputs a first clock to control the flip-flop to output an output signal, the second oscillator operates in the phase-locked mode to adjust a frequency of a second clock. Before switching to the clock and data recovery mode, the second oscillator synchronizes the second clock with the first clock.

Abstract: A circuit for detecting a clock has a plurality of first transmission elements, a plurality of first exclusive OR gates and a first AND gate. Each first transmission element is coupled to a last first transmission element for receiving output data, and the data received by each first transmission element is transmitted to an input terminal of a next first transmission element. In addition, the input of a first transmission element is coupled to a clock source for receiving a predetermined clock signal of which a frequency is less than a frequency of a local clock signal. Furthermore, the first and second input terminals of a kth exclusive OR gate are coupled to output terminals of a kth and a (k+1)th first transmission elements, wherein k is an integer greater than 0 smaller than a total number of the first transmission elements.

Abstract: The present invention provides an event edge synchronization system and a method of operating the same. In one embodiment, the event edge synchronization system includes: (1) a first clock zone device configured to generate an event signal based upon a first clock rate, (2) a second clock zone device configured to operate at a second clock rate, which is asynchronous with the first clock rate and (3) a synchronous notification subsystem configured to receive the event signal, synchronize the event signal to the second clock rate based upon an edge transition of the event signal and the second clock rate, and generate a synchronous notification signal therefrom.

Abstract: A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

Abstract: A clock and data recovery circuit that tracks the frequency and phase fluctuation of serial data includes a feedback controller for monitoring tracking speed of an extraction clock with respect to the frequency and phase fluctuation of the serial data and applying feedback control to an integrator adaptively and moment to moment, thereby raising the tracking speed of the recovered clock and improving the jitter tolerance characteristic.

Abstract: In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock.

Abstract: A frequency overlay communication system that includes a first communication system for performing communication using a first frequency band being a preset bandwidth; and a second communication system for performing communication using a second frequency band being a second preset bandwidth, wherein the second frequency band includes the first frequency band.

Abstract: A guard interval length detector is introduced. The guard interval length detector includes a delay conjugate multiplier capable of delaying a plurality of input signals to provide delayed input signals and multiplying each of the plurality of input signals with a complex conjugate of a corresponding one of the delayed input signals to provide multiplied signals, a phase detector capable of determining phase values corresponding to the multiplied signals, and a period detector capable of detecting a period according to the phase values, and determining a guard interval length of the input signals according to the period.

Abstract: A communication device comprises a receiver and a data recovery module. The receiver may be an element of a serial transceiver embedded in or otherwise associated with an FPGA or other type of reconfigurable hardware. The receiver is operable with an unlocked sampling clock. The data recovery module is configured to detect transition edges in data signal samples generated by the receiver using the unlocked sampling clock, and to determine from the detected edges a sampling point for use in recovery of the associated data. The data recovery module is further configured to provide adjustment in the sampling point in the presence of transition edge variations, such as one or more exception conditions, that are attributable to the unlocked sampling clock.

Abstract: A multiphase encoded protocol has sufficient density of commands to allow a rich language to be realized on a bus. When ten field bits are dedicated to commands, it is possible to have more than six million words to choose from per clock. Architecture to implement the multiphase encoded protocol and synchronize the bus includes an extracted clock, a command element, and a data element. One-bit multipliers are used as correlation elements to provide feedback into slaved delay-locked loop (DLL) devices, which provides precise phase alignment for successful data extraction of several channels.

Abstract: A system and method is provided for bit eye center retraining. In general, the system samples an incoming data stream to determine where transitions in the data stream occur, selectively compares the location of the transitions to the expected locations to produce difference values, and combines pairs of difference values to determine when the sample point of the data stream needs to be adjusted.

Abstract: A communication system, clock generation circuit, and method are provided for receiving jitter upon data and to generate a clock reference that does not contain the received jitter. The clock reference can be used either by a digital subsystem of a communication system node, or can be transmitted as substantially jitter-free data from that node to a downstream node of the communication system. Instead of recovering the clock reference from the data having jitter, a pattern is regularly defined within the data stream preferably at periodic, timed intervals. The data pattern may be made up of a series of non-transitions which, regardless of any jitter in the data itself, does not impute any jitter onto a phase-locked loop triggered from an edge of the non-transitioning data pattern. Using the edge as a reference point, a jitter-free clocking signal can be derived at the same frequency as a clocking signal which would normally be produced from the jitter-induced data.

Abstract: A method for determining a clock for a sensor signal which has a synchronization signal, which method involves a control unit measuring the period between a first edge and a second edge of the synchronization signal, wherein both edges are either rising or falling, and the control unit taking the period as a basis for determining a clock for sampling data in the sensor signal.

Abstract: The present invention relates to receiver equipment with AC-coupled receiver circuits and AC coupling filters. A switch connected between a first stage and a second stage among the receiver circuits is adapted to switch from a high coupling corner frequency, for rapid settling of a signal during preparation of data reception, to a low corner frequency, for low signal distortion during data reception. The receiver circuits are adapted to use known properties in the signal to perform the switch at a time when the short term DC-components of the signal are as low as possible.

Abstract: A method for extracting a clock in a clock data recovery system is provided. The method includes following steps. First, a serial link transmission data is sampled for a number of times, and a number of pulse signals are generated and sequentially arranged. Then, a mark is inserted after all pulse signals are generated and had been delayed for a predetermined delay time. The predetermined delay time is less than a period between two adjacent pulse signals, and a period between two adjacent pulse signals is divided into two sub-periods by the predetermined delay time. Then, it is checked whether the data status in each sub-period is changed or not, and this operation is repeated for a predetermined number of times. Finally, the clock is extracted when a pulse signal of no data status change within the predetermined number of times is being generated.

Abstract: A method for selecting a subsequence of video frames (72-84) from a sequence of video frames (70) comprising defining a distance function between video frames (72-84) in the sequence of video frames (70). An optimization criterion is defined to express a feature of a plurality of subsequences of video frames (72-84) selected from the sequence of video frames (70). A method is disclosed for displaying key frames for browsing and streaming.

Abstract: A communication apparatus (400) capable of supporting two bidirectional communication protocols is connected to a single bidirectional signal line and a controller (414). Software processes of the controller (414) include only processes of requesting transmission, setting transmission data, and decoding reception data. All communication processes, such as generation of a waveform during transmission, sampling of data during reception, decoding of a reception address, and the like, are hardware processes of the communication apparatus (400). In accordance with a control of a state determining circuit (405), the generation of a waveform during transmission is controlled by a transmission control circuit (409) and a data output circuit (111), while the sampling of data during reception and the decoding of a reception address are controlled by a waveform timing check circuit (407) and a reception control circuit (410).

Abstract: A method for the generation of binary signals (So1, So2, So3) which are out-of-phase with a control phase angle (?) which is continuously variable in relation to at least one synchronisation binary signal from a set of synchronisation binary signals (Si1, Si2, Si3) which have the same variable period, such as those creating rising and falling fronts of the out-of-phase signals (So1, So2, So3) by calculating at least one level switching time at least from rising or falling synchronisation fronts of the synchronisation binary signal (Si1, Si2, Si3) at least according to the control phase angle (?). According to the invention, at least one reference front is selected from the synchronisation fronts such that the time is as short as possible.

Abstract: A complementary optical wiring system has a transmitting circuit configured to combine a delayed signal obtained by delaying a digital electric input signal by a time shorter than a minimum pulse width of the digital electric input signal with the digital electric input signal to generate a first electric pulse signal synchronized with a rising edge of the digital electric input signal and a second electric pulse signal synchronized with a falling edge of the digital electric input signal, a first light-emitting element configured to convert the first electric pulse signal to a first optical signal, a second light-emitting element configured to convert the second electric pulse signal to a second optical signal, a first optical transmission path configured to transmit the first optical signal, a second optical transmission path configured to transmit the second optical signal, a first light-receiving element configured to convert the first optical signal transmitted through the first optical transmission path

Abstract: The timing synchronization module includes a phase locked loop (PLL) and a synchronization processing unit. The PLL receives an output-end clock signal. When the PLL receives the output-end clock signal for the first time, the PLL generates a reception-end clock signal according to the output-end clock signal. The synchronization processing unit receives a procedure clock signal and the reception-end clock signal. The output-end clock signal has M clocks after the reception-end clock signal is generated, while the reception-end clock signal has N clocks as generated. When the difference value of M and N is larger than a preset value, the synchronization processing unit removes the media signal corresponding to the procedure clock signal and generates the reception-end clock signal again. When the difference value is smaller than the preset value, the synchronization processing unit controls media signal playing according to the reception-end clock signal and the procedure clock signal.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: A receiver in an impulse wireless communication. The receiver (300) includes a pulse-pair correlator (304) that receives a signal (316) and divides it into two signals for paths. One of the signals is input to signal multiplier (312) while another signal is delayed by a delay unit (310). The signal multiplier (312) multiplies the received signal (316) by a delayed signal (318). An integrator (314) integrates an output signal (322) over a designated period of time. An adding module (306) sums an output signal (324) from the integrator (314). An acquiring module (308) compares an summing-up output (326) from the adding module (306) with a predetermined threshold value to detect the existence of a transmitting-standard preamble.

Abstract: A method for extracting a clock in a clock data recovery system is provided. The method includes the following steps. First, a serial link transmission data is sampled for a plurality of times, and a plurality of pulse signals are generated and sequentially arranged. Then, a mark is inserted after all pulse signals are generated and had been delayed for a predetermined delay time. The predetermined delay time is less than a period between two adjacent pulse signals, and a period between two adjacent pulse signals is divided into two sub-periods by the predetermined delay time. Then, it is checked whether the data status in each sub-period is changed or not, and this operation is repeated for a predetermined number of times. Finally, the clock is extracted when a pulse signal of no data status change within the predetermined number of times is being generated.

Abstract: In an apparatus and method for checking a network synchronization clock signal in a communication system, the apparatus generates a divided clock signal which is the same as an externally inputted network synchronization clock signal, compares the value of one period of the network synchronization clock signal to the value of one period of the divided clock signal, and determines whether the network synchronization clock signal is normal or not. Thus, the reliability of an operation of checking the network synchronization clock signal is enhanced.

Abstract: A clock recovery circuit comprising an initial delay select circuit, a delay locked loop and a clock synthesizer circuit is provided. The initial delay select circuit comprises an initial timing generator, a first multiplexer and an initial value generator. The delay locked loop comprises a delay chain, a phase detector, a counter, and a decoder circuit. The delay locked loop delays an input clock signal to generate a first delay signal and several unit delay signals. The initial value generator receives the unit delay signals to generate an initial value used as an initial counting value of the delay locked loop to prevent harmonic lock. The delay locked loop controls the phase difference between the input clock signal and the first delay signal. The output clock signal of the clock recovery circuit is generated by the clock synthesizer circuit based on the input clock signal and the first delay signal.