With Transition Detector Patents (Class 375/360)
  • Publication number: 20090122935
    Abstract: A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock signal is also accepted at a second rate. The clock signal is a timing reference recovered from the raw data signal. The raw data signal is sampled at a rate responsive to the clock signal, generating a sampled signal. Edge transitions are counted in the sampled signal, creating a sampled count. Then, the raw count is compared to the sampled count, to determine if the first rate is equal to the second rate. The method is used to determine if the second rate is less than the first rate—to detect if the clock signal is incorrectly locked to the first rate.
    Type: Application
    Filed: November 9, 2007
    Publication date: May 14, 2009
    Inventors: Simon Pang, Viet Linh Do, Mehmet Mustafa Eker
  • Publication number: 20090122936
    Abstract: A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges.
    Type: Application
    Filed: January 15, 2009
    Publication date: May 14, 2009
    Inventors: David Wills Milton, Jason Edward Rotella
  • Publication number: 20090116598
    Abstract: A data clock frequency divider circuit includes a training decoder and a frequency divider. The training decoder outputs a clock alignment training signal, which is indicative of the start of a clock alignment training, in response to a command and an address of a mode register set. The frequency divider, which is reset in response to an output of the training decoder, receives an internal data clock to divide a frequency of the internal data clock in half. The data clock frequency divider circuit secures a sufficient operating margin so that a data clock and a system clock are aligned within a pre-set clock training operation time by resetting the data clock to correspond to a timing in which the clock training operation starts, thereby providing a clock training for a high-speed system.
    Type: Application
    Filed: December 27, 2007
    Publication date: May 7, 2009
    Inventors: Kyung-Hoon Kim, Yung-Ki Kim, Dae-Han Kwon, Taek-Sang Song
  • Publication number: 20090116593
    Abstract: Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.
    Type: Application
    Filed: January 6, 2009
    Publication date: May 7, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: HAYDEN C. CRANFORD, JR., GARETH JOHN NICHOLLS, BOBAK MODARESS-RAZAVI, VERNON R. NORMAN, MARTIN L. SCHMATZ
  • Publication number: 20090092212
    Abstract: A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a clock signal, a first pre-data and a second pre-data, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding of the first pre-data and the second pre-data, and a timing controller to delay the transition time point of the clock signal with a delay phase which generates the sampling control signal.
    Type: Application
    Filed: January 30, 2008
    Publication date: April 9, 2009
    Applicant: TLI INC.
    Inventor: Jae Gan KO
  • Publication number: 20090086869
    Abstract: Disclosed are a method and system for receiving a tag signal in a Radio Frequency Identification (RFID) reader. The method includes generating an edge signal using a tag signal received from an RFID tag; extracting edge information from the generated edge signal, and generating an edge clock corresponding to the extracted edge information; and determining bit data with respect to the tag signal using the generated edge clock.
    Type: Application
    Filed: June 27, 2008
    Publication date: April 2, 2009
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Ji-Hoon Bae, Hee Sook Mo, Donghan Lee, ChengHao Quan, Gil Young Choi, Cheol Sig Pyo
  • Publication number: 20090074123
    Abstract: A stream of data may flow over a fiber or other medium without any accompanying clock signal. The receiving device may then be required to process this data synchronously. Embodiments describe clock and data recovery (CDR) circuits which may sample a data signal at a plurality of sampling points to partition a clock cycle into four phase regions P1, P2, P3, and P4 which may be represented on a phase plane being divided into four quadrants. A relative phase between a data signal transition edge and a clock phase may be represented by a phasor on the phase plane. The clock phase and frequency may be adjusted by determining the instantaneous location of the phasor and the direction of phasor rotation in the phase plane.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Inventors: Yu-Li Hsueh, Miaobin Gao, Chien-Chang Liu
  • Patent number: 7505541
    Abstract: The multi-mode phase and data detector includes a phase detector and a charge pump. A plurality of latching blocks clocked on complimentary phases of a feedback signal produces a plurality of phase and transition signals. Based on a selectable bias level, latched comparators in the latching blocks operate to detect the multi-level input data signal as it crosses a plurality of threshold levels. Logic within the multi-mode phase and data detector selects subsets of exclusive OR gates from sets of exclusive OR gates and subsets of the latching comparators to place the multi-mode phase and data detector in one of a PAM-4, NRZ, or PRML mode of operation. The logic further selects subsets of latched comparators from the plurality of parallel coupled latches to further define the mode of operation of the multi-mode phase and data detector.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: March 17, 2009
    Assignee: Xilinx, Inc.
    Inventors: Brian T. Brunn, Firas N. Abughazaleh
  • Patent number: 7502434
    Abstract: A frequency detector and frequency-locked loop suitable for use in a clock recovery circuit are disclosed. The detector is linear, and can be used in implementing a loss of lock indicator. Variable delay filtering permits the frequency detector to be less sensitive to data fluctuations, and random or pseudo random addition of jitter helps address low gain in the data stream. A VCO controller cycles through a number of control states and provides varying levels of gain, dither and delay during each of the control states.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: March 10, 2009
    Assignee: Silicon Laboratories Inc.
    Inventors: Eric T. King, Douglas Pastorello
  • Patent number: 7489754
    Abstract: A frequency-lock detector (FLD) adapted to register more than one target count per period of a target clock signal to generate a count value related to a frequency difference between the target clock signal and a reference clock signal. In various embodiments of the invention, this count registration is implemented by multiplying the target clock signal, discerning two or more phases of a signal, and/or organizing a count pipeline. In a representative embodiment, an FLD of the invention has a counter circuit and a control circuit. The counter circuit has (i) a frequency multiplier adapted to multiply the frequency of the target clock signal to generate a multiplied signal, (ii) two target counters adapted to register counts based on occurrences of two different phases of the accelerated signal to generate two auxiliary numbers, and (iii) a multiplexer adapted to select an appropriate one of the auxiliary numbers as the count value related to the frequency difference.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: February 10, 2009
    Assignee: Agere Systems Inc.
    Inventors: Xingdong Dai, Max J. Olsen, Lane A. Smith
  • Patent number: 7477713
    Abstract: Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: January 13, 2009
    Assignee: International Business Machines Corporation
    Inventors: Hayden C. Cranford, Jr., Gareth John Nicholls, Bobak Modaress-Razavi, Vernon R. Norman, Martin L. Schmatz
  • Publication number: 20080310571
    Abstract: A method of encoding data and timing information on a single line comprising: asserting a first edge on the single line to encode said timing information; asserting a second edge on the single line a selectable time period after said first edge, said selectable time period representing said data, characterised in that: said step of asserting said first edge comprises supplying a clock signal to a clock input of a flip-flop; and the step of asserting the second edge comprises supplying the output of the flip-flop to an input of a programmable delay line having a data input connected to receive said data and an output connected to a reset input of the flip-flop, whereby an output of the flip-flop provides said encoded data and timing information on the single line.
    Type: Application
    Filed: December 16, 2005
    Publication date: December 18, 2008
    Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventor: Robert G. Warren
  • Patent number: 7466969
    Abstract: A MIMO receiver, a MIMO reception method and a wireless communication system capable of accurate MMSE control even when each transmit antenna uses a different chip power ratio in MIMO filter reception. A correction coefficient calculator receives as input the chip power ratio of each transmit antenna, and estimates such pilot power that renders the chip power ratio of each transmit antenna equal to that of a reference transmit antenna. Thereby, the correction coefficient calculator calculates a correction coefficient ?m to correct the actual pilot power of each transmit antenna. A weight calculator receives as input transmission channel impulse responses transferred into frequency domain by FFT sections, chip noise power estimated by a chip noise estimation section, and the correction coefficient ?m obtained by the correction coefficient calculator. The weight calculator calculates filter weights according to the minimum mean square error (MMSE) criterion.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: December 16, 2008
    Assignee: NEC Corporation
    Inventors: Masayuki Kimata, Shousei Yoshida
  • Patent number: 7466783
    Abstract: Embodiments of the invention relate to a method and system to implement a DDR interface, such as a high-speed encode/decode interface. In one embodiment, a method of encoding data comprises the acts of (1) receiving a first signal, a second signal, and a first clock signal common to the first and second signals; (2) detecting rising edges and falling edges of the first clock signal; and (3) generating a composite signal based at least in part on the first and second signals and the detected rising and falling edges. The composite signal is associated with a second clock signal that is generated based at least in part on the detected rising and falling edges and on a time delay relative to the first clock signal.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: December 16, 2008
    Assignee: Lexmark International, Inc.
    Inventors: Earl L. Fugate, Jason K. Young
  • Patent number: 7453970
    Abstract: Provided are a clock signal selecting apparatus and method that can guarantee the continuity of an output clock signal. The clock signal selecting apparatus and method can synchronize the phases of at least two clock signals by continuously controlling the phases of the clock signals. Accordingly, even when an active clock signal and a standby clock signal have different frequencies, it is possible to guarantee the continuity of the output clock signal regardless of whether the clock signals are switched from one to another. In addition, it is possible to guarantee the stability of the output clock signal.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: November 18, 2008
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Tae Sik Cheung, Bhum Cheol Lee, Bong Tae Kim
  • Publication number: 20080267330
    Abstract: The feedback of reinterleaved correctly decoded data blocks to a decoder is provided for use in channel decoding operations of channel coded word containing data block. Once a properly decoded data block has been determined, feedback of constraints on the estimated bit sequences decoded data characteristics to a turbo decoder assist in additional decoding operations. Estimated bit sequences may be selected from those trellises that pass through the constraint imposed by knowledge of re-interleaving properly decoded data blocks. This allows the decoder to generate solutions having a minimum probability of error that are also confined by the re-interleaved properly decoded data blocks.
    Type: Application
    Filed: April 26, 2007
    Publication date: October 30, 2008
    Inventors: Arie Heiman, Arkady Molev-Shteiman
  • Patent number: 7434084
    Abstract: A synchronous bit-serial data interface utilizes a transmitter that transmits a data stream having duplicates of each data bit. The receiver samples the data stream utilizing either the rising or falling edge of a received clock signal. If the rising edge is utilized the first duplicated bit is discarded and if the falling edge is utilized the second duplicated bit is discarded. The system allows transmitter/receiver pairs of devices that sample and latch data on the same clock edge to communicate.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: October 7, 2008
    Assignee: Cisco Technology, Inc.
    Inventors: Cornel Yau, John Ly, Tong Tang
  • Patent number: 7424059
    Abstract: A transmission unit loads transmission data on a first register and outputs it to a transfer line and starts counting the transmission clock signals in a strobe generation counter according to a transmission clock signal. When the counted value reaches a set value, a strobe signal is output. A reception unit loads the transfer data onto a second register according to a reception clock signal. An edge detection unit generates a valid signal with a pulse width corresponding to one cycle of the reception clock signal when the strobe signal is detected. A third register loads the data that is output from the second register, and outputs it as reception data according to the reception clock signal when the valid signal is supplied.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: September 9, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Atsuhiko Okada
  • Patent number: 7424046
    Abstract: A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: September 9, 2008
    Assignee: Altera Corporation
    Inventors: Adam L. Carley, Daniel J. Allen
  • Patent number: 7424077
    Abstract: A channel detector has an anchor points inserter, a desired signal calculator, a distance calculator and a data detector. The anchor points inserter is adapted to choose values of expected transition locations for transition shifts within a received signal and to insert anchor points corresponding to the chosen values within a bit detection interval. The desired signal calculator is coupled to the anchor points inserter and is adapted to estimate desired signals corresponding to transition location information from the anchor points inserter. The distance calculator is coupled to the desired signal calculator and is adapted to generate a distance calculator output based on distances between the received signal and each of the desired signals. The data detector is coupled to the distance calculator and is adapted to identify a bit sequence corresponding to a desired signal having a minimum distance from the received signal.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: September 9, 2008
    Assignee: Carnegie Mellon University
    Inventors: Xueshi Yang, Erozan Mehmet Kurtas, Rohit Negi, Xun Zhang
  • Patent number: 7421029
    Abstract: A method for receiving at a receiver having a variable filter a transmitted signal that includes a periodic training signal. The method includes (a) receiving and sampling the transmitted signal at the receiver to produce a digital complex baseband signal; (b) filtering the digital complex baseband signal with the variable filter; (c) detecting the periodic training signal in the filtered digital complex baseband signal; (d) determining a desired channel impulse response based on the detected periodic training signal; (e) calculating filter coefficients required by the variable filter to achieve the desired channel impulse response; and (f) adjusting the variable filter according to the calculated filter coefficients. A receiver for implementing the method is also provided.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: September 2, 2008
    Assignee: Unique Broadband Systems, Inc.
    Inventors: Ambighairajah Yasotharan, Dmitri Korobkov
  • Publication number: 20080198957
    Abstract: A verification apparatus that can verify a circuit in a shorter time while taking possible metastability into consideration. A clock domain crossing (CDC) detector finds CDC paths between circuit elements operating with different clocks in the circuit. A delay generator inserter produces a delay-insertable version of the circuit by embedding a delay generator into each found CDC path. When activated, those delay generators give a signal delay to the corresponding CDC paths. A simulator simulates the behavior of the delay-insertable circuit by using a specified simulation pattern while deactivating the embedded delay generators. A delay pattern generator creates a delay pattern from simulation results, which activates or deactivates delay generators individually so as to produce signal delays that could affect output signals of the circuit. A verifier verifies the circuit by applying the delay pattern to each delay generator in the circuit.
    Type: Application
    Filed: January 22, 2008
    Publication date: August 21, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Satoshi KOWATARI
  • Patent number: 7415089
    Abstract: A system for clock and data recovery (“CDR”) includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a confidence counter, and a multiplexer outputting recovered data. The clock generator generates an 8-phase clock signal at half a rate of the transmitted serial data. The phase detector samples input data at four times the standard sampling rate, takes the oversampled data and detects phase transitions therein, i.e., phase lead and lag. The encoder encodes the phase transition data. The confidence counter receives the phase transition data and generates a signal representing the accumulated net effect of the phase transitions. The phase selector receives the confidence counter signal and the 8-phase clock from the clock generator, and determines the optimum phase for data sampling.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: August 19, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Chau-chin Su, Chien-Hsi Lee, Hung-Wen Lu, Hsueh-Chin Lin, Yen-Pin Tseng, Chia-Nan Wang, Uan-Jiun Liu
  • Patent number: 7412016
    Abstract: A circuit for adjusting the phase of a clock signal. A first sampling circuit generates a sequence of data samples in response to transitions of the clock signal, each of the data samples having either a first state or a second state according to whether an incoming signal exceeds a first threshold. An second sampling circuit generates an error sample in response to one of the transitions of the clock signal, the error sample having either the first state or the second state according to whether the incoming signal exceeds a second threshold. A phase adjust circuit adjusts the phase of the clock signal if the sequence of data samples matches a predetermined pattern and based, at least in part, on whether the error sample has the first state or the second state.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: August 12, 2008
    Assignee: Rambus Inc.
    Inventor: Vladimir M. Stojanovic
  • Publication number: 20080170650
    Abstract: The time-scale of a digital signal is efficiently modified. A system suitable for embedded or stand-alone processing includes a module that can transform the time-scale of the signal according to a user's preference. An improved method for time-scale modification is based on envelope-matching but introduces a new function that is very fast to compute, the use of which avoids the computation of correlation coefficients where they are not needed. The invention is demonstrably faster than other methods related to SOLA (synchronized-overlap-and-add) with envelope matching, yet with no sacrifice in quality of the processed output.
    Type: Application
    Filed: January 11, 2007
    Publication date: July 17, 2008
    Inventor: Edward Theil
  • Patent number: 7397878
    Abstract: The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method includes: a step of encoding data of N bits (N being 2 or larger) to transmission data of M bits (M being 3 or larger) on a transmission side; a step of generating a transmission signal in which transition takes place in at least one level of any of the transmission data synchronously with a transmission clock and transmitting the transmission signal to a transmission line on the transmission side; a step of recognizing transition in the signal of M bits received via the transmission line and detecting the reception data of M bits synchronized with the transmission clock on a reception side; and a step of decoding the reception data of M bits to the data of N bits.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yuichi Okuda, Takeshi Sakata, Takashi Sato
  • Patent number: 7397876
    Abstract: Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: July 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Hayden Clavie Cranford, Jr., Gareth John Nicholls, Vernon Roberts Norman, Martin Leo Schmatz, Karl David Selander, Michael Anthony Sorna
  • Patent number: 7397879
    Abstract: The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method includes: a step of encoding data of N bits (N being 2 or larger) to transmission data of M bits (M being 3 or larger) on a transmission side; a step of generating a transmission signal in which transition takes place in at least one level of any of the transmission data synchronously with a transmission clock and transmitting the transmission signal to a transmission line on the transmission side; a step of recognizing transition in the signal of M bits received via the transmission line and detecting the reception data of M bits synchronized with the transmission clock on a reception side; and a step of decoding the reception data of M bits to the data of N bits.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yuichi Okuda, Takeshi Sakata, Takashi Sato
  • Patent number: 7382845
    Abstract: Systems and methods are described for distribution of synchronization in a packet switched local area network environment. A method for extracting network synchronization timing from a data transmission burst includes: recovering a clock during the data transmission burst; and then holding over the clock after the data transmission burst ceases. A method for inserting network synchronization timing into a data transmission burst includes encoding data using a time-base reference signal governed clock.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: June 3, 2008
    Assignee: Symmetricom, Inc.
    Inventor: Kishan Shenoi
  • Publication number: 20080117952
    Abstract: Existing message fields and/or message parameters are configured to facilitate the packet and message synchronization and decoding tasks that conventionally rely upon a known bit sequence in each packet, thereby eliminating the need for a predefined message preamble in each packet. In example embodiments, the unique identifier of each transmitter is structured to facilitate determination of bit polarity and the start of each packet; packet sequence numbers use an unconventional counting sequence to assure synchronizing bit transitions; and so on. Other techniques, such as the use of run-length limited (RLL) message encoding, or 8b/10b encoding, to assure within-packet bit transitions, are also used to enhance clock synchronization and proper header location determination.
    Type: Application
    Filed: November 7, 2007
    Publication date: May 22, 2008
    Inventor: Luis G. JORDAN
  • Patent number: 7372931
    Abstract: A bus data signal is applied to a tapped data delay line. The various increasingly delayed data values present at the taps of the delay line are clocked into respective cells of a sticky ZEROs register (SZERO) previously initialized to all ONES, and into respective cells of a sticky ONES (SONE) register previously initialized to all ZEROS. SZERO measures the unit interval of a ONE.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: May 13, 2008
    Assignee: Agilent Technologies, Inc.
    Inventor: Glenn Wood
  • Publication number: 20080107220
    Abstract: In accordance with a detection method in a wireless communication system, an initial hypothesis for a starting position of a desired signal within a received wireless communication signal may be determined. The desired signal may have a conjugate symmetric property. At least one correlation value may be determined based on the initial hypothesis. The at least one correlation value may indicate the extent to which at least one sample sequence selected from the received signal has the conjugate symmetric property.
    Type: Application
    Filed: October 26, 2007
    Publication date: May 8, 2008
    Applicant: QUALCOMM INCORPORATED
    Inventors: Ju Won Park, Jong Hyeon Park, Je Woo Kim
  • Publication number: 20080101517
    Abstract: This invention samples and transmits the CEA-909 standard smart antenna analog pulse train waveforms using only a digital I/O pin for both mode A and mode B operation. This invention implements the smart antenna interface based on a single digital programmable counter. This counter is programmable so that it can tolerate or produce wide variation of symbol width.
    Type: Application
    Filed: October 31, 2007
    Publication date: May 1, 2008
    Inventors: Towfique Haider, Kazunobu Shin
  • Patent number: 7362837
    Abstract: A clock signal is deskewed relative to a data signal by sweeping a sampling point in time and sweeping an amplitude offset. Bit error measurements are made at each sampling point in time and compared. Bit error measurements may be made by comparing received data to predetermined data values. The predetermined data values may be sourced from a linear feedback shift register.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: April 22, 2008
    Assignee: Intel Corporation
    Inventors: James E. Jaussi, Bryan K. Casper, Ganesh Balamuragan, Stephen R. Mooney
  • Patent number: 7359471
    Abstract: The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method includes: a step of encoding data of N bits (N being 2 or larger) to transmission data of M bits (M being 3 or larger) on a transmission side; a step of generating a transmission signal in which transition takes place in at least one level of any of the transmission data synchronously with a transmission clock and transmitting the transmission signal to a transmission line on the transmission side; a step of recognizing transition in the signal of M bits received via the transmission line and detecting the reception data of M bits synchronized with the transmission clock on a reception side; and a step of decoding the reception data of M bits to the data of N bits.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: April 15, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yuichi Okuda, Takeshi Sakata, Takashi Sato
  • Patent number: 7356108
    Abstract: A channel estimator is configured for determining a gain adjustment for a received wireless signal having a prescribed plurality of tones. The channel estimator is configured for generating, for each of the tones, a corresponding pseudo power value representing a detected power level for the corresponding tone. An accumulated pseudo power value is obtained based on accumulating the respective pseudo power values of the prescribed plurality of tones. Each of the pseudo power values is selectively adjusted by an adjustment factor based on a determined difference between the accumulated pseudo power value relative to an expected accumulated power level relative to a prescribed dynamic range. The pseudo power values are then output for decoding of data modulated at the respective tones.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: April 8, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ping Hou, Harish Kutagulla
  • Patent number: 7352771
    Abstract: A data collision detection device that includes a means for de-modulating at least one carrier signal corresponding to a received modulated subcarrier signal from at least one data transmitter to recover the subcarrier signal from the carrier signal. A microcontroller is operatively connected with the means for recovering a subcarrier signal. The microcontroller includes a means for decoding a recovered subcarrier signal. The means for decoding the recovered subcarrier signal is capable of interpreting signal transitions in the recovered subcarrier signal, and is capable of detecting data collisions in the recovered subcarrier signal when in the presence of a plurality of modulated subcarrier signals.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: April 1, 2008
    Assignee: Colder Products Company
    Inventor: Richard Stewart Garber
  • Patent number: 7349510
    Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: March 25, 2008
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Richard E. Warmke, David B. Roberts, Frank Lambrecht
  • Patent number: 7349509
    Abstract: A clock and data recovery device (CDR) based on multi-rate multi-phase oversampling technique is capable of receiving serial data streams of different data rates. The CDR uses a multi-rate multi-phase oversampling technique. N phase shifted clocks are generated based on a single clock and rising edges (or falling) of the phase shifted clocks and define N sampling points where a serial data stream is sampled. The multi-phase oversampling technique provides at least two sampling points per data bit of the serial data stream at highest data rates. The sampling points divide one clock cycle of the single clock into N zones. Depending on which of the zones a data edge transition is detected, the CDR can converge the sampling points to optimal data sampling positions in the serial data stream.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: March 25, 2008
    Assignee: Kawasaki LSI U.S.A., Inc.
    Inventors: Jerome Ribo, Benoit Roederer
  • Patent number: 7342969
    Abstract: At least two sequences of predetermined reference times are established on respective ones of at least two communication lines. At least some of the reference times of at least one of the sequences occur out-of-phase with at least some of the reference times of another of the sequences. Digital data is encoded onto data signals on one or more communication lines such that a time difference between at least one of the data signals and the nearest one of the reference times on one of the communication lines is smaller than the time difference between the same data signal and the nearest one of the reference times on another one of the communication lines.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: March 11, 2008
    Assignee: Intel Corporation
    Inventors: Larry R. Tate, Timothy D. Wig
  • Patent number: 7321617
    Abstract: A data communication system includes circuitry to assure components respond to variations in the time length of the valid data window or “eye” of the high speed data communication signal. A self-test portion of the system periodically injects the effects of phase jitter into the data communication signal to assure the system performs properly.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: January 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Jon David Garlett, Victor Moy, Michael A. Sorna
  • Patent number: 7321647
    Abstract: In a clock extracting circuit according to the present invention, after serial data is subjected to oversampling using a reference clock of 2N times a frequency of the serial data, clock timing in a period of time in which signal level remains unchanged for a long duration is extracted. Clock timing based on a point of change in the signal level is also extracted, and a final clock timing signal is outputted according to these timings detected. Thus, clock timing can be extracted accurately without omission even when the input signal includes jitter. Further, the clock extraction is performed without converting the input signal into parallel data and by simple processing. A clock extracting circuit for extracting a clock signal from the received serial data with high accuracy is thus realized without increasing the circuit scale.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: January 22, 2008
    Assignee: Sony Corporation
    Inventor: Kouji Matsuura
  • Patent number: 7319730
    Abstract: The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method includes: a step of encoding data of N bits (N being 2 or larger) to transmission data of M bits (M being 3 or larger) on a transmission side; a step of generating a transmission signal in which transition takes place in at least one level of any of the transmission data synchronously with a transmission clock and transmitting the transmission signal to a transmission line on the transmission side; a step of recognizing transition in the signal of M bits received via the transmission line and detecting the reception data of M bits synchronized with the transmission clock on a reception side; and a step of decoding the reception data of M bits to the data of N bits.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: January 15, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yuichi Okuda, Takeshi Sakata, Takashi Sato
  • Patent number: 7317489
    Abstract: A technique to provide a cost effective solution to detect teletext data that can reduce detected error in teletext when the transmission data rate is known. In one example embodiment, this is accomplished by detecting data bits in an unsynchronized digital data stream by finding start of each data bit based on an estimated data bit width and transitions in the unsynchronized digital data stream.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: January 8, 2008
    Assignee: Analog Devices, Inc
    Inventors: Amogh D. Thaly, Nilesh Bhattad, Rajesh Bhaskar, Sudheesh A S
  • Patent number: 7317775
    Abstract: A method and circuit capable of handling skew between a clock and data signal up to +/? one half bit on a random input data pattern. A digital algorithm cycles through each data bit and individually deskews that bit by detecting data transitions in a first sampling region and in a second sampling region and determining a difference between a number of transitions in the first sampling region and a number of transitions in the second sampling region. The sampling regions and a deskew timing signal may then be incremented or decremented based on a comparison of the computed difference to a predetermined constant. If no transitions occur on a particular bit, the algorithm times out leaving the deskew timing signal in the original position. When analysis of a final bit of a channel is completed, the algorithm begins monitoring and analyzing the first bit of another channel.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: January 8, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Richard Alexander Erhart, Loren Tomasi, Mark D. Kuhns, Arif Alam
  • Publication number: 20070297550
    Abstract: In a method for reducing electromagnetic interference in a clocked circuit, the clock circuit includes at least a first clock signal and a second clock signal. The method detects when a first transition of the first clock signal is substantially aligned with a corresponding second transition of the second clock signal. The second clock signal is delayed by a predetermined amount of time when the first transition is substantially aligned with the second transition.
    Type: Application
    Filed: June 22, 2006
    Publication date: December 27, 2007
    Inventor: Don A. Gilliland
  • Patent number: 7310400
    Abstract: A data recovery device. The device adjusts a digital signal according to a pulse signal output by a phase-locked loop circuit. The sampling circuit samples each bit of the digital signal five times to generate a first sampled signal. The data delay buffer decides a sampling range of the first sampled signal and outputs a second sampled signal. The sampling range selector picks a part of bits of the second sampled signal and outputs output data. The weighted detecting module outputs a phase shifting signal responding to the output data. The first loop filter outputs a first adjusting signal. The first sampling window module outputs a phase selecting signal. The second loop filter outputs the recovery signal and a second adjusting signal. The second sampling window module outputs the first phase checking signal and the second phase checking signal. The phase picking module outputs the output data.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: December 18, 2007
    Assignee: Realtek Semiconductor Corp.
    Inventor: Yi-Shu Chang
  • Patent number: 7308048
    Abstract: A clock recovery circuit samples an incoming data stream that includes sequences of signal transitions. A transition detector categorizes the received signal transitions into various types, such as those associated with 2PAM and 4PAM signaling schemes. Select logic control circuitry analyzes the signal-transition types to determine which of the transition types is best suited for clock recovery. This determination relies upon a number of factors, including for example whether the received signal is a 4PAM signal or a 2PAM signal, the existence of a pattern within the received data, or the relative abundance or scarcity of certain types of transitions.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: December 11, 2007
    Assignee: Rambus Inc.
    Inventor: Jason Wei
  • Patent number: 7284141
    Abstract: A sampling system is disclosed which measures high speed data signals by performing sampling events at intervals determined by a programmable DDS output frequency and a programmable counter. The reference frequency of the DDS is that of a clock signal that is synchronous with the data signal to be measured. The present invention is able to arrange the sample points to form an eye diagram of the input signal. In addition, the present invention is capable of sampling synchronously with the data clock and controlling the phase of the synthesized signal such that the samples are localized around the rising and falling edges of the data waveform. The present invention is thereby able to determine the location of the edges of the data signal and analyze the deterministic jitter of the waveform.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: October 16, 2007
    Assignee: Anritsu Company
    Inventor: Kyle Stickle
  • Patent number: 7265690
    Abstract: The present invention facilitates data recovery without requiring selection of a sample phase. The data is recovered by sampling a received signal to obtain a number of samples at a number of phases over a given time period referred to as a bit time. The samples are analyzed to determine if a transition has occurred in one or more consecutive phases. Such a transition is also referred to as a data toggle. Generally, one or more toggles in a single bit time indicate one data value (e.g., a zero) whereas no transitions indicate another data value (e.g., a one).
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: September 4, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Suzanne Mary Vining