With Transition Detector Patents (Class 375/360)
  • Patent number: 7257173
    Abstract: A description of signal behavior in the vicinity of a time and voltage of interest is produced by defining a region in the (time, voltage) plane that is a closed straight sided figure whose vertices are identified by threshold crossings offset for the voltage of interest and clocked by time delays offset from a clock time of interest. A first set of latches clocked by the time delays accumulates the state of signal behavior relative to the threshold voltages as it occurs, and their contents are subsequently transferred to a second set of latches at the start of a new clock cycle, allowing a new accumulation to begin and also allowing a detection logic circuit to operate on a unified and completed collection of indicators of what the just concluded description amounts to. The detection logic circuit responds to the combinations of latched indications to produce a signal corresponding to that description.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: August 14, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Glenn Wood, David D. Eskeldson
  • Patent number: 7242735
    Abstract: A data recovery system and method is disclosed, which comprises an oversampler, a phase detection circuit, a data pick circuit, a data overlap/skip detection circuit and a data correction circuit. The oversampler oversamples an input signal and thus generates oversampled signals. The phase detection circuit receives for detecting transitions of the oversampled signals and outputting a phase signal. The data pick circuit receives the phase signal, accordingly groups the oversampled signals into n groups and picks one group as an output data. The data overlap/skip detection circuit determines if data is overlapped or skipped according to the phase signal and the last phase signal. The data correction circuit corrects data when data is overlapped or skipped and outputs an accurate output data.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: July 10, 2007
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chao-Hsin Lu, Yi-Shu Chang, Shiu-Rong Tong, Kuang-Hsi Hsieh
  • Patent number: 7239813
    Abstract: A bit synchronization circuit composed of a multiphase data sampling unit for converting each received burst data sets to multiphase data trains, a phase determination unit for generating a control signal indicating an optimum phase data train, an output data selector for selectively passing optimum phase data train indicated by the control signal, and a data synchronization unit for converting the optimum phase data train to a data train in synchronization with a reference clock. The phase determination unit repeatedly detecting the optimum phase data train during the same burst data set is received. When optimum phase varies, the output data selector dynamically switches the optimum phase data train to be supplied to the data synchronization unit.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: July 3, 2007
    Assignee: Hitachi Communication Technologies, Ltd.
    Inventors: Yusuke Yajima, Toshihiro Ashi, Tohru Kazawa
  • Patent number: 7236555
    Abstract: In a method for measuring jitter, a signal under test is inputted to generate signal transition locations. A signal transition location is latched using a sampling clock signal, and the signal transition location is converted to a delay value. The delay value is converted to an edge position output, and a value of the edge position output is detected.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: June 26, 2007
    Assignee: Sunrise Telecom Incorporated
    Inventor: Symon Brewer
  • Patent number: 7221725
    Abstract: A host interface includes transition detection circuitry, transition phase averaging circuitry, and bit stream sampling circuitry. The transition detection circuitry receives an incoming bit stream and a reference clock signal and detects transitions of the incoming bit stream with respect to the reference clock signal. The transition detection circuitry also determines relative phases of the transitions with respect to the reference clock signal. The transition phase averaging circuitry determines an average relative phase of the detected transitions with respect to the reference clock signal and also determines, based upon the average relative phase of the detected transitions with respect to the reference clock signal, a sampling phase with respect to the reference clock signal. The bit stream sampling circuitry samples the incoming bit stream at the sampling phase with respect to the reference clock signal to extract the bit values. The incoming bit stream may comply with the Universal Serial Bus 2.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: May 22, 2007
    Assignee: Sigmatel, Inc.
    Inventor: Darrell E. Tinker
  • Patent number: 7212580
    Abstract: Clock recovery of a multi-level (ML) signal can be performed in a two-step process. First, the transitions within the ML signal can be detected by a novel transition detector (TD). And second, the output of the TD circuit can comprise a pseudo-non-return-to-zero (pNRZ) signal that can drive a conventional OOK clock recovery (CR) IC. The TD circuit can convert the edges of the ML signal into the pseudo-NRZ (pNRZ) signal. The TD circuit can capture as many transitions as possible to allow the conventional NRZ clock recovery (CR) chip to optimally perform. The TD circuit can differentiate the ML signal in order to detect the ML signal's transitions.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: May 1, 2007
    Assignee: Quellan, Inc.
    Inventors: Vincent Mark Hietala, Andrew Joo Kim
  • Patent number: 7151811
    Abstract: This invention relates to an electronic circuit for decoding an asynchronous two-phase data signal. According to the invention, such an electronic circuit comprises means for generating a decoding clock using a counter powered by an internal clock, and repeating cycles including incrementation of the said counter until detection of a transition in the said data signal, followed by decrementing the said counter down to zero.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: December 19, 2006
    Assignee: Atmel Nantes SA
    Inventors: René Aubree, Raphaël Letendu
  • Patent number: 7149268
    Abstract: A digital subscriber line (DSL) driver allows a transmitter to monitor its own transmit spectrum at the subscriber loop and adjust the transmit spectrum based on detected line conditions, affected by the presence of bridged taps or any other impedance variations. The transmit spectrum is preferably equalized so that all carriers, or tones, transmit using the same power and exhibit the same margin. The invention is applicable to DMT and single carrier modulation formats.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: December 12, 2006
    Assignee: Paradyne Corporation
    Inventor: William L. Betts
  • Patent number: 7145973
    Abstract: A method for the reception of a signal comprising the following steps: 1) on the detection or reception of an edge in the received signal, a counting cycle Nc is activated, 2) when the value of Nc is equal to a number M of beeps of a generation clock Hg, a leading edge of the reception clock signal is sent and a new counting cycle Nc is activated, 3) when this new value of Nc is equal to a number M of beeps of a generation clock Hg, the clock Hr is made to pass to zero, and simultaneously 3.1) in the event of reception of an edge in the received signal, a new clock signal edge is sent when Nc=M, 3.2) in the event of non-reception in the received signal, a new clock signal edge offset by a value of 1(M+1) is sent when Nc=M, 4) the steps 1) and 2) are executed so long as the header is not detected, 5) upon the detection of a header, a Header Found signal is sent, the steps 1), 2), 3) and 3.1) are executed and this Header Found signal is transmitted at a processing step.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: December 5, 2006
    Assignee: Thales
    Inventor: Bruno Fievre
  • Patent number: 7120216
    Abstract: A data/clock recovery circuit can recover high-rate data using the data as a clock signal. It includes an edge detector, a clock selection signal generating circuit, a clock selection circuit and a synchronizing circuit. The edge detector generates edge position information using a receiver output as a clock signal. The clock selection signal generating circuit generates a clock selection signal in response to the edge position information using the receiver output as the clock signal. The clock selection circuit selects a recovered clock signal from a clock signal group in response to the clock selection signal. The synchronizing circuit synchronizes the receiver output using the recovered clock signal, and outputs it as a synchronized data signal.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: October 10, 2006
    Assignees: Renesas Technology Corp., Mitsubishi Electric System LSI Design Corporation
    Inventors: Hiroshi Shirota, Ryosuke Okuda, Katsuya Mizumoto, Kazuaki Tanida
  • Patent number: 7113562
    Abstract: Conventional receiver architectures are based on either frequency/phase tracking or oversampling. Both receiver types typically employ sensitive analog circuits, which create noise, consume power and utilize valuable space in their implementation. The invention adopts a novel approach to phase/frequency tracking that utilizes the edges or zero crossings of the input data waveform to effectively track the remote transmitter clock phase/frequency. This methodology minimizes the use of analog circuitry, thereby reducing the noise domain and the substrate space required for implementation of a tracking device.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: September 26, 2006
    Assignee: Intel Corporation
    Inventors: David S. Dunning, Chamath Abhayagunawardhana, Kenneth Drottar, Richard S. Jensen
  • Patent number: 7113560
    Abstract: A method and circuit to produce an optimal sampling phase for recovery of a digital signal is achieved. A digital signal is over-sampled by sampling on each phase of a multiple phase clock to generate a sample value per phase. The multiple phase clock may be generated by a DLL. A voted value is determined per phase comprising a majority value of a set of consecutive sample values. Transition phases are sensed. A transition phase is defined as two consecutive voted phases comprising different values. The transition phases are compared to a stored phase state to determine a signal shift direction. The signal shift direction is filtered to generate a state update signal. The stored phase state is updated based on the state update signal. The stored phase state corresponds to an optimal sampling phase for recovery of the digital signal.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: September 26, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mu-Jen Huang, Linhsiang Wei, Fu-Shing Ju
  • Patent number: 7095353
    Abstract: A technique of processing an input signal having an input signal phase is disclosed. The technique includes determining a number of transitions of the input signal within a period having a start and an end. The technique includes determining a relative beginning phase of the input signal at the start of the period, which includes generating a first reference signal having a first reference signal frequency and a first reference signal phase synchronized with the start of the period, and detecting a first time interval required for the input signal phase to have a first specified relationship to the first reference signal phase. The technique includes similarly determining a relative ending phase of the input signal at the end of the period. The technique includes determining an input signal temporal characteristic from the number of transitions and the relative beginning phase and the relative ending phase.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: August 22, 2006
    Assignee: Amalfi Semiconductor Corporation
    Inventors: Wendell Sander, Stephan V. Schell, Matthew Mow
  • Patent number: 7072630
    Abstract: A method and apparatus for determining the data rate of a reverse link communication of an access terminal includes receiving a reverse activity bit (RAB) from an access point in the communication system, and passing the RAB to a digital filter to produce a filtered RAB. In one embodiment, the reverse link data rate is determined based on the filtered value of the RAB. Furthermore, a processor in the access terminal may determine whether the access terminal is in an idle mode, and passing a non-busy state value of the RAB to the digital filter when the access terminal is in the idle mode. The filtered RAB may be compared to a threshold to determine a mode of reverse link data rate determination. The mode defines a set of criteria for an aggressiveness level of increasing or decreasing the reverse link communication data rate. The processor, therefore, determines the data rate based on the filtered reverse activity bit in accordance with the determined mode.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: July 4, 2006
    Assignee: Qualcomm, Inc.
    Inventors: Christopher Gerard Lott, Jean Put Ling Au
  • Patent number: 7068747
    Abstract: In a data decision circuit: a clock generation unit generates a clock signal based on a phase difference signal so that the clock signal has an optimum phase with respect to a phase of an input data signal; a data determination unit determines data values carried by the input data signal, by using the clock signal; a phase-difference detection unit detects a rising-side phase difference and a falling-side phase difference, where the rising-side phase difference is a phase difference between a rising of the input data signal and a next transition in the clock signal, and the falling-side phase difference is a phase difference between the transition and a next falling of the input data signal; and a phase-difference-signal generation unit generates the phase difference signal so as to represent a difference between the rising-side phase difference and the falling-side phase difference.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: June 27, 2006
    Assignee: Fuijtsu Limited
    Inventors: Hiroyuki Rokugawa, Tadashi Ikeuchi, Daisuke Yamazaki, Masaaki Kawai
  • Patent number: 7069037
    Abstract: A method and apparatus for determining the data rate of a reverse link communication of an access terminal includes receiving a reverse activity bit (RAB) from an access network in the communication system, and passing the RAB to multiple digital filters to produce filtered RABs. The reverse link data rate is determined based on these filtered values of the RABs. From the filtered RAB values a continuous fluid power level is determined each rate update. The access terminal maps the continuous fluid power level to actual physical transmissions by dithering among discrete power levels allowed by the physical layer.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: June 27, 2006
    Assignee: Qualcomm, Inc.
    Inventors: Christopher Gerard Lott, Jean Au, Rashid Ahmed Akbar Attar, Peter J. Black, Mingxi Fan, Naga Bhushan
  • Patent number: 7068649
    Abstract: An extended bandwidth HomePNA system uses a transmit spectrum having a greater bandwidth than the bandwidth specified by a HomePNA 2.0 communication standard. The extended bandwidth system of the invention provides for additional copies of a spectrum of a 2 Mbaud training signal for better accuracy in decoding transmitted data by a receiver. In one embodiment, the extended bandwidth is a 12 MHz band centered at 10 MHz, from 4 MHz to 16 MHz. This extended bandwidth allows for three copies of a 4 Mbaud training sequence or six copies of a 2 Mbaud training sequence. The extended bandwidth of the invention is compatible with a HomePNA 2.0 system by providing a training sequence that enables a HomePNA 2.0 receiver in 2 Mbaud mode to train on the transmitted signal and determine that the transmitted signal is not intended for the HomePNA 2.0 receiver in 2 Mbaud mode.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: June 27, 2006
    Assignee: 2Wire, Inc.
    Inventors: Kevin Fisher, Scott A. Lery, Andrew L. Norrell
  • Patent number: 7062003
    Abstract: The invention describes a baud rate generator for use in a sampled data system. This generator makes possible the sampling of asynchronous digital input data when its baud rate is not known, and does so without the use of phase-locked loop circuitry. The invention uses a digital counter to count the clock intervals between successive transitions in the digital input data. This process is repeated over a period of time sufficient to assure that recognizable recurring data patterns will occur in the data stream. The smallest interval recorded by the counter is captured and is directly related to the required sampling rate.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: June 13, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Roshan J. Samuel
  • Patent number: 7046754
    Abstract: A method for a user equipment (UE) to establish a communication link comprising the steps of receiving an input communication signal at an initial search frequency, processing the input communication signal to retrieve a primary scrambling code, the retrieval of the primary scrambling code being a code decision, and adjusting the search frequency of the UE in response to the code decision.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: May 16, 2006
    Assignee: InterDigital Technology Corporation
    Inventors: Alpaslan Demir, Donald M. Grieco
  • Patent number: 7046964
    Abstract: A method and apparatus provide for monitoring radio frequency signals and, in conjunction with the monitoring, determining frequency of a received dominant radio frequency signal. Zero amplitude transitions of the signal are counted in primary and secondary sampling periods to determine frequency and frequency stability. The method and apparatus can be used to tune to radio frequency signals having frequencies in a list of frequencies to be monitored and detecting signals in the radio frequency spectrum on other frequencies. The monitoring and scanning may occur simultaneously, sequentially, or in any order or sequence. The frequencies of dominant signals received are determined and added to the list for monitoring. The receiver may be tuned to a frequency determined immediately upon determination of the frequency determined, after storage of the frequency determined, only after a signal on the currently monitored frequency terminates, or upon other conditions.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: May 16, 2006
    Assignee: Counter Technologies, LLC
    Inventors: Terence Sean Sullivan, Terence Brennan, Richard Barnett
  • Patent number: 7035365
    Abstract: A receiver involved in high-speed data transmission includes a decision system. The decision system calculates a value of an input signal and holds the value as a tentative value. The decision system calculates an error value, amplifies the error value, and holds the amplified error value as a corrected value. The decision system determines whether the amplified error value is within a marginal range. The decision system also determines whether adjacent values to the value indicate the input signal was in transition from a positive to negative state, or a negative to positive state. If the amplified error values is within a marginal range and the input signal was in transition from a positive to negative state, or a negative to positive state, then the decision system overrides the tentative value with the corrected value.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: April 25, 2006
    Assignee: Intel Corporation
    Inventors: Hiroshi Takatori, James M. Little, Scott Chiu
  • Patent number: 7023943
    Abstract: A detector detects timing in a digital data flow with a bit-time equal to T. A first circuit generates four local timing signals each having periods substantially equal to the bit-time. Each of the four local timing signals are out of phase with one another by ¼ period. A second circuit samples the four local timing signals upon each transition of a first type for determining, based upon the sampling, whether two of the four local timing signals forming a pair of reference signals that are out of phase by ½ period are advanced or delayed relative to the timing of the data flow. The second circuit controls the first circuit for delaying or advancing the four local timing signals based upon the pair of reference signals.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: April 4, 2006
    Assignee: Stmicroelectronics S.r.l.
    Inventors: Jesus Guinea, Luciano Tomasini
  • Patent number: 7020227
    Abstract: A clock data recovery (CDR) circuit that can be used for recovering data from a high-speed serial transmission using components that operate at a fraction of the data speed. The CDR consists of a phase detector, an averaging circuit and a phase interpolator. The phase detector samples each data bit at its midpoint and at its transitional region and then compares the two samples to determine whether the sampling clock, which is generated by a phase interpolator, is leading or lagging the data stream. The averaging circuit filters out the high frequency jitters in the phase detector output and then passes the filtered signals on to the phase interpolator for phase selection. The phase interpolator uses the filtered signals from the averaging circuit as a guide in the selection of an output clock phase that minimizes the phase difference between the output clock and the incoming data.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: March 28, 2006
    Assignee: Acard Technology Corporation
    Inventors: David Y. Wang, Jyn-Bang Shyu, Yu-Chi Cheng
  • Patent number: 7020154
    Abstract: An information processing system contains a sender, a receiver and a communication channel coupled between the sender and the receiver. The communication channel transmits a first and second binary logic signal. The sender encodes data values and information distinguishing successive clock phases into a combination of the first and second signal. The receiver receives the data values and the information. The sender uses alternately a first and a second data dependent criterion to select which one of the first and second signal has a logic level change between immediately successive clock phases. As a result so that the first and second signal are alternately mutually opposite and mutually equal. The first criterion selects the level of the first signal dependent on the data value. The second criterion provides for a level change of either the first or the second signal depending on the data value.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: March 28, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Erik Van Der Ven
  • Patent number: 7006936
    Abstract: A pulse width measuring device is disclosed that calculates the pulse width of a signal to be measured, based on a count value and a count clock signal. In the pulse width measuring device, the counter circuit has a plurality of bits that are divided into an exponent and a significand. The control unit of the pulse width measuring device includes: an exponent storing unit that stores an exponent setting value that represents the number of bits of the exponent of the counter circuit; and a decoder unit that generates a count value setting signal for rewriting the count value of the counter circuit, based on the exponent setting value stored in the exponent storing unit, when the count value overflows in the counter circuit, the decoder unit then outputting the count value setting signal to the counter circuit.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: February 28, 2006
    Assignee: Fujitsu Limited
    Inventor: Satoshi Matsui
  • Patent number: 7003061
    Abstract: The invention provides methods and apparatus, including computer program products, implementing and using techniques for masking and extracting a foreground portion from a background portion of a digital image. In the method, a first input defining a first border region is received, which includes at least a part of the foreground portion and at least a part of the background portion in a first digital image. A second input defining a second border region is received, which includes at least a part of the foreground portion and at least a part of the background portion in a second digital image. An intermediary border region is interpolated for an image intermediary in time to the first and second digital images and the first, second, and intermediary border regions are used for masking the foreground portion from the background portion in the digital video.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: February 21, 2006
    Assignee: Adobe Systems Incorporated
    Inventor: Gregg D. Wilensky
  • Patent number: 6999544
    Abstract: The architecture and the method of operation of a receiver core are described. The core performs clock and data recovery on an incoming serial data stream transmitted across a wired media, such as a chip-to-chip or card-to-card interconnect. The bit error rate and accuracy of the recovery are optimized without centering of oversampling. Further, random errors due to edge mis-tracking are minimized. The receiver utilizes a phase rotator to detect the edge position of the bits of the data stream, select the optimum data sample and generate early and late signals if the detected edge is not in the expected position. A phase locked loop provides a frequency source for the phase rotator. At least three evenly spaced samples are detected for each bit. A sample processing algorithm, preferably an adaptive behavior algorithm, is used for centering the bit edge between two of the samples.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: February 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Hayden Clavie Cranford, Jr., Vernon Roberts Norman, Martin Leo Schmatz
  • Patent number: 6993105
    Abstract: A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal and a position of the first edge, (B) determining if the position is within a zone, (C) if the edge is not within the zone, adjusting the clock signal towards the position of the edge, (D) detecting a second edge of the data signal and a position of the second edge, (E) determining a in value indicating a position of the second edge, (F) adding the first value to a second value, wherein the second value indicates a position of a third edge of the data signal and (G) adjusting the clock signal based on the result of step (F).
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: January 31, 2006
    Assignee: Cypress Semiconductor Corp.
    Inventors: Terry D. Little, Bertrand J. Williams, Kamal Dalmia, Timothy D. Jordan
  • Patent number: 6975694
    Abstract: A digital subscriber line (DSL) driver allows a transmitter to monitor its own transmit spectrum at the subscriber loop and adjust the transmit spectrum based on detected line conditions, affected by the presence of bridged taps or any other impedance variations. The transmit spectrum is preferably equalized so that all carriers, or tones, transmit using the same power and exhibit the same margin. The invention is applicable to DMT and single carrier modulation formats.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: December 13, 2005
    Assignee: Paradyne Corporation
    Inventor: William L. Betts
  • Patent number: 6968197
    Abstract: In mobile communication systems employing the CDMA method, the communication quality is acquired from the CDMA pilot channel. A communication quality acquisition apparatus comprises a delay profile acquisition unit comprising a control unit, synchronization unit and measurement unit, in addition to a data storage unit. The communication quality is measured by the synchronization unit and the measurement unit which are alternatively controlled by the control unit. When the communication quality is acquired through the CDMA pilot channel, the data acquisition efficiency can be significantly raised.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: November 22, 2005
    Assignee: NTT DoCoMo, Inc.
    Inventors: Shinichi Mori, Tetsuro Imai, Yoshihiro Ishikawa, Mikio Iwamura
  • Patent number: 6950486
    Abstract: A delay apparatus delays a rising edge and a falling edge of a digital signal. The delay apparatus includes a first edge detection circuit which detects a first edge or rising edge of the digital signal and generates a detection signal; a set circuit that includes a first counter for generating a count value and clearing the count value in response to the detection signal, wherein the set circuit generates a set signal if the count value reaches the number of the reference clock signals corresponding to the delay period of time; a reset circuit which generates a reset signal if an elapsed period of time since a generation of the set signal equals a period of time the digital signal maintains the second logic level; and an output circuit that outputs a delayed digital signal including edges synchronized with the set signal and the reset signal.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: September 27, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Satoru Araki
  • Patent number: 6940931
    Abstract: Measuring gate pulse is generated that rises in synchronism with one of first and second clock signals and falls in synchronism with the other of the first and second clock signals. Then, a pulse width of the generated measuring gate pulse is measured by counting clock pulses higher in frequency than the first and second clock signals. When counted values indicative of respective pulse widths of an adjacent pair of the measuring gate pulses generated in succession coincide with each other, it is determined that the frequencies of the first and second signal are the same, but when the counted values of the adjacent pair of the measuring gate pulses do not coincide with each other, it is determined that the frequencies of the first and second signal are not the same.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: September 6, 2005
    Assignee: Yamaha Corporation
    Inventors: Tsugio Ito, Ryuuji Wakatsuki
  • Patent number: 6937682
    Abstract: In a clock-pulse supply unit, a first receiver unit is used to tap a central system clock pulse from the back panel. A time delay occurs in the first receiver unit. In order to compensate this time delay, a second receiver unit is used which is identical in construction to the first receiver unit and has the same time delay as the first receiver unit. A redundant clock pulse is supplied to the second receiver unit and thereby undergoes the same time delay as the central system clock pulse in the first receiver unit. The central system clock pulse and the redundant clock pulse can then be accurately compared with one another in a phase detector. The redundant clock pulse is then synchronized to the central clock pulse. The switchover from a slave clock pulse to the redundant clock pulse is effected only when synchronization is completed.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: August 30, 2005
    Assignee: Alcatel
    Inventors: Henning Höfs, Norbert Puschmann
  • Patent number: 6927604
    Abstract: A clock signal selector circuit is disclosed including a synchronizer circuit, two switching circuits, and a multiplexer. The synchronizer circuit synchronizes a first control signal to a first clock signal, thereby producing a second control signal. A first switching circuit produces the first clock signal at a first node when the second control signal is asserted. The multiplexer drives a second node with a signal at the first node when the second control signal is asserted. The second switching circuit forms an electrical connection between the first and second nodes when the second control signal is deasserted. The two switching circuits significantly reduce a probability of error at the second node due to metastability when the second control signal transitions from asserted to deasserted and the first clock signal is deselected. The second switching circuit provides electrical feedback from the second node to the first node.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: August 9, 2005
    Assignee: International Business Machines Corporation
    Inventors: David W. Boerstler, Eskinder Hailu
  • Patent number: 6925111
    Abstract: In data communication among a plurality of component units in an apparatus, transition state information corresponding to a state transition which has occurred in a sending side unit is sent to a receiving side unit in serial communication. In the receiving side unit, a state control signal is regenerated at the time when a given delay time has elapsed from the occurrence time of the state transition. Therefore, the state control signal can be sent in serial communication without any time skew. Also, in serial communication between the sending side unit and the receiving side unit, even if a control command signal is to be sent, in addition to the state control signal, a transition state information can be identified from the received signal, by means of adding identification information to the sending information.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: August 2, 2005
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Mikio Koga
  • Patent number: 6917659
    Abstract: A method of recovering data from a modulated data signal includes tracking a transmitted clock with a plurality of locally-generated clock phases, estimating an average phase of previously detected edges, registering a pulse edge in the received stream of data at a transition phase corresponding to one of the plurality of locally-generated clock phases, determining whether a first symbol was received multiple times consecutively prior to the registered pulse edge, and using the determination of whether the first symbol was received multiple times consecutively in a receiver decision process.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: July 12, 2005
    Assignee: Intel Corporation
    Inventors: David S. Dunning, Chamath Abhayagunawardhana, Kenneth Drottar, Richard S. Jensen
  • Patent number: 6914951
    Abstract: Logic apparatus filters noise signals on a signal line to a digital circuit. An edge detector determines one or more edges of the noise signals relative to a fast clock. Signals indicative of the edges asynchronously reset a timer; the timer clocks the latch of the signal line when the signal line is stable, and without noise signals detected by the edge detector, for a period defined by a slow clock. The slow clock is slower than the fast clock by several orders of magnitude. The edge detector may be constructed by one flip-flop and an XOR gate. A second flip flop couples to the signal line and the output of the timer to pass through the latched value of the signal line to the digital circuit when clocked by the timer.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: July 5, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael John Erickson, Bradley D. Winick, David R. Maciorowski
  • Patent number: 6907090
    Abstract: Methods and corresponding apparatus to recover data from a signal comprising groups of pulses generated in response to analog waveforms are described. Data recovery in accordance with the invention is based on parameters characterizing the groups of pulses. These parameters are the basis for mapping the groups of pulses to information symbols which collectively constitute the data to be recovered.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: June 14, 2005
    Assignee: The National University of Singapore
    Inventor: Guo Ping Zhang
  • Patent number: 6891898
    Abstract: The system for recovering symbol timing offset and carrier frequency error from an orthogonal frequency division multiplexed (OFDM) signal includes a receiver circuit for receiving an OFDM modulated signal representing a series of OFDM symbols, and providing a received signal to an output thereof. A peak development circuit is included for developing a signal having a plurality of signal peaks representing symbol boundary positions for each received OFDM symbol, where each of the signal peaks is developed responsive to an amplitude and phase correspondence produced between the leading and trailing portions of each of the received OFDM symbols. The system includes a circuit for enhancing the signal peak detectability, which includes a circuit for additively superimposing and then filtering the signal peaks, to produce an enhanced signal peak having an improved signal-to-noise ratio.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: May 10, 2005
    Assignee: iBiquity Digital Corporation
    Inventors: Paul James Peyla, Joseph Bertram Bronder
  • Patent number: 6891475
    Abstract: The invention concerns a radio-frequency transponder (12) for contact-free identification with a reader (10), comprising: an antenna (24), an analog circuit (25) including a capacitor (32) an AC-DC converter (34), a modulator (40) and a demodulator (38), a logic control circuit (26), a storage unit (27). Said transponder (12) is designed such that: the antenna (24) and the capacitor (32) form together a resonant circuit, the clock extractor (36) processes the first signal (Tx) to extract therefrom a clock signal addressed to said modulator (38) as long as the voltage of said signal (Tx) exceeds a first threshold value, the converter (34) transforms the first signal (Tx) into a rectified signal, to power the transponder (12). The performances of the transponder, and more particularly energy recuperation and data transmission rate, are improved by the fact that the analog circuit comprises two clock extractors, one of low level type (35), the other of the high level type (36).
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: May 10, 2005
    Assignee: MBBS Holding S.A.
    Inventors: Ngoc-Chau Bui, Christian Werner, Yves Gaudenzi, Martial Benoit, Vincent Cassi, Christian Mirus, Jean-Daniel Chatelain, Jacques Kowalczuk
  • Patent number: 6888905
    Abstract: A wireless receiver e.g., a Bluetooth-compatible receiver or a receive chain in a Bluetooth-compatible transceiver, includes a discriminator unit and a timing recovery unit. The output of the discriminator unit is provided as an input to the timing recovery unit, which timing recovery unit is configured to align a free-running clock of the receiver with a received signal to extract received data therefrom.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: May 3, 2005
    Assignee: Microtune (San Diego), Inc.
    Inventors: Jonathon Cheah, Jianping Pan, Le Luong
  • Patent number: 6850580
    Abstract: A bit synchronizing circuit used in a reception circuit for serial communication comprises a data sampling circuit for over-sampling inputted data, a change point detecting circuit for detecting a change point of the inputted data based on an output from the data sampling circuit, a change point holding circuit for changing a held value stepwise in the case where the output from the change point detecting circuit is different from the held data, a selected value setting circuit for determining which value of the data sampling circuit is to be selected based on the output of the change point holding circuit and a data selecting circuit for selecting the data from the data sampling circuit based on the output of the selected value setting circuit. It alternatively may comprise a data sampling circuit for over-sampling the bit data, a synchronizing circuit, a change point detecting circuit, and a data selecting circuit.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: February 1, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hitoshi Naoe
  • Patent number: 6847789
    Abstract: Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate, receiving the clock signal having a first clock frequency, alternating between a first level and a second level, wherein the first data rate is twice the first clock frequency. A first signal is generated by passing the data signal when the clock signal is at the first level, and storing the data signal when the clock signal is at the second level. A second signal is generated by passing the data signal when the clock signal is at the second level, and storing the data signal when the clock signal is at the first level. A third signal is generated by passing the first signal when the clock signal is at the second level, and storing the first signal when the clock signal is at the first level.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: January 25, 2005
    Assignee: Broadcom Corporation
    Inventor: Jafar Savoj
  • Patent number: 6839381
    Abstract: A method of channel estimation in a Code Division Multiple Access (CDMA) transmission system that incorporates Pilot Symbol Assisted Modulation (PSAM) using an iterative coherent detection method to estimate the phase and frequency of the received pilot symbols. Arctangent calculations are used to estimate phase and frequency. An iterative least squares linearization identifies and corrects values of the arctangent associated with an incorrect 2? alias, which arise due to the multiple-valued nature of the arctangent function. An alternative non-iterative least squares linearization also corrects the arctangent values, based on a calculation involving stored values of the pilot symbols.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: January 4, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chengke Sheng, Christopher P. Thron, T. Keith Blankenship
  • Publication number: 20040264614
    Abstract: A host interface includes transition detection circuitry, transition phase averaging circuitry, and bit stream sampling circuitry. The transition detection circuitry receives an incoming bit stream and a reference clock signal and detects transitions of the incoming bit stream with respect to the reference clock signal. The transition detection circuitry also determines relative phases of the transitions with respect to the reference clock signal. The transition phase averaging circuitry determines an average relative phase of the detected transitions with respect to the reference clock signal and also determines, based upon the average relative phase of the detected transitions with respect to the reference clock signal, a sampling phase with respect to the reference clock signal. The bit stream sampling circuitry samples the incoming bit stream at the sampling phase with respect to the reference clock signal to extract the bit values. The incoming bit stream may comply with the Universal Serial Bus 2.
    Type: Application
    Filed: June 27, 2003
    Publication date: December 30, 2004
    Inventor: Darrell E. Tinker
  • Patent number: 6836503
    Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: December 28, 2004
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Richard E. Warmke, David B. Roberts, Frank Lambrecht
  • Patent number: 6829309
    Abstract: The invention is related to analog to digital conversion of a multi-level analog signal at a very low sampling rate. The analog signal is sampled by a recovered clock to produce a succession of samples of the analog signal. The low sampling rate may be within an order of magnitude of the symbol rate of the analog signal. Each sample is converted to a digital word. A phase detector reference circuit determines from peak values of the analog signal at least two allowable levels of the analog signal including a reference-crossing level. The phase detector defines a zero band of amplitude ranges of the analog signal including the reference-crossing level. It further defines an error band of amplitude ranges of the analog signal extending from said zero band to a fraction of the amplitude of the next allowable level. The phase detector then infers either a positive or negative phase error for each pair of successive samples of the analog signal.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: December 7, 2004
    Assignee: 3Com Corporation
    Inventor: Anthony Eugene Zortea
  • Publication number: 20040202268
    Abstract: In a method for detecting a varying data rate in a data signal, with which data signal a bit is transmitted in the form of a signal edge generated at a particular nominal time, after triggering by an interrupt signal (IS) generated in an analog/digital converter (13), the times of occurrence (TA, TB, TC, TD) of the signal edges are detected and subsequently the edge intervals (T1, T2) determined from the times of occurrence (TA, TB, TC, TD) of the signal edges and subsequently the mean edge interval (Tm) determined from the determined edge intervals (T1, T2). From the mean edge interval (Tm) and a tolerance range of the mean edge interval (Tm) are determined an upper time of occurrence limit (OAZ) and a lower time of occurrence limit (UAZ), within which upper and lower time of occurrence limit a subsequent signal edge must occur in order to be valid for the detection of a current data rate from the mean edge interval (Tm).
    Type: Application
    Filed: January 20, 2004
    Publication date: October 14, 2004
    Inventors: Michael Angelo Rauber, Werner Mair, Heinz Lanzenberger
  • Publication number: 20040190667
    Abstract: In a clock extracting circuit according to the present invention, after serial data is subjected to oversampling using a reference clock of 2N times a frequency of the serial data, clock timing in a period of time in which signal level remains unchanged for a long duration is extracted by first timing detecting means. Clock timing based on a point of change in the signal level is extracted by second timing detecting means, and a final clock timing signal is outputted according to these timings detected. Thus, clock timing can be extracted accurately without omission even when the input signal includes jitter. Further, the clock extraction is performed without converting the input signal into parallel data and by simple processing. A clock extracting circuit for extracting a clock signal from the received serial data with high accuracy is thus realized without increasing the circuit scale.
    Type: Application
    Filed: February 24, 2004
    Publication date: September 30, 2004
    Inventor: Kouji Matsuura
  • Patent number: 6798857
    Abstract: A clock recovery circuit which has a transition detector connected to the incoming data stream. An output of the transition detector is connected to a gate, such as a D flip-flop, which has an input receiving the recovered clock. A zero or one output will be generated depending upon whether the transition is before or after the rising edge of the recovered clock. An accumulator circuit accumulates a count for each transition, providing the results to a comparison circuit. The comparison circuit compares the accumulated count to maximum and minimum thresholds, and provides advance or retard outputs when those thresholds are exceeded. A phase circuit adjusts the phase of the recovered clock by advancing or retarding it after a sufficient number of transitions have been detected either in advance or behind the recovered clock to justify such an adjustment.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: September 28, 2004
    Assignee: Exar Corporation
    Inventors: Roubik Gregorian, Shih-Chung Fan