Abstract: System and method for data transfer with buffer control. According to an embodiment, the present invention provides a system for synchronized data communication. The system includes a first communication interface for receiving data and a first clock signal. For example, the first clock signal is associated with a transmitting source. The system also includes a second communication interface for transmitting data. The system further includes a processing component for separating a single data stream into multiple data streams. The system additionally includes a clock that is configured to provide a second clock signal. Also, the system includes a plurality of buffer components for providing temporary storage for data streams. For example, each of the buffer components can be characterized by a predetermined buffer size. The plurality of buffering component includes a first buffer component and a second buffer component.

Abstract: A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.

Abstract: A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.

Abstract: In some embodiments an apparatus includes a higher order statistical signal processor to process a jittered digital signal, a diagonal line average unit to identify a distinct line in a signal output from the higher order statistical signal processor, and a peak detection unit to determine a peak value in response to an output of the diagonal line average unit and to provide a data rate signal as an output. Other embodiments are described and claimed.

Abstract: A NICAM system includes a NICAM deframer, a FIFO buffer and a symbol rate conversion (SRC) unit. The NICAM deframer obtains multiple deinterleaved symbols according to a strobe signal and a data signal in each timing and expands the deinterleaved symbols to corresponding multiple pulse code modulation (PCM) symbols. The FIFO buffer temporarily stores the symbols and outputs the PCM symbols at a local timing, rate. The SRC unit determines whether a SRC function is enabled according to the statuses of the symbols in the FIFO buffer every a constant time interval. When the SRC function is enabled, the SRC unit interpolates the PCM symbols to obtain multiple new PCM symbols and outputs the new PCM symbols at the local timing rate.

Abstract: The present invention discloses a de-jittering method for a clock signal, which is implemented by adopting a controllable frequency divider and includes: taking the clock signal to be de-jittered as a reference signal, and comparing a feedback clock signal outputted by the controllable frequency divider with the reference signal; generating the control signal that is then transmitted to the controllable frequency divider; the controllable frequency divider performs frequency division upon the input high-frequency signal to generate a stable clock, and the stable clock is outputted as the feedback clock signal which has been de-jittered. The present invention also discloses a de-jittering apparatus for implementing the above-mentioned method, which includes: a circuit for generating a control signal and a controllable frequency divider. By applying the present invention, the de-jittering circuit for clock signal can be simple.

Abstract: In one embodiment, the present invention includes a method for maintaining a vocoder and channel codec in substantial synchronization. The method may include receiving a configuration message that includes rate information and an effective radio block identifier at a mobile station, coding a current radio block via a vocoder and channel codec, configuring an encoding portion of the vocoder and channel codec with the rate information after performing the coding, and then coding the effective radio block using the rate information. Other embodiments are described and claimed.

Abstract: The techniques described herein allow a more efficient transmuxing operation for transferring data from a synchronous domain (e.g., SONET) to a plesiochronous (e.g., PDH) domain as compared to the prior art, in which extraction of data streams, jitter filtering and stuff bit generation are processed separately. The techniques described herein include extraction of data from the plesiochronous data stream without complete extraction of the underlying native data stream. Filtering is performed based on synchronous timing, which results in a simpler filter design.

Abstract: A data synchronization apparatus is provided. The data synchronization apparatus comprises a first-in first-out buffer (FIFO buffer), a control circuit and a phase-locked loop (PLL). The FIFO buffer receives and stores a plurality of data and provides a FIFO adjustment signal according to the number of the data stored in the FIFO buffer. The data stored in the FIFO buffer are sent out to an external device at a clock rate derived from a master clock signal. The control circuit provides a PLL adjustment signal according to the FIFO adjustment signal. The PLL provides the master clock signal and adjusts the frequency of the master clock signal in response to the PLL adjustment signal.

Abstract: A receiver for a digital communication signal has a first decision gate (DGa), which has a first decision threshold (xd) for outputting a first decision signal, a second decision gate (DGb), which has a second decision threshold (xm) for outputting a second decision signal, a counter (CNT) for counting events where the first and second decision signals of the first and second decision gates (DGa, DGb) differ from each other, and a controller (PROC) capable of controlling the decision thresholds of said first and second decision gates in accordance with count values delivered by said counter. The controller (PROC) determines an initial decision threshold value by performing a statistical analysis of the received signal and setting the decision threshold such that the distribution of logical ‘0’ and logical ‘1’ in the decided signal corresponds to the expected distribution, which is in typically 50%/50%.

Abstract: Apparatus, methods and techniques for adjusting the phase offset used in sampling rate conversion uses a Farrow structure or the like to compensate for clock problems such as “clock jitter” and/or “clock drift” effects, which typically arise where one clock is truly independent of the other. A phase offset adjustment value ?? based on the measured data flow between clock domains across a transition interface and/or through a buffer is calculated. Where an output FIFO buffer is used, the measured data flow value represents the number of data words written to and read from the FIFO buffer, such as the current number of data words stored in the FIFO buffer or a counter value representing the net number of data words written to the FIFO buffer. The measured data flow value is compared to a target data flow value, which may be a range of values. The phase offset adjustment value may be updated and/or recalculated continuously and/or periodically and is added to or subtracted from the phase offset ? as necessary.

Abstract: A phase measurement circuit is described that receives a signal with irregularly spaced edges and assigns a numerical value to the phase of each edge. An interpolator provides linear interpolation between successive values to provide continuous phase values at smaller, regular intervals. The interpolated values are resampled at a lower, regular rate to simplify subsequent processing by filters or other data-reduction means. The interpolation is performed without dividers or two-variable multipliers.

Abstract: Circuit and method for an adaptive elastic buffer for receiving data including timing signals. Received data is recovered and stored in the adaptive elastic buffer, and a recovery clock pointer is increased to identify the next buffer location for stuffing received data, responsive to a controller. When a data fetch enable condition occurs, the controller causes a receiver circuit to fetch the data stored at a location identified by a system clock pointer. Underflow and overflow conditions are detected and the controller adapts the effective elastic buffer depth to compensate for these conditions. A buffer of M/2 physical locations is adaptively operated to provide a data buffer of M virtual locations. A method of buffering received data with a buffer having M/2 physical locations so as to provide the benefit of a buffer with M virtual locations is disclosed.

Abstract: A phase locked loop (PLL) architecture provides voltage controlled oscillator (VCO) gain compensation across process and temperature. A simulator may be used to calculate the control voltages for the maximum and minimum output frequency of the VCO for each combination of the process and temperature corners. The maximum and minimum values of control voltage are then selected from these control voltages. Using a counter, the number of cycles of VCO in some cycles of the PLL input clock are counted in binary form and stored in latches for the extreme control voltages. The difference between them and the corresponding difference for typical process and temperature corner is used to modify the charge pump to change the current delivered to the loop filter. After the charge pump bits have been decided, the input control voltage of the VCO connects to the charge pump output to start the normal operation of the PLL.

Abstract: A phase rotator generates an output signal having plurality of possible output phases with reduced phase jitter. The low jitter phase rotator includes a plurality of differential amplifiers configured to receive a plurality of input differential signals having different phases, and configured to generate a plurality of weighted signals responsive to the plurality of input differential signals. A plurality of digital-to-analog converters (DAC) are arranged into a plurality of groups, each group of DACs configured to provide current for one of the corresponding differential amplifiers. The number of active DACs in each group of DACs determines a relative weighting of the weighted signals, where relative weighting determining an output phase of an output signal of the phase rotator. The DACs are configured to adjust the output phase of the phase rotator. At a kth phase, N/4 adjacent DACs are activated that are indexed as m0, m1, . . . m((N/4)?1), wherein N is the number of said plurality of DACs.

Abstract: A clock synchroniser, for generating a local clock signal synchronised to a received clock signal, is described and claimed, along with a corresponding clock synchronisation method. The clock synchroniser incorporates a reference oscillator providing a reference signal, and a synthesiser circuit arranged to synthesise a local clock signal from the reference signal. The synthesiser circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchroniser also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and remote clock signals. A control link is arranged to link the clock comparison circuit to the divider.

Abstract: A method for automatically calibrating intra-cycle timing relationships between command signals, data signals, and sampling signals for an integrated circuit device. The method includes generating command signals for accessing an integrated circuit component, accessing data signals for conveying data for the integrated circuit component, and accessing sampling signals for controlling the sampling of the data signals. A phase relationship between the command signals, the data signals, and the sampling signals is automatically adjusted to calibrate operation of the integrated circuit device.

Abstract: Techniques are provided for calculating a clock rate for a serial clock of a transmitter where information sent by the transmitter is sent in packets from the transmitter over an asynchronous network. The techniques involve minimizing the number of adjustments to the clock rate that are needed to fine tune the clock rate to match the serial clock of the transmitter.

Abstract: In the operation of a mobile device (such as a cellular telephone or a PDA, i.e. Personal Digital Assistant), which mobile device includes a mobile terminal and a memory module, certain operational signals of the mobile device are multiplexed and demultiplexed, resulting in efficient device bus utilization and reduced device pin count.

Abstract: A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal.

Abstract: The invention includes a method and apparatus for generating virtual clock signals for differing hierarchies in a communication system conveying data frames of differing hierarchies. Specifically, a method according to one embodiment of the invention includes receiving data frames of a first hierarchy, receiving at least one input clock signal, and generating a virtual clock signal using the at least one input clock signal and a clock enable signal. The clock enable signal is generated using at least one of a data rate ratio and a clock rate ratio. The virtual clock signal is adapted for converting at least a portion of the data frames of the first hierarchy to data frames of a second hierarchy. The frequency of the virtual clock signal is determined by applying the clock enable signal to a common clock signal.

Abstract: A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (<m) bits within a transfer period and a serial clock synchronized therewith, and to shift and hold the serial data by one bit based on the serial clock; an input mode identifying unit to identify whether the input bit number is m or n bits, based on a count value obtained by counting the number of generation of the serial clock during the transfer period; and a parallel data generating unit to output the held m-bit data as first parallel data when the input bit number is identified as m bits, and to output m-bit data obtained by adding predetermined (m?n)-bit data to the held n-bit data as second parallel data when the input bit number is identified as n bits.

Abstract: A data reception apparatus adjusts a first clock signal and fetches the data signal in a data buffer, using a data signal in accordance with the adjustment clock signal in such a way that a set-up time and a hold time of the data signal are secured for each bit or for each group of parallel data. Then, this apparatus selects the data of a plurality of bits in the data buffer in chronological order and reads out the selected data as parallel data, in accordance with a second clock signal.

Abstract: A clock rate used in rendering broadcast streaming audio/video data is adjusted to converge on a clock rate associated with broadcasting the streaming data. The clock rate is adjusted by monitoring the buffer depth associated with a receive buffer that stores the incoming streaming data. The buffer depth provides an estimate of clock drift between the two clock rates. From the estimate of clock drift, the clock rate used in rendering broadcast streaming data is adjusted to avoid the clock drift causing skips or pauses in the rendered audio/video data.

Abstract: A method for digital clock smoothing comprising: (A) inputting an asynchronous data stream having an asynchronous symbol rate into a two-port memory block; (B) accumulating a plurality of symbols of the asynchronous data stream in the two-port memory block for a predetermined time period; (C) computing an average symbol rate for the input asynchronous data stream; (D) generating a clock error signal equal to the difference between the average symbol rate of the input asynchronous data stream and a nominal output synchronous clock; (E) obtaining a smoothed symbol rate clock by using the error clock signal; and (F) generating an output smoothed data stream having the smoothed symbol rate clock.

Abstract: A sampling apparatus for converting first data, sampled at a first sampling rate, into second data, sampled at a second sampling rate. A FIFO storing the first data based on a write control signal and outputs the second data read out based on a read control signal indicating whether the second data is to be read out during the next time interval. The apparatus further includes a frequency detection unit for measuring the first clock signal during the current time interval to generate the value of the first current clock frequency, generating the value of a current predicted clock frequency from the value of the first current clock frequency and the value of the directly previously predicted clock frequency and for using the value of the current predicted clock frequency as the directly previously predicted clock frequency during the next time interval.

Abstract: A receiving apparatus receives data sequences, each of which includes plural data blocks, from plural transmission lines, respectively. The apparatus includes plural elastic buffers and a deskew circuit. The corresponding data sequence is written into each elastic buffer. A predetermined number of consecutive timing control symbols are inserted into the data sequences as markers for data blocks to be read from the data sequences at the same cycle. The elastic buffers adjust numbers of the timing control symbols included in the written data sequences, respectively. The data sequences, in each of which the number of the timing control symbols has been adjusted, are read from the elastic buffers in synchronization with a reading clock. The data sequences are written into the deskew circuit. The deskew circuit adjusts the number of the timing control symbols included in each data sequence so as to be equal to the predetermined number.

Abstract: Methods and apparatus are provided for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications. An interface is provided for use between a parallel bus and a serial bus. The interface includes a plurality of serializer/deserializer circuits that generate a clock signal, wherein one of the serializer/deserializer circuits is a master circuit generating a master clock signal and the remaining of the serializer/deserializer circuits are slave circuits generating slave clock signals. The master clock signal is substantially phase-aligned to a reference clock and is distributed to the slave circuits. The interface also includes a clock divider associated with the master circuit for selectively generating a master clock signal having one or more lower data rates than the reference clock; and a frequency detector associated with each of the slave circuits for automatically detecting a rate of the master clock signal.

Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.

Abstract: A signal processing device includes a phase shifting unit for supplying a second clock signal having a predetermined phase difference relative to a first clock signal, a head recognition bit adding unit for adding a head recognition bit to a predetermined position of data constituting a packet, an inputting unit for reading out a data signal from the memory in synchronization with the second clock signal, a clock replacing unit for inputting the data signal on the basis of the second clock signal and outputting the data signal on the basis of first clock signal, a data shifting unit for shifting the data signal by an amount corresponding to a predetermined number of clock cycles, and an enable signal generating unit for generating an enable signal for recognizing an available length of the packet after an appearance of the head recognition bit in the output signal.

Abstract: A system for monitoring EF-on-EF jitter in a network node having an EP output queue into which EF packets are entered comprises a first counter that counts the packets entering the queue and also a second counter that counts the packets entering the queue when the queue depth is greater than an operator-determined maximum depth, whereby the operator can compare the two counts to determine the proportion of packets that might be subject to jitter corresponding to the maximum depth. Preferably, the system also includes a third counter that counts the number of packets entering the queue when the queue depth exceeds an alarm depth greater than the maximum depth.

Abstract: A clock synchronizer, for generating a local clock signal synchronized to a received clock signal, is described and claimed, along with a corresponding clock synchronization method. The clock synchronizer incorporates a reference oscillator providing a reference signal, and a synthesizer circuit arranged to synthesize a local clock signal from the reference signal. The synthesizer circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchronizer also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and remote clock signals. A control link is arranged to link the clock comparison circuit to the divider.

Abstract: A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal.

Abstract: In a data transmission controller apparatus, a first-in first-out storage stores newly inputted data in response to a write request signal, and reads and outputs the stored data which has been stored earliest in response to a read request signal. A remaining data amount detection portion detects a remaining data amount of the stored data which remain in the first-in first-out storage. A variable frequency oscillating portion generates an enable signal at a time rate according to frequency control information so as to enable generation of the write request signal or read request signal. A frequency control portion corrects the frequency control information so as to return the remaining data amount to an appropriate value when the remaining data amount detected by the remaining data amount detection portion varies away from the appropriate value toward an upper limit value or varies away from the appropriate value toward a lower limit value.

Abstract: Buffer circuitry receives data to be processed by electronic circuitry using a first clock signal associated with a first clock domain. The buffered data is output using a second clock signal associated with a second clock domain. The buffering of the data is associated with a buffering delay. Counting circuitry receives at a start count input a write timing signal associated with the first clock domain and with writing data to the buffer circuitry. The counting circuitry receives at a stop count input a read timing signal associated with the second clock domain and with reading data from the buffer circuitry. A count value accumulated between receiving the write timing signal and the read timing signal corresponds to the buffering delay. Control circuitry performs a control operation based on the count value.

Abstract: A phase lock loop device further includes a probability shaping device provided between a phase detection device and charge pump and loop filter (CPLF) device. The probability shaping device operates to reduce the frequency of outputting up-index or down-index; thereby shaping probability distribution to reduce degradation due to mismatching of the CPLF device.

Abstract: A circuit for data stream buffer management, lane alignment, and clock compensation of data transfers across a clock boundary using a single first in first out (FIFO) buffer in each serial channel is described. The RapidIO® data channel, for example, operates using a clock recovered from the data stream. The RapidIO® data stream has embedded special characters, where a select sequence of embedded characters is a clock compensation pattern. A look ahead circuit is used to detect the clock compensation pattern early and generate a clock compensation indicator signal. The FIFO writes data and the associated clock compensation indicator signal in a clock compensation indicator bit in synchronism with the recovered clock. A read circuit using a second clock of a different frequency than the first clock reads data and clock compensation bits from the FIFO and generates an almost empty signal when appropriate. A multiplexer is used at the FIFO output to pad data to the system interface.

Abstract: The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals.

Abstract: A transmitter LSI 1 transmits a source clock, transmission data, and a transmission sync signal indicating the timing of the transmission data to a receiver LSI for establishing transmission synchronization between LSIs. The transmitter LSI 1 includes: a data transmission section that transmits, as the source clock, a transmitter LSI system clock input from outside to the receiver LSI and, at the same time, transmits the transmission data according to the transmitter LSI system clock to the receiver LSI; and one or more transmission sync signal generation sections 11 that generate the transmission sync signal based on the timing of the transmitter LSI system clock and an inter-LSI sync signal input from outside.

Abstract: Embodiments of the present invention include a frequency synthesizer comprising a first plurality of dividers receiving a first signal having a first frequency and generating a first plurality of divided signals and a frequency combination network including a plurality of mixers, the frequency combination network receiving one or more of the first plurality of divided signals and generating a plurality of synthesized signals having different frequencies. The frequency combination network may further include additional dividers and multiplexers for more flexibility in synthesizing different frequencies. In one embodiment, the frequency combination network is coupled to dividers in the feedback path of a phase locked loop. The present invention is particularly advantageous for synthesizing frequencies above one (1) gigahertz.

Abstract: Data is transferred from a transmitter to a data buffer of a receiver according to the clock of the transmitter. When the amount of data in the data buffer exceeds an upper limit, the frequency of the reference clock of the receiver is increased to read the data faster, which is transferred to a digital-to-analog converting and audio amplifying section. When the amount of data falls below the upper limit, data is read at the original frequency of the reference clock of the receiver. When the amount of data falls below a lower limit, the frequency of the reference clock of the receiver is decreased.

Abstract: A digital modulator in a radio transmitter includes circuitry for switching between Gaussian Minimum Shift Keying (GMSK) and Phase-Shift Keying (PSK) while maintaining spectral mask requirements. The digital modulator of the present invention includes both GMSK and PSK symbol mappers that produce PSK in-phase and quadrature symbols and GMSK symbols, respectively, to a pulse shaping block. Based on opposite phases of a modulation control signal, the symbol mappers produce either modulated data or a steam of logic zeros to the pulse shaping block. The pulse shaping block filters the received data and multiplexes the data so that each modulated data stream receives non-zero data during a guard time to avoid abrupt changes in the modulated signal that would violate the spectral mask requirements.

Abstract: A method, system, and apparatus for synchronizing an asynchronous data transmission between a transmitter and a receiver are presented. For example, an elastic buffer can include a symbol storage coupled to receive transition data from a transmitter and to store the transition data in a plurality of addressable symbol storage elements; a write clock domain, which operates at a recovery clock, for selecting a symbol storage element of symbol storage to store the transition data, determining whether a SKIP ordered set has occurred, and deleting a SKIP symbol of the SKIP ordered set based on the determination to prevent the deleted SKIP symbol from being stored in symbol storage; and a read clock domain, which operates at a local clock, for selecting a symbol storage element of the symbol storage to retrieve the transition data as receiver data, determining whether a SKIP ordered set is occurring, adding a SKIP symbol to the receiver data based on the determination; and providing the receiver data to a receiver.

Abstract: Embodiments of the present invention may provide for independent setting of jitter tolerance and jitter transfer levels, and reduced jitter generation of a data transmission device, such as a clock and data recovery (CDR) circuit or the like. An architecture may provide for reconfigurability of a circuit for use in various applications. The architecture may include a multi-loop structure, such as a tri-loop structure.

Abstract: An oversampling system (oversampling apparatus), a decoding LSI chip, and an oversampling method capable of decreasing the memory capacity of an output buffer used to oversample and output decoded data for digital audio.

Abstract: In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.

Abstract: A circuit for data stream buffer management, lane alignment, and clock compensation of data transfers across a clock boundary using a first in first out (FIFO) buffer in each serial channel is described. A look ahead circuit is used to detect a clock compensation pattern early and generate a clock compensation indicator signal. Data and the clock compensation indicator signal are written in the FIFO in synchronism with the recovered clock. A read circuit using a second clock of a different frequency than the recovered clock reads data and clock compensation bits from the FIFO and generates an almost empty signal when appropriate. A multiplexer is used at the FIFO output to pad data to the system interface. A clock compensation control circuit generates a selection signal based on the almost empty signal and the clock compensation indicator bit read out of the FIFO to control the multiplexer selection signal.

Abstract: A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. The decoder buffer level limits are specified in terms of a maximum number of encoded frames (or duration). The transmitter can predict the number of encoded frames, Fpred, in the decoder buffer and transmit the value, Fpred, to the receiver with the audio data. If the transmitter determines that the decoder buffer level is becoming too high, the frames being generated by the encoder are too small and additional bits are allocated to each frame for each of the N programs. Likewise, if the transmitter determines that the decoder buffer level is becoming too low, the frames being generated by the encoder are too big and fewer bits are allocated to each frame for each of the N programs. The transmitted predicted buffer level, Fpred, can also be employed to (i) determine when the decoder should commence decoding frames; and (ii) synchronize the transmitter and the receiver.

Abstract: A delay buffer includes a first shift register receiving input data and having a shift signal input port. The first shift register right shifts the input data responsive to a shift signal on the shift signal input port. The shift signal is determined based on an effective bit width of the input data. A first delay line receives the shifted data from the first shift register while a second delay line of equal length to the first delay line receives the shift signal. A second shift register receives the output from the first delay line and receives the output of the second delay line on a shift signal input port. The second shift register then left shifts the data contained therein according to the shift signal.

Abstract: A technique includes in response to a training mode, communicating between a device and a processor of a computer system over a data bit line of a bus. The technique includes based on the communication, regulating a timing between a strobe signal and a signal that propagates over the data bit line.