Abstract: The present invention relates to a system and method for generating a first clock frequency for a plurality of digital data bursts compressed in time, where each of the plurality of digital data bursts has been multiplexed into one of a plurality of data blocks of higher speed digital data. The system and method includes acquiring the width in data elements of a digital data burst and the width in data elements of a data block of higher speed digital data. The width of one period of a clock pulse is computed at the first clock frequency. A clock pulse is generated at the first clock frequency.

Abstract: A digital signal offset adjusting apparatus has a capacitor causing an output terminal to pass a high frequency band of an input digital signal. A first coil has one end connected to an input terminal and a second coil has one end connected to an output. An operational amplifier has an input connected to another end of the first coil, a second input connected to a direct current voltage generator and an output connected to another end of the second coil. The operational amplifier outputs a signal obtained by subtracting and combining the low frequency band, the direct current component and a direct current bias voltage. A frequency characteristic compensating circuit is connected between a reference point and the second input of the operational amplifier. The gain of the operational amplifier increases with a component having a higher frequency from among low frequency bands of the input digital signal.

Abstract: The present invention includes a time-division-multiple-access (TDMA) communication system having a base station and at least one mobile station, each transmitting and receiving an analog radio-frequency signal carrying digitally coded speech. The speech is encoded using a vocoder which samples a voice signal at variable encoding rates. During periods when the radio-frequency channel is experiencing high levels of channel interference, the encoded voice channel having a lower encoding rate is chosen. This low-rate encoded voice is combined with the high degree of channel coding necessary to ensure reliable transmission. When the radio-frequency channel is experiencing low levels of channel interference, less channel coding is necessary and the vocoder having a higher encoding rate is used. The high-rate encoded voice is combined with the lower degree of channel coding necessary to ensure reliable transmission.

Abstract: A method for calculating equal error protection (EEP) profiles is disclosed. The method uses a profile function related to a sub-channel size to calculate EEP profiles and then uses the EEP profiles to decode data. When a receiver receives a protection level and a size value of the sub-channel size, a corresponding sub-channel size can be rapidly obtained through a reference table of the protection level and the sub-channel size so as to calculate the required EEP profiles. The method in the present invention requires only a few adders/subtractors and shifters or an easily realizable multiplier to calculate the profiles so that the objective of effectively saving cost and rapidly obtaining the profiles is achieved.

Abstract: A sampling apparatus for converting first data, sampled at a first sampling rate, into second data, sampled at a second sampling rate. A FIFO storing the first data based on a write control signal and outputs the second data read out based on a read control signal indicating whether the second data is to be read out during the next time interval. The apparatus further includes a frequency detection unit for measuring the first clock signal during the current time interval to generate the value of the first current clock frequency, generating the value of a current predicted clock frequency from the value of the first current clock frequency and the value of the directly previously predicted clock frequency and for using the value of the current predicted clock frequency as the directly previously predicted clock frequency during the next time interval.

Abstract: A modulation device comprises a modulation unit (2) that modulates data in a hierarchical manner using multiple types of modulation techniques, and a transmission unit (3) that transmits the hierarchically modulated data. A demodulation device comprises a receiving unit (4) that receives the hierarchical modulation data having been subjected to hierarchical modulation using multiple types of modulation techniques, and a demodulation unit (6) that demodulates the hierarchical modulation data using a demodulation technique corresponding to a specific hierarchy of the hierarchical modulation data.

Abstract: An integrated circuit device is provided including a plurality of circuit blocks which operate based on a clock signal. The quartz oscillation circuit outputs a first clock signal. A spectrum spread clock generator outputs a second clock signal having a spread frequency. A clock signal is output to the plurality of circuit blocks and, based on an instruction to output the clock signal from a CPU, a clock signal output to the plurality of circuit blocks is switched from the second clock signal to the first clock signal.

Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.

Abstract: When a controller transmits a clock pulse of a positive phase as a first transmit signal (a) and a clock pulse of an opposite phase as a second transmit signal (b), the controller modulates the “H” pulse of the second transmit signal to a signal advanced by time of td1 relative to the “L” pulse of the first transmit signal when the logic of transmit data is “1”, and to a signal advanced by time of td2 relative thereto when the logic of transit data is “0” and transmits the modulated signal. A data carrier device detects the change of the delay time of the second transmit signal by using a clock extracted from the first transmit signal to demodulate data (e).

Abstract: A clock synchronizer, for generating a local clock signal synchronized to a received clock signal, is described and claimed, along with a corresponding clock synchronization method. The clock synchronizer incorporates a reference oscillator providing a reference signal, and a synthesizer circuit arranged to synthesize a local clock signal from the reference signal. The synthesizer circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchronizer also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and remote clock signals. A control link is arranged to link the clock comparison circuit to the divider.

Abstract: Techniques to filter pilot symbols for a pilot in an “adaptive” manner to provide an improved estimate of the response of a communication channel. A received signal may experience different channel conditions at different times, and different multipaths may also experience different channel conditions even when received close in time. A pilot filter with an adaptive response is used to provide an improved estimate of the channel response. Various adaptive pilot filtering schemes may be used. In a first scheme, the channel conditions are estimated based on the quality of the received pilot. In a second scheme, the channel conditions are estimated based on the quality of the pilot estimates (i.e., the filtered pilot symbols). For each scheme, a particular filter response is selected based on the estimated quality of either the received pilot or the pilot estimates.

Abstract: An apparatus and a method for estimating a carrier to interference and noise ratio (CINR) in a communication system. The CINR value is precisely estimated by removing the error floor value, which is caused by the inaccurate sliding average window SAW channel estimation value, from the CINR estimation value. Since the CINR value is precisely estimated, performance of the adaptive power control or the adaptive modulation and coding device is improved.

Abstract: A multi-input multi-frequency synthesizing apparatus and method for a multi-band radio frequency (RF) receiver. The frequency synthesizing apparatus may generate an output from a greater number of high frequency signals by using one multi-input single side band (SSB) mixer. The multi-input SSB mixer may generate a signal whose frequency is an addition of frequencies of two signals selected from a signal selection control unit, or a difference of frequencies therebetween. According to a circuit configuration of the multi-input SSB mixer, the signal selection control unit may select more than two signals.

Abstract: In one embodiment of the method of adaptively selecting an airlink coding scheme in a telecommunications network, a coding scheme operating region is determined based on a currently used coding scheme and measurements representative of a block error rate. A block error coding scheme is determined based on the determined coding scheme operating region. In another embodiment of the method of adaptively selecting an airlink coding scheme in a telecommunications network, a first coding scheme is determined based on measurements representative of one or more conditional channel quality metrics, and a second coding scheme is determined based on measurements representative of a block error rate. One of the first and second coding schemes is selected as the coding scheme.

Abstract: A method is provided that includes selectively engaging impedance circuits one at a time from a plurality of selectable impedance circuits in-line with a communication channel. Each of the plurality of selectable impedance circuits includes a hybrid circuit responsive to a modem and to the communication channel. The method further includes determining a performance characteristic for each of the impedance circuits and selecting one of the plurality of selectable impedance circuits for transmission based on the respective performance characteristic.

Abstract: A radio frequency (RF) transmitter includes a digital radio processor and a baseband processor. A complex analog-to-digital converter (ADC) within the radio processor provides an analog interface to the baseband processor to receive an analog complex modulated baseband signal and convert the analog complex modulated baseband signal to a digital complex modulated baseband signal. A demodulator within the radio processor demodulates the digital complex modulated baseband signal to recreate the original transmit digital data as a demodulated digital signal. The demodulated digital signal is processed by a digital processor in the radio processor to mitigate the effects of various imperfections in the radio processor circuitry.

Abstract: A method of controlling a communication device that is operable to transmit digital data over a plurality of frequency channels. The method includes selecting an initial transmission power and a corresponding data rate for each channel. The method also includes identifying in a first channel a first ratio of a first decrement in transmission power to a first data rate decrement that is greater than a second ratio of a second decrement in transmission power to a second data rate decrement. Then, the initial transmission power allocation of the first channel is reduced by the first decrement. The method also includes reallocating the decremented initial transmission power of the first channel to one or more other channels.

Abstract: A data transfer apparatus is composed of a transmitter and a receiver. The transmitter includes an output buffer developing a differential signal in response to a data signal, and an amplitude controller. The receiver includes an input buffer converting the differential signal into a single-end signal, and an amplitude detector developing a feedback signal in response to the single-end signal. The amplitude controller controls an amplitude of the differential signal in response to the feedback signal.

Abstract: Methods, systems, and computer program products adaptively apply a target noise margin to a DSL loop to establish a DSL data rate on the DSL loop. A method involves receiving performance data associated with a quantity of errors detected over a period of time on the DSL loop and adjusting the target noise margin for the DSL loop based on the performance data. The target noise margin is inversely associated with the DSL data rate that can be established and is adjusted in order to maximize the DSL data rate while minimizing the quantity of errors detected over the period of time. Thus, embodiments of the present invention allow a maximum data rate that can be sustained on a DSL loop without an excessive quantity of errors.

Abstract: A transceiver comprises a communication line interface, memory, and logic. The memory stores predefined noise spectra, and the logic is configured to analyze an initialization signal received from the communication line coupled to the communication line interface during an initialization phase that precedes a data phase. The logic is configured to automatically select one of the predefined noise spectra based on the initialization signal and to combine the selected noise spectrum with the initialization signal to calculate a value. The logic is configured to perform a comparison between the value and a threshold and to make a determination, based on the comparison, whether a data signal to be communicated in the data phase will be spectrally compatible, if the data signal is transmitted at a data rate of the initialization signal. The logic is further configured to select a data rate for the data signal based on the determination thereby ensuring that the data signal is spectrally compatible.

Abstract: A transceiver that includes a receiver configured to receive a data signal, a controller, a first memory that includes a first table associated with a first set of gain values and a second table associated with a second set of gain values, and a second memory accessible by an external host is provided. The controller is configured to access a first value associated with a strength of the data signal from the receiver, access a second value associated with the first value from the first table, generate a third value using the second value, and store the third value in the second memory.

Abstract: The present invention includes a time-division-multiple-access (TDMA) communication system having a base station and at least one mobile station, each transmitting and receiving an analog radio-frequency signal carrying digitally coded speech. The speech is encoded using a vocoder which samples a voice signal at variable encoding rates. During periods when the radio-frequency channel is experiencing high levels of channel interference, the encoded voice channel having a lower encoding rate is chosen. This low-rate encoded voice is combined with the high degree of channel coding necessary to ensure reliable transmission. When the radio-frequency channel is experiencing low levels of channel interference, less channel coding is necessary and the vocoder having a higher encoding rate is used. The high-rate encoded voice is combined with the lower degree of channel coding necessary to ensure reliable transmission.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: An information apparatus switches a display at a predetermined area which includes at least a part of a portion where an electromagnetic-wave emitting unit used for data communications with a data storage device is disposed, according to data communication processing with the data storage device, and emits sound generated according to the processing at corresponding timing.

Abstract: Waveforms for controlled source electromagnetic surveying. The waveforms have frequency spectra that include three or more frequencies spaced at substantially equal intervals on a logarithmic frequency scale and spanning a bandwidth of about one decade or more, at least three of which frequencies have approximately equal corresponding amplitudes.

Abstract: A novel apparatus and method for a hybrid Cartesian/polar digital QAM modulator. The hybrid technique of the present invention utilizes a combination of an all digital phase locked loop (ADPLL) that features a wideband frequency modulation capability and a digitally controlled power amplifier (DPA) that features interpolation between 90 degree spaced quadrature phases. This structure is capable of performing either a polar operation or a Cartesian operation and can dynamically switch between them depending on the instantaneous value of a metric measured by a thresholder/router. In this manner, the disadvantages of each modulation technique are avoided while the benefits of each are exploited.

Abstract: An analog to digital converter device that includes a sample rate reduction system configured to sample a radio frequency (RF) signal. The RF signal has a bandwidth centered at a first frequency. The sample rate reduction system is configured to directly sample the RF signal at a sampling rate that is an integer multiple of the first frequency. The sample rate reduction system also is configured to provide M-sample outputs, each of the M-sample outputs being sampled at a reduced sampling rate equal to the sampling rate divided by M. M is an integer sample rate reduction value. An Nth order complex bandpass filter is coupled to the sample rate reduction system. The complex bandpass filter is configured to filter each of the M-sample outputs to obtain a plurality of complex baseband signals.

Abstract: A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.

Abstract: A method for converting a real signal into a complex signal in quadrature, whose particularity consists of the fact that it comprises the step that consists in adding to a real signal meant to be converted into a complex signal a signal whose frequency is four times the band-center frequency of the signal to be converted, in order to obtain a quadrature. The method further comprises the steps of: after the adding step from which a sum signal is obtained, selecting, from the sum signal, a first component and a second component which are in phase and in quadrature; removing components below a given level from the first and second components in phrase and in quadrature, in order to obtain a first and a second signal component at DC zero level.

Abstract: In a configuration testing integrated circuits, the system clock signals are forced to the same frequency as the test clock signals. When the test clock signals and the system clock signals have the same frequency, both clock signals can applied to the integrated circuit through a single terminal, whereby providing a terminal for the exchange of other signals with the integrated circuit. Using the same signals for test and system clocks allows selected components to be eliminated.

Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable circuit for the DC termination for a variety of international phone standards. The invention may also be utilized with circuitry for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.

Abstract: A fully integrated, programmable mixed-signal transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the transceiver being programmable and configurable for multiple radio frequency bands and standards and being capable of connecting to many networks and service providers. The RFIC does not use spiral inductors and instead includes transmission line inductors allowing for improved scalability. Components of the transceiver are programmable to allow the transceiver to switch between different frequency bands of operating. Frequency switching can be accomplished though the content of digital registers coupled to the components.

Abstract: A communications system includes a transmitter that transmits a modulated signal having encoded communications data over a communications channel. The transmitter adjusts one of at least modulation and coding at the transmitter based on the received channel state information of the transmitted signal. A receiver determines received signal metrics from the modulated signal. A noise power estimator estimates the noise power of the received communications signal by collecting N data samples from the communications signals, forming a covariance matrix of the N data samples based on a model order estimate, computing the eigenvalue decomposition of the covariance matrix and ranking resultant eigenvalues from the minimum to the maximum for determining the noise power of the received signal. At least one of modulation and coding are adjusted based on the monitored link quality of the communications channel to enhance use of the available channel capacity.

Abstract: A method and a device for signal separation. First, values of signals observed by M sensors are transformed into frequency domain values, and these frequency domain values are used to calculate relative values of the observed values between the sensors at each frequency. These relative values are clustered into N clusters, and the representative value of each cluster is calculated. Then, using these representative values, a mask is produced to extract the values of the signals emitted by V (1?V?M) signal sources from the frequency-domain signal values, and this mask is applied to the frequency-domain signal values. After that, if V=1 then the limited signal is output directly as a separated signal, while if V?2 then the separated values are obtained by separating this limited signal with separation techniques such as ICA.

Abstract: An integrated circuit 18 is provided that includes a memory 32 and a memory modification component 33. The memory 32 maintains a bits count, a gain, and a tone order for each of a plurality of discrete multi-tone sub-channels. The memory modification component 33 operable to control an in-service modification of at least some of the bits count, the gain, and the tone order using a single bits, gains and tone order table.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: Embodiments of the invention describe a method and a device for digital measurement of the momentary frequency response of the phase-path component of a modulator, based on digitally sampling the output frequency of the modulator by clocks and count values derived from components already used by the modulator, e.g. a counter in a divider, and a reference frequency based on a crystal oscillator.

Abstract: An input receiver circuit is provided for receiving a noisy high-speed input signal and for generating a plurality of output signals that can be processed at a low acquisition speed compared to the speed of the high-speed input signal. The input receiver circuit includes an input for receiving the high-speed input signal (data), a plurality of integration elements and a switch for connecting the input to one of the plurality of integration elements for integrating the high-speed input signal. The input receiver circuit further includes a plurality of means for receiving one of the integrated high-speed input signals at a time and for outputting one of the plurality of output signals at a time, and a controller for controlling the switch.

Abstract: Interoperability is achieved between wireless user communication devices that have different speech processing formats and/or attributes. A first wireless user communication device includes a primary speech codec that encodes a first speech message using a first speech encoding format. The encoded speech is then sent to a second wireless user communications device that includes a primary speech codec supporting a second speech encoding format. The first user device receives from the second user device a second speech message encoded using the second speech encoding format. The second speech message is then decoded by the first user device using a second speech decoder supporting decoding of the second speech encoding format. But the first communication device does not support speech encoding using the second speech encoding format—regardless of whether the first communication device includes or does not includes an encoder for encoding speech using the first speech encoding format.

Abstract: A transmission device includes: parallel/serial conversion units; a clock signal transmission unit; a known-parallel data generation unit for inputting known-parallel data to the parallel/serial conversion units; a clock shift unit for sequentially shifting a clock signal, which is outputted from the clock signal transmission unit, by 1 UI of a data signal; sampling units for sampling data signals obtained by serializing the known-parallel data, in accordance with the clock signal shifted by 1 UI; and a diagnostic processing unit for making a diagnosis as to whether the transmission device is operating normally by comparing sampling results with the known-parallel data, and outputting a result of the diagnosis.

Abstract: A baseband receiver having quadrature analog outputs and a plurality of analog control and status signals and a transmit modulator having analog quadrature inputs and a plurality of analog control and status signals are coupled to a transmit processor having a digital output and a plurality of digital control and status signals and to a receive processor having a digital input and a plurality of digital control and status signals by multiplexing analog to digital converters and digital to analog converters such that during a receive time the converters are used for a receive purpose and during a transmit time, the converters are used for a transmit purpose.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: A signal detector comprises a signal translator, a data signal detector, a clock signal detector and an inputting control circuit for detecting abnormal clock and data signals. The signal translator respectively converts differential data signals and differential clock signal into a single data signal and a single clock signal. The data signal detector outputs a data detecting signal according to the single data signal. The clock signal detector outputs a clock detecting signal according to the single clock signal. The interrupting control circuit receives the data detecting signal and outputs a shutdown signal when the single data signal is at high voltage level over a predefined ratio. The interrupting control circuit also receives the clock detecting signal and outputs the shutdown signal when the single clock signal abnormally disappears.

Abstract: Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register for shifting the serial data signal through a number of stages at least equal to (and in many cases, preferably more than) the number of bits in a byte. The output signal of any shift register stage can be selected as the output of the “bit slipping” circuitry so that any number of bits over a fairly wide range can be “slipped” to produce or help produce appropriately aligned bytes. The disclosed bit slipping circuitry is alternatively or additionally usable in helping to align (“deskew”) two or more serial data signals that are received via separate communication channels.

Abstract: An embodiment of the present invention relates to a asynchronous interconnection system comprising a transmitter circuit and a receiver circuit inserted between inserted between respective first and second voltage references and having respective transmitter and receiver nodes coupled in a capacitive manner. The receiver circuit comprises: a recovery stage inserted between the first and second voltage references of the receiver circuit and connected to the receiver node; and a state control stage, in turn inserted between the first and second voltage references of the receiver circuit connected to the recovery stage correspondence with a first feedback node providing a first control signal and having a second feedback node connected in a feedback manner to the recovery stage.

Abstract: A communication system includes an optical transmitter which is differentially driven and an optical receiver that outputs a differential signal. The optical transmitter creates the differential drive signal from an input signal and delivers the differential drive signal to a laser. The differential drive signal is generated with a transformer and RF chokes for floating the laser above ground. The signal detected by the receiver is input as a differential signal to a transformer which then passes the signal through amplifiers and a filter. The optical communication system provides an increased spurious-free dynamic range which is well suited for RF signals and other analog signals.

Abstract: A tuner includes a mixer which receive first and second inputs via a multiplexer in different frequency ranges from different sources such as cable and satellite. A local oscillator supplies signals via a bandswitch which switches the local oscillator frequency range in synchronism with the selection of inputs by the multiplexer. The mixer converts the selected incoming data stream to zero or near-zero intermediate frequency and this signal is filtered exclusively by a variable bandwidth low-pass filter before being converted to the digital domain and demodulated.

Abstract: In order to output an analog signal from which unnecessary out-of-band noise components are appropriately removed in accordance with digital data to be reproduced, a reproduction frequency determination circuit and cutoff frequency selection circuit detect the frequency level of a reproduced signal associated with input digital data and switch an analog LPF to a filter of an appropriate cutoff frequency selected and determined based on the detection result, thereby appropriately removing unnecessary out-of-band noise components from an analog audio signal obtained from the digital data using the filter having the cutoff frequency according to the frequency level of a reproduced signal obtained by reproducing the digital data.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: The optimal allocation of resources—power and bandwidth—between training and data transmissions is considered for time-selective Rayleigh flat-fading channels under the cutoff rate criterion. The transmitter, assumed to have statistical channel state information (CSI) in the form of the channel Doppler spectrum, embeds known pilots symbols into the transmission stream. At the receiver, instantaneous, though imperfect, CSI is acquired through minimum mean square estimation of the channel based on some subset of pilot observations. The cutoff rate is computed and the optimal resource allocation is developed using, for example, a Gauss-Markov correlation model of a communication channel or a Jakes model.