Abstract: A pulse data recorder system and method are provided. Upon the arrival or occurrence of an event or signal, the state of a digital switch is set. Upon receiving a pulse from a readout clock, the state of the switch is stored in a buffer memory, and the state of the switch is reset. As the readout clock is run, a time history of the state of the switch is obtained. The pulse data recorder can feature a plurality of unit cells, for use in imaging or other multiple pixel applications.

Abstract: An electrical circuit used for measuring times is disclosed. In one embodiment, the electrical circuit has a counter, a decoder and a multiplicity of time trap elements. At least the counter and the time trap elements are located together on an integrated semiconductor component. Each time trap element has a data input, a clock input, a delay output and a output port. The time trap element contains a delay element and a flip flop. The delay element outputs a signal change at the data input with a time delay at the delay output. The flip flop has a data input, a clock input and an output port, the data inputs, the clock inputs and the output ports of the flip flop and of the time trap element being connected to one another. The time trap elements are connected as ring oscillator.

Abstract: A signal monitor device that detects a signal propagating on a signal line and that generates a timestamp when the signal is detected. The timestamp may be used in a variety of applications including measuring the propagation delays on signal lines and determining the timing in a system.

Abstract: A pressure-induced counter includes a pressure acquisition unit, a delay unit and a counter unit. The pressure acquisition unit is electrically coupled to the counter unit via the delay unit. The pressure acquisition unit is configured for acquiring a pressure signal of an external pressure applied thereon to generate and output an original electrical signal corresponding to the pressure signal. The delay unit is configured for processing the original electrical signal outputted from the pressure acquisition unit to obtain a processed electrical signal by depressing the leading-edge jitter existing therein. The counter unit is configured for receiving the processed electrical signal transmitted from the delay unit and taking count of the received signals.

Abstract: In a radiation detector (10) for a time of flight positron emission tomography (PET) scanner (2), a radiation sensitive member (20) generates a signal (22) indicative of a radiation detection event. A time to digital converter (34) includes digital delay elements (40) operatively interconnected as a ring oscillator (36, 36?) and readout circuitry (50, 52, 60, 82, 84, 86, 88) configured to generate a timestamp for the radiation detection event based at least on a state of the ring oscillator when the signal is generated. Delay trim elements (46) operatively connected to the digital delay elements set a substantially common delay for the digital delay elements.

Abstract: A frequency measurement device includes: a short gate time counter section that continuously measures a pulse stream signal supplied, and outputs a series of count values that behave like a pulse stream corresponding to a frequency of the pulse stream signal; and a low-pass filter that removes high frequency components from the series of count values to obtain a level signal corresponding to the frequency of the pulse stream signal supplied.

Abstract: A signal processing device includes a detecting part that detects intensity of an input signal, a timer part that includes a time constant circuit and measures time based on a time constant of the time constant circuit, and a determination circuit that counts the number of times of switching of the input signal detected by the detecting part within the time measured by the time constant circuit.

Abstract: A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set.

Abstract: A method of calibrating once-around and harmonic errors of encoded nips is provided. An encoder with an index pulse is used to measure the velocity and rotation of the driven wheel or idler. The geometry of the drive train and wheel and idler is chosen so that their once around and harmonic frequencies are unique such that no other drive errors will generate these frequencies. The method includes running the idler or wheel at substantially constant velocity for N revolutions. Each index triggers the collection of velocity data, which is averaged for N revolutions. This process detects drive train motion errors that are periodic with respect to the timing of the index pulse (i.e., once per revolution of the wheel or idler). Once the velocity errors have been measured, corrections are made. This method may be incorporated in xerographic machines as part of a setup or calibration procedure.

Abstract: A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.

Abstract: Capacitive detection systems, modules, and methods. In one embodiment, time interval measurement(s) are generated that are monotonic functions of the capacitance(s) of capacitive sensor(s) in a capacitive sensing area. In one embodiment, the generated time interval measurement(s), or any other monotonic function(s) of capacitance(s) of capacitive sensor(s) in a capacitive sensing area, may be analyzed to detect the presence of an object near the capacitive sensing area and/or to detect the position of an object near the capacitive sensing area.

Abstract: An integrated circuit (1) that comprises an internal clock circuit (12) with a clock output for clocking functional circuits (10) of the integrated circuit (1). The integrated circuit is provided with a counter circuit (16) and a state holding circuit (18) for use during testing. The integrated circuit is switched to a test mode and a start of a test time interval is signalled. Clock pulses from the internal clock circuit 12 are counted from the start of the test time interval and the state holding circuit (18) is locked into a predetermined state if the internal clock circuit has produced more than a predetermined number of clock pulses from the start of the test time interval. Information about whether the state holding circuit (18) has reached the predetermined state in the test time interval is read from the integrated circuit (1) and the information is used by a test evaluation apparatus (2) to accept or reject the integrated circuit (1).

Abstract: A device for counting the number of rotations of an object in a system, in which a storage means carries counting data designed to represent the number of rotations counted. The counting data is used for conditionally resetting the storage means if and only if two separate conditions are fulfilled, where at least of one of the conditions is the reception of information from an external device, thereby insuring that the counting data represents the number of rotations counted from a predetermined time.

Abstract: A circuit structure for a timer counter counting the cycles of the pulse width of a digital signal corresponding to a clock signal is provided, wherein the signal type of the digital signal is Non-return to zero code. The timer counter circuit structure includes a first counter module and a second counter module. The first counter module receives the digital signal and the clock signal and counts the cycles of the pulse width of the digital signal corresponding to the clock signal while the logic of the digital signal is high. The second counter module receives the inverted digital signal and the clock signal and counts the cycles of pulse width of the inverted digital signal corresponding to the clock signal while the logic of the inverted digital signal is low.

Abstract: Systems and methods consistent with embodiments of the present invention provide a method for the measurement and analysis of particle counts in flow cytometry and hematology instruments. In some methods for the measurement and analysis of particle counts, a corrected histogram of particle distributions is calculated and used to obtain an accurate count of particles and an accurate measurement of other particle parameters.

Abstract: Electronic sensor comprising at least: capture means producing a signal s comprising x pulses during a given capture time, such that a?<x<b?, where a?, b? and x are non-null natural integers, counting means receiving the signal s, which are incremented with each pulse received, comprising a maximum counting capacity equal to z such that (b??a?)?z<a?, where z is a non-null natural integer, resetting the counting when the maximum counting capacity z is exceeded and outputting, at the end of the capture time, a number representative of the number of pulses x of the signal s.

Abstract: Provided is a test apparatus for testing a device under test, the test apparatus including: a pattern generator that generates an expected value pattern of an output signal of the device under test; a timing generator that generates a timing signal indicating a timing for acquiring the output signal of the device under test by delaying a reference clock; a comparator that acquires the output signal of the device under test at the timing designated by the timing signal and compares the acquired output signal to the expected value pattern; and a measurement circuit that starts operating at the timing designated by the timing signal and counts a number of pulses of the output signal of the device under test.

Abstract: The present invention relates, in general, to shoes for measuring the quantity of motion and a method of measuring the quantity of motion using the shoes and, more particularly, to artificial intelligence shoes, in which various numerical values (calorie consumption, body fat, and a pulse), measured by a walking sensor (23), a body fat measurement unit, and a pulse sensor (21) mounted in a shoe body, are displayed in real time on a display unit (32), so that a user can periodically check his or her quantity of motion, and in which calorie consumption and body fat are calculated on the basis of the user's body conditions, so that the precision thereof is high, and such quantity of motion numerical values can be transmitted to various types of external devices, thus enabling the user to periodically manage the quantity of motion thereof.

Abstract: In some embodiments, a chip includes clock generation circuitry to create a clock signal, and reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal. The chip includes a counter to change a count value in response to changes in the reference signal; and count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal and to make at least some of the values in the count storage circuitry related to a duty cycle of the clock signal available to an external tester. Other embodiments are described and claimed.

Abstract: A semiconductor integrated circuit device includes a semiconductor memory and a test circuit. The semiconductor memory includes a memory block having a plurality of memory cells and tests the memory cells. The test circuit includes a controller and a counter. The controller consecutively increments a gate voltage of the memory cells and controls the semiconductor memory so as to read a data from the memory cells provide with the gate voltage. The counter measures, for the gate voltage, the number of memory cells determined to be defective. The controller determines the memory block to be defective when the counter consecutively shows a count falling within a predetermined range during the variation in gate voltage.

Abstract: A detecting apparatus detects the degree of correlation between first events and second events repeatedly occurring in an observed apparatus includes an acquiring unit that acquires second event count values each indicating the number of second events occurring during each first period between each first event and the first event next thereto. A measuring unit measures an observed number of each second event count value derived from the number of times the second event count value is observed. A calculating unit calculates the degree of correlation between the first events and the second events based on the observed number of each second event count value.

Abstract: In one embodiment, eyewear having an activity monitoring capability is disclosed. Activity, such as motion, steps or distance, can be measured by an activity detector. The measured activity can then be used in providing activity-related information to a user of the eyewear. Advantageously, the user of the eyewear is able to easily monitor their degree of activity. For quieter operation, acoustic dampening can be employed. In other embodiments, activity monitoring capability can be provided to products other than eyewear.

Abstract: Counting circuits applied to distance estimation for ultra wideband (UWB) application, in which a first counting unit generates a sequence of pseudo-random number series not including zero, a first recoding unit records a first series and a second series from the sequence according to a first signal and a second signal, and a transfer unit generates a binary counting value according to the first series and second series from the recording unit.

Abstract: A method for reducing oscillations of an output value associated with a program to be operatively coupled to a data processing system. The program having an internal process configured to read an input value provided by the program, the input value adjusting a performance aspect of the internal process, the internal process configured to provide an output value reflecting changes in the internal process responsive to the input value, the output value readable by the program.

Abstract: Disclosed is an integrated circuit device, comprising: a first power rail for supplying power to first latch and a circuit during a first clock phase; a second power rail for supplying power to a second latch during a second clock phase; and the circuit coupled between an output of the first latch and an input of the second latch.

Abstract: A memory test system for peak power reduction. The memory test system includes a plurality of memories, a plurality of memory built-in self-test circuits and a plurality of delay units. Each of the memory built-in self-test circuits comprises a built-in self-test controller for receiving a clock signal and producing a plurality of required control signals to test one of the memories. Each of the delay units is coupled between two adjacent built-in self-test controllers. The clock signal input to one of the built-in self-test controllers is received by the delay unit to produce a delayed clock signal, and the delay unit outputs the delayed clock signal to the other.

Abstract: A temperature monitoring technique that eliminates the need for bipolar devices. In one embodiment of the present invention, a long-channel MOS transistor is configured in a diode connection to sense change in temperature. The diode drives a linear regulator and an oscillator. The oscillator in turn drives a counter, which counts pulses for a fixed period of time. The system clock on the chip is used as a temperature-independent frequency to generate a count. The temperature-dependent frequency is counted for a fixed number of system clock cycles. The present invention eliminates band gap circuitry currently used in most thermal sensing devices to provide a temperature-independent reference.

Abstract: A digital counter with a dial position having a hardware part which determines the n lowest-value bits of the dial position and a software part which determines the remaining higher-value bits of the dial position includes first and a second software parts as the software part with the dial position being a combination of the first software part and the hardware part when the hardware part is in a first counting range, and being a combination of the second software part and the hardware part when the hardware part is in a second counting range.

Abstract: There is provided a scan test system comprising: a semiconductor device including a scan register connected between an input/output pin on an analog input side and an internal system logic; a semiconductor device including a scan register connected between an input/output pin on an analog output side and an analog sensor; and an analog wiring connecting the input/output pins each other. Thus, the scan register can be chained to thereby constitute a boundary scan register chain, and thereby JTAG control can be carried out by use of TAPC. Therefore, monitoring inspection where probes are set up by high-density-assembling of semiconductor devices and the multiple pins of low-cost devices, can be achieved.

Abstract: A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.

Abstract: The invention provides an electrooptic device and an electronic apparatus, in which the electrical characteristics of many thin-film switching elements formed in a substrate to support an electrooptic material can be accurately inspected. The invention also provides a method for making the electrooptic device. In a TFT array substrate of a liquid crystal device, an inspection TFT is formed in one of dummy pixels disposed at the periphery of a pixel region. A pixel electrode connected to a drain region of the TFT functions as a first inspection pad. In an adjacent dummy pixel, the pixel electrode electrically connected to an extended portion of a data line functions as a second inspection pad. In another adjacent dummy pixel, the pixel electrode electrically connected to an extended portion of a scan line via a junction electrode functions as a third inspection pad.

Abstract: A method and system for improved accuracy in period counting using a tunable oscillator, such as a voltage controlled oscillator, without an additional reference oscillator. The method and system use digital logic to correct the count made by a counter by loading the counter with a preset. The invention is suitable for use with any digital circuit that has a tunable oscillator and programmable digital logic.

Abstract: In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.

Abstract: Systems, devices and methods are provided for measuring battery current. According to one aspect, a medical device is provided that comprises a battery, a pulse generator, and a current measuring device. The pulse generator draws a pulse generator current from the power source, and the current measuring device determines the pulse generator current or tracks charge depletion from the battery. The current measuring device comprises an oscillator and a counter. The oscillator produces an oscillating output with a frequency of oscillation dependent on the pulse generator current, and the counter provides an oscillation count for the oscillating output. The current measuring device is capable of being calibrated while continuously determining the pulse generator current. In one embodiment, the current measuring device includes at least two current sources, each including an operational amplifier that has an autozeroing feature.

Abstract: A method and apparatus for detection of missing pulses from a repetitive pulse train including signal detection circuits for capturing the rising and/or falling edges of an input signal, time-stamping the captured edges, calculating the maximum and minimum instantaneous frequency over a specified time period, and displaying such frequency values. Instantaneous frequency values between any two adjacent edges are calculated based upon the time-stamps of the edges. The instantaneous frequency values in a specified time period are then sorted to find the minimum and maximum frequency values for that time period. These instantaneous frequency values are displayed in the form of a histogram evidencing the occurrence or lack of occurrence of missing pulses from the input signal.

Abstract: A filter on which living bacteria are captured is processed with an extraction reagent and a luminescence reagent. The state of luminescence of the filter is photographed by a television camera 1 including an optical system and an image acquisition means such as a charge coupled device. The number of luminous points is counted from data for the image of the luminous points of fluorescence originating in microbes through an image processing device 3 and a data-analyzing device 4. The result of the count is shown on a display 5. In the analysis of the data, when there exists a first luminous point adjacent to a second luminous point, the first and second luminous points are grouped and counted as one luminous point. A process for eliminating the effect of the diffusion of light from a luminous point of great luminance is performed.

Abstract: A testing device for checking a clock signal generated by a clock pulse generating circuit. The clock pulse generating circuit outputs a clock signal and a multiplied clock second signal. The testing device includes a reset circuit, a dividing unit and a mask circuit. The reset circuit receives a first reset signal and the clock signal and then generates a second reset signal synchronous with the clock signal. The second reset signal controls the dividing unit and the mask circuit. Inside the dividing unit, the multiplied clock signal is divided by an integral multiple to produce a divided clock signal. The divided clock signal is then passed to the mask circuit where uncertain portions of the third signal are blanketed to produce a masked clock signal. The masked clock signal is sent to a tester where cycle width of the masked clock signal is measured and first reset signal is sent to the reset circuit.

Abstract: This invention relates to a method and apparatus for improving the precision of at least one of neutron coincidence counting and neutron multiplicity counting. The method includes the steps of: (1) sampling the real and accidental coincident pulses at the incoming pulse rate; and (b) sampling the accidental coincidences at a clock rate, wherein the clock rate is much faster than the pulse rate. The clock rate is faster than the pulse rate by a factor of 5 to 10 (in the preferred embodiment, approximately 4 MHz).

Abstract: A semiconductor integrated circuit device has a data holding section for storing information, a counter for counting the number of externally applied pulses, and a comparison/verification section. The comparison/verification section compares an output of the counter with an output of the data holding section, and verifies whether the outputs match or not. This configuration serves to reduce the number of wiring lines formed from pads to a comparison/verification circuit (a signature circuit), and thereby achieves a reduction in layout area and facilitates efficient layout work.

Abstract: The invention relates to dust/particle monitors, and particularly but not necessarily exclusively to a method of monitoring fine particles harmful to humans in working environments. Equipment and methods of detection are known but which have several disadvantages such as no instantaneous warnings of excessive exposure, bulky sampling equipment, prone to errors due to poor handling of particles, and fluctuating flow rates of air borne particles. The object of the invention is to provide a method and equipment that avoids those disadvantages mentioned above, an objective met by a method of monitoring dust/particulate material concentrations in air, comprising drawing air through a monitor at a predetermined rate to enable particles to pass through a measurement section one at a time, whereby they may be individually detected and counted.

Abstract: An event counter is disclosed which, in one embodiment, provides a reaction timer to time a user's response time to an event. In a second embodiment, the event counter provides a counting device to count the number of occurrences of events or the magnitude of an event. The invention uses a commercially available stopwatch to time the response time. The start/stop switch of the stopwatch is connected to a signal generator such as a piezoelectric element. In one variation, the internal piezoelectric element used as a beeper in the stopwatch is used as the signal generator. In a second variation, the event timer is further provided with a circuit to allow a higher voltage LED to be driven by a lower voltage of the system battery. In yet another variation, the event timer further includes a random delay circuit to randomly delay the start time of the stopwatch. Random delay is provided without a microprocessor by using a variable current switch and two RC circuits having different tau values.

Abstract: A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit. The logic circuit may be configured to generate one or more control signals in response to one or more control inputs. The counter circuit may be configured to generate a first counter output and a second counter output in response to (i) the control outputs and (ii) one or more inputs. The counter may comprise a first portion configured to generate the first counter output and a second portion configured to generate the second counter output.

Abstract: The present invention relates to a method for detecting a minor variation of capacity via accumulation and a circuit for detecting the same. An oscillated pulse signal is generated by a delay accumulating circuit which includes a logic device having an open drain and a pull up resistance. The generated pulse signal is then sent to a microprocessor via a counter. The microprocessor will determine whether there is a variation of the frequency of the pulse signal. When a variation of capacity is detected at the detecting polar plate connected to the testing terminal of the delay accumulating circuit, the microprocessor picks up and determines this variation. The present invention can be applied to a plurality longitudinal and transverse polar plates. When a conductor is moved along the polar plates, the variation of the capacity resulting from the movement of the conductor above the static capacity detecting plate can be readily detected.

Abstract: A method and apparatus for detection of missing pulses from a repetitive pulse train including signal detection circuits for capturing the rising and/or falling edges of an input signal, time-stamping the captured edges, calculating the maximum and minimum instantaneous frequency over a specified time period, and displaying such frequency values. Instantaneous frequency values between any two adjacent edges are calculated based upon the time-stamps of the edges. The instantaneous frequency values in a specified time period are then sorted to find the minimum and maximum frequency values for that time period. These instantaneous frequency values are displayed in the form of a histogram evidencing the occurrence or lack of occurrence of missing pulses from the input signal.

Abstract: A system and method for detecting fault conditions within a vehicle recording device are disclosed herein. The fault detection technique may be implemented in a vehicle in which are incorporated one or more vehicle sensors for monitoring one or more operational parameters of the vehicle. A recording device disposed within the vehicle is used to collect vehicle operation data produced by the one or more vehicle sensors.The fault detection technique of the invention contemplates storing a current time value at regular intervals during periods in which the recording device is provided with a source of main power. Time differences are determined between consecutive ones of the stored time values, and the time differences compared to a predetermined maximum value. A power loss fault condition is registered when at least one of the time differences exceeds the predetermined maximum value.

Abstract: A pulse-width modulation system provides means for controlling dual-coil, air-core gauges at a various rates over 360 degrees. The system moves a dial needle from one octant of the gauge to the next in response to coded data representing measurands by holding one coil at 100% duty cycle while applying a PWM of a varying duty signal to the other coil. When the magnitude of the measurand dictates that the needle should move into another octant of the dial, the PWM signal and the 100% duty cycle signal are interchanged between the coils in a manner permitting the needle to move to other octants of the dial. The system includes a variable PWM count clock that permits selecting at least PWM rates and periods for forming PWM duty cycles ranging from 0% to 100%.

Abstract: Sensors are provided for monitoring the speeds of a turbine and a compressor interconnected by a shaft. Signals from the sensors are used to control the direction of counting of a counter. If the shaft is intact, the counter repeatedly counts up from and returns to zero. If the shaft breaks, the counter counts upwardly and a signal is given when the count in the counter exceeds a threshold value.

Abstract: A system and probe for indicating the level of material in a vessel as a function of material capacitance comprising a resonant circuit including a capacitance probe adapted to be disposed in a vessel so as to be responsive to variations in capacitance as a function of material level. An rf oscillator has an output coupled to the resonant circuit and to a phase detector for detecting variations in phase angle as a function of probe capacitance. Level detection circuitry is responsive to an output of the phase detector and to a reference signal indicative of a predetermined level of material for indicating material level as a function of a difference between capacitance at the probe and the reference signal. In the preferred embodiments of the invention disclosed, an automatic calibration circuit adjusts the resonance characteristics of the parallel resonant circuit of the reference signal indicative of a predetermined reference material level.

Abstract: In the case of setting one comparison timing in one operation period, a select signal is set to the "0" level, by which first, second and third counters are each put in the state of operation of a 1-to-4 frequency dividing counter which produces four frequency-divided outputs sequentially displaced apart in phase in a cyclic order. A first comparison clock is frequency divided by the first counter and its four frequency-divided outputs are used to latch a comparison signal in four first latch circuits in a sequential order, by which the comparison signal is demultiplexed and expanded. A first system clock is frequency divided by the second counter down to 1/4 and its four frequency-divided outputs are used to latch an expected value signal in four second latch circuits in a sequential order, by which the expected value signal is demultiplexed and expanded. The corresponding ones of the outputs from the first and second latch circuits are subjected to logical comparison by four comparators.

Abstract: A phase shift vernier for providing an output signal with continuously variable delay based on an input phase delay is disclosed. The apparatus comprises delay value means, a ring oscillator, a multiplexer, a DAC, and a signal combiner. The delay value means is adapted for receiving an input phase delay value, indicating the amount of delay for an output signal. The ring oscillator is adapted for circulating an oscillating signal through multiple differential stages to generate multiple quadrature signals. The oscillating signal has a predetermined frequency and each of the differential stages is connected in series. Each of the stages delays its inputs by a predetermined amount to generate its differential outputs from each stage. The multiplexor is coupled to the ring oscillator and to the delay value means to receive the quadrature signals from the ring oscillator.