Abstract: The present disclosure relates to a signal processing apparatus and method that enables to reduce required power. In the signal processing apparatus, a RTC of a main chip and a RTC of a power supply chip are synchronized before power supply of the main chip is stopped, and the RTC of the main chip is synchronized with the time of the RTC of the power supply chip after the power supply of the main chip is restored. In this way, the RTC uses continuous time information before and after the stop. The present disclosure is capable of being applied to, for example, a GPS module in which a digital circuit includes a plurality of chips.

Abstract: A billing system used together with an image forming apparatus for forming an image on a sheet and discharging the sheet includes: a counting unit for counting, when a print job is interrupted, a billing unit number for a sheet which already has an image formed thereon when the interruption occurs and which has not discharged from the image forming apparatus; a determination unit for determining whether the print job is continued or cancelled after the print job is interrupted; and a billing unit for counting a billing counter corresponding to an amount for which the image forming apparatus is used, and billing a user who uses the image forming apparatus according to the billing counter, wherein the billing unit switches whether the billing counter is counted by using a count result of the counting unit in accordance with a determination result of the determination unit.

Abstract: A battery powered device is able to maintain a clock value when the battery is removed for a short period. During a first time period, while the battery is in the device, clock pulses derived from a first oscillator are counted at a first rate in a first counter that represents the clock value. During a second time period following the first time period, while the battery is removed, the value of the first counter is maintained independent of any clock pulses derived from the first oscillator, clock pulses derived from a second low power oscillator are counted in a second counter. During a recovery time period following the second time period, clock pulses derived from the second oscillator are again counted in the second counter, while clock pulses derived from the first oscillator are counted in the first counter at a second rate higher than the first rate, the duration of the recovery time period being determined based on the number of pulses counted in the second counter during the second time period.

Abstract: A counter circuit and method of controlling such a counter circuit, including a first counting section that counts in accordance with a state-cycle, and a second counting section clocked by the first counting section. At least one invalid counting state is introduced by controlling the second counting section to change its state before the first counting section has completed the state-cycle; and the invalid counting state is then detected and corrected. Thereby, some redundancy is introduced in the counter, which can be used to detect and correct incomplete switching of counter states.

Abstract: A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.

Abstract: An encoder reset device and method that allows for an encoder to be reset and/or recharged at virtually any location. A reset device and method of the present invention also allows the reset/charging process to take place simultaneously with the removal of an encoder-equipped device that is being replaced, as a device of the present invention does not require the use of an encoder-equipped device controller to perform the reset/charging process.

Abstract: A method, an apparatus, and a computer program are provided for generating an error detection state and correction of code patterns. Generally, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment is difficult. A circuit, however, can be employed that periodically detects the functionality of the dI/dt circuit to indicate success or failure. When errors are detected, the circuit allows for erroneous codes to be replaced with accurate ones. Using this circuit, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment can be more easily achieved.

Abstract: An image processing apparatus including a scanner with a direct control section configured to control a scanning operation of the scanner so as to input image information from an original document and a main body configured to process the image information. The main body includes a control section configured to perform an initializing process for the main body. Further, a homing operation of the scanner is performed by the direct control section independently of the initializing process of the control section of the main body, when power is supplied to the image processing apparatus or when the image processing apparatus is returned from a shutdown state.

Abstract: A digital counter with a dial position having a hardware part which determines the n lowest-value bits of the dial position and a software part which determines the remaining higher-value bits of the dial position includes first and a second software parts as the software part with the dial position being a combination of the first software part and the hardware part when the hardware part is in a first counting range, and being a combination of the second software part and the hardware part when the hardware part is in a second counting range.

Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

Abstract: A counter circuit includes a plurality of flip flop circuits (FF circuits) sequentially connected for receiving a common clock signal, and two-input logic gates each having an input connected to an output of a corresponding FF circuit and the other input connected to an output of a common FF circuit, and of which output signal is supplied to an FF circuit positioned at the post stage of the corresponding FF circuit. A booby trap is realized by the two-input logic gates. The value input to each of the FF circuits is determined by logical operation of at most two logical values, so that the counter circuit can be adapted to the increasing frequency of a clock signal CLK. Thus, the counter circuit with the booby trap, capable of performing high-speed operation can be provided.

Abstract: A system and a method are characterized in that the method of detection can be configured by varying a size and/or a position of a time slot to be taken into consideration for the detection and/or by varying relevant bits of the counts to be compared. This makes it possible to individually adapt the detection method to various or varying requirements at any time and with a minimum of expenditure required.

Abstract: A counting device, comprising: an input 105, 107 for receiving an input signal having at least three distinct input states; memory means 810 for storing a count; and means 620 responsive to a predetermined sequence of input states of said input signal to vary said count, wherein said predetermined sequence includes the at least three input states.

Abstract: The present invention provides a method of processing signals of encoders and an apparatus employing the same by each of which increase and decrease of a counter value can be made to match an angle of a rotational angle of two-phase incremental encoders all the time.

Abstract: The track counter circuit of the present invention is for counting tracks. The circuit indicates a circuit for generating a first signal indicating a first track has been crossed and a second signal indicating a second track has been crossed after the first track, a circuit for determining when a third track should have been crossed and generating a missing signal to indicate the third track, a circuit for determining a valid track period based on the first signal and the second signal, and a circuit for maintaining the valid track period when said missing signal is generated. The track counter circuit for counting tracks may use the first signal as a MIRR signal. Additionally, the second signal may be a MIRR signal.

Abstract: A method of selecting a pinion for a vehicle speedometer system uses a transmission output speed sensor and a transmission controller which applies a pinion factor to the signal from the sensor to generate an output signal representing the speed of the vehicle.

Abstract: An electrical apparatus (e.g., copying apparatus) equipped with a counter for counting the number of specific cycles. Allowance or prevention of an operation cycle is controlled in accordance with voltage changes at a predetermined position of the controlling circuitry supplying a driving voltage to the counter. A specific operation of the electrical apparatus is enabled by connection of counter.

Abstract: The revolutions of a diesel engine are counted by providing vibration detector converting the vibration propagating through the fuel injection pipe into an electric signal; an amplitude sorter for receiving the electric output signal of the detector and providing an output signal when the amplitude becomes larger than a predetermined level; a waveform shaper for receiving the output signal of the sorter and converting respective pulse groups to single pulse outputs. The respective pulses from the sharper are judged to determine whether signal pulse in the present period is within a predetermined allowable range or not, and thereby determining whether respective pulses are "normal" pulses or not. The number of normal pulses per unit time are counted and displayed on a monitor.

Abstract: An anti-fraud device for digital measuring instrument includes a sensing encoder integrated circuit combinably packed with a sensor, and a measuring decoder integrated circuit combinably packed with a measuring meter for receiving signal as sensed from the sensor through a transmission line. When an external-signal generator is fraudulently installed on the transmission line for increasing output signals into the meter for cheating a meter fare, an external signal from the external-signal generator will be first checked by the measuring decoder integrated circuit provided before the measuring meter to be different from a prestored data in the measuring. Then the measuring decoder will not output a valid pulse to be counted in the measuring meter, without increasing an unwanted meter fare or fees for preventing a fraud matter.

Abstract: A polling device (10) includes a housing (12), pushbuttons (14, 16) mounted on the housing for receiving customer responses to an inquiry, circuitry for counting and storing the number of times each pushbutton (14, 16) is depressed, and a time delay circuit for disabling the counting circuitry for a predetermined period of time after one of the pushbuttons has been depressed for discouraging repetitive voting. A display unit (46) for reading and displaying the number of times each pushbutton (14, 16) has been depressed is also provided.

Abstract: A method of determining a calibration factor used to calibrate vehicle speed signals includes the steps of driving the vehicle over a measured distance, counting the pulses generated while driving the vehicle over the measured distance, and then calculating the calibration factor from the number of pulses counted and a nominal pulse count stored in memory. An indication of the difference in a reference speed using the old and new calibration factors is displayed to the vehicle operator who can then choose to accept or abort the new calibration factor.

Abstract: A timeout circuit with internal calibration includes an oscillator (11) for generating an initial frequency for division by a modulo-n counter (20). The counter (20) receives the value of n from a calibration register (22) and divides the frequency of the oscillator by the value of n. A gate (26) prevents alteration of the contents of the register (22). The output of the counter (20) provides a calibrated frequency which is further divided by a day counter (32) for output to a countdown counter (34). The countdown counter (34) provides a predetermined countdown of the signal output by the day counter (32) and, at the end of the count, generates a Timeout signal. The predetermined countdown value is determined by a value stored in a register (36) which can be protected by a customer lock out circuit (42).

Abstract: A remote controlled object counter has a data counter which may e.g. be buried beneath a trail for counting the passage of people along the trail and a data collector separate from the data counter. The data counter employs an inductive loop with an oscillator and a processor for detecting the oscillator frequency and transmitting a corresponding data signal through radio transceivers in the data counter and the data collector for processing in the latter. To enable adjustment of the data counter sensitivity without physical contact, an adjustment signal generated in the data collector is sent through the transceivers to the data collector processor.

Abstract: A delay circuit for a data manipulation circuit is provided in which data update signals to the data manipulation circuit are delayed when a data access signal is present so that data is not manipulated during accessing of the data.

Abstract: A self correcting single event upset-hardened CMOS register comprises a master portion and a slave portion. The master portion is coupled to a source of data and includes a feedback means such that said master portion can store said data during the first phase of a bi-phase clock signal. A slave portion including a second feedback path, has an input coupled to the output of said master portion and has an output which comprises the output of the register. An odd plurality of inverters is placed in series in the feedback path so as to isolate each node which is a possible site for high-energy particle impingement from other nodes in the loop and to attenuate and delay any resulting impulses such that the state of the error pulse cannot be maintained thus permitting the slave loop to remain in the state determined by the preceding data pulse.

Abstract: A method for the non-volatile storage of the counter reading of a digital counter including storage locations for receiving counter readings and state information of a counting cycle, includes successively storing an actual counter reading in two independent counter reading registers, initially marking one of the registers containing a preceding counter reading, at least up to completion of a counter reading transfer into the other of the registers, subsequently marking the other register, and after a voltage interruption, transferring the counter reading of the marked register into the counter for presetting and selectively incrementing by 1, and an apparatus for carrying out the method.

Abstract: A method and apparatus for counting the exact number of electrical circuit components carried by a length of component dispensing tape is disclosed. In the preferred embodiment, the invention uses optical detectors to detect the transmission of light through tape index holes and component carrier compartment holes and variously to increment or inhibit operation of a counter accordingly. In one form of the invention, the circuitry is adapted to detect automatically whether the tape is optically transmissive or opaque and to modify the counting scheme accordingly.

Abstract: A device for counting objects in a stacked relationship which includes a bifurcated optical cable, a light source for directing light through the bundle at the stack and a sensor for generating a signal proportional to the light reflected by the stack. The signal is digitized and fed to a digital counter. Various displays connected to the counter indicate the count results.

Abstract: A timing system which includes a timer circuit, a source of first clock pulses for advancing the timer circuit, and a circuit for reading out the timer circuit in synchronism advanced therewith and where there is also included a second source of clock pulses asynchronous with respect to the first source of clock pulses, a synchronizing circuit is provided for storing an indication of the receipt of each second clock source pulse. Then the timer is advanced only when a pulse is produced by the first clock source and the indication is present that a signal has been produced by the second clock source.

Abstract: A digital filter circuit includes first and second counters which set and reset a latch circuit at predetermined counts. Clock pulses and the input signal are passed through a gate circuit to the first counter which outputs a set signal to the latch circuit only if the input signal is maintained at a high level for the predetermined count. Clock pulses and the inverted input signal are passed through a gate circuit to the second counter which outputs a reset signal to the latch circuit only if the input signal is maintained at a low level for the predetermined count. In this manner noise pulses on the input signal are filtered out of the output signal obtained from the latch circuit.

Abstract: In an apparatus for counting enumeration input pulses according to the present invention, an enumeration input pulse is put in parallel in a plurality of stages of logical product computing oscillator means, and counting in the logical product computing oscillator means of the subsequent stage is advanced on condition that an output of termination of counting is put out from the logical product computing oscillator means of the precedent stage. For this purpose, delay means is arranged after the logical product computing oscillator means to set the time from the point of output of the logical product computing oscillator means of the precedent stage to the point of termination of a predetermined delay time so that this time is longer than the width of the enumeration input pulse and shorter than the frequency thereof.

Abstract: An indicating device in a measuring machine in which the flickering of an indicated value due to vibrations of the machine and the like is avoided. The indicating device includes a flickering sensing circuit for receiving up signals or down signals outputted from an encoder as input signals thereto and sensing the change in the signals from the up signals to the down signals and vice versa. When the change in the signals is sensed by this flickering sensing circuit, a hold signal having a predetermined period of time is outputted from a hold circuit, whereby renewing storage of counted values from the counter by a latch circuit is interrupted for a predetermined period of time.

Abstract: Detectors (11a-d) are located at a plurality of locations and include go, no-go decision processor apparatus for subjecting outputs of the detectors (11a-d) to a go, no-go decision process. First signal generator and transmitter apparatus (12a-d) are interconnected to said go, no-go decision processor apparatus for generating and transmitting signals responsive to the output of said go, no-go decision processor apparatus, the signals being transmitted in a wave form configured to maximize differentiation from noise and interference. First data receiver apparatus (13) receives the signals from said first signal generator and transmitter apparatus (12a-d) and includes wave form recognition apparatus. A reprogrammable central processor apparatus (14) is interconnected to the data receiver apparatus (13) for providing action outputs representative of one or more actions to be taken in response to one or more signals received from the first data receiver apparatus (13).

Abstract: An electronic postage meter includes electronic circuitry for providing an accounting of the number of mailpieces imprinted with postage, and the amount of postage imprinted on such mailpieces. An electro-optic sensor connects with a mechanical drive of a printing drum of the meter to sense successive rotations of the printing drum, one rotation occurring for each imprinting of postage. A comparison circuit compares the one-bit signal provided by the electro-optic sensor with the least significant bit of a count of the mailpieces, which count is provided electronically by the accounting function. Any discrepancy between the least significant bit of the mechanical count and the least significant bit of the electronic count serves as a warning of a malfunction, or of tampering, of the postage unit. An error-signal circuit connected to the comparison circuit terminates operation of the meter upon the occurrence of a discrepancy between the mechanical and electrical counts.

Abstract: Offset-error included data normally is output from a single ramp analog to digital converter in response to input information applied thereto during light or cuvette sample intervals. During dark sample intervals between the cuvette sample intervals, the input information is blocked from the converter and the converter is operated with the output counter counting down to a dark count representing the offset error of the counter. During the next cuvette sample interval the counter counts up from the dark count effectively subtracting out the offset error introduced by the converter.

Abstract: An electrical impulse operated number wheel counter with coaxial number wheels (2); transfer pinions (8); a reciprocable pawl (12) engaging the first number wheel and a solenoid (20) driving the pawl, has a series of leaf springs (33) carried on the solenoid armature (24). In the rest position the leaf springs (33) engage bosses (9) on the transfer pinions to ensure that the number wheels (2) are correctly aligned but when the solenoid (20) is energized to effect a count, the movement of the armature (24) lifts the leaf springs away from the transfer pinions (8) which therefore rotate unhindered. An additional effect of the leaf springs is to reduce the power consumption of the counter and this effect can still be achieved with other spring arrangements. A shock resistance element (50) is freely rotatably mounted in the path of the pawl (12) so as to be struck in the event of shock induced movement of the pawl, substantially to eliminate spurious shock induced counts.

Abstract: A usage control system for copiers and the like, adapted to connect to the copier through the existing accounting system connection. A check-operated device, such as a coin box or magnetic card reader, supplies the copier with a signal to initiate operation. When the operation has progressed, the copier supplies a signal intended to increment the counter in the accounting system. After a suitable delay, permitting completion of the copy cycle, the operate signal is reset, and the copier is disabled. As an option, power to the copier may be controlled. The system requires no internal connections or modifications to the copier.

Abstract: A method of sampling accurately the instantaneous content of a high speed counter without interrupting the counting process is provided. The method is applicable even when the higher order digits of the counter are constructed by slower switching circuits configured in either a synchronous or ripple-through arrangement. The switching and carry propagation times of these higher order counters need not be shorter than the time between successive events being counted. Sampling of the contents may be made repeatedly in the interim without affecting the totality of the final count.

Abstract: A gun shot control unit for a seismic exploration system compensates for the inherent delay between the shot command signal and the actual occurrence of the seismic pulse. A digital clock is synchronized with an external source. Timing pulses occurring at a time preceding the timing pulse upon which the occurrence of a seismic pulse is desired are produced by the clock. These timing pulses start a digital counter at a time preceding the desired time of occurrence of the seismic pulse. This counter is adjustable so that the delay which interposes between the timing and the actual occurrence of the seismic pulse can be minimized.