Abstract: Disclosed is a method and apparatus for a modular high performance low power divider with 50/50 duty cycle output. The modularity offers custom dividers to be quickly developed while maintaining minimum power usage. A multi-modulus divider (MMD) receives an input signal and outputs an MMD output signal. The MMD includes a chain of modulus divider stages in such a way as to generate any divide value from 1 to 2(n+1)?1 (n is the number of cascaded elements) while maintaining a 50/50 duty cycle output. Power can be dramatically reduced as the frequency of each subsequent element is halved. The modular nature allows rapid development of any dividers simply by adding more elements to the chain.

Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a high-frequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the high-frequency component reduced.

Abstract: A frequency divider includes a phase selection circuit, control circuit and a retiming circuit. The phase selection circuit is arranged to receive a plurality of input signals with different phases, and generate an output signal by selectively outputting one of the input signals according to a plurality of retimed signals. The control circuit is arranged to receive the output signal to generate a plurality of control signals. The retiming circuit is arranged to retime the control signals to generate the retimed signals according to the input signals.

Abstract: A digital frequency divider including a parallel output register, a presettable asynchronous counter and a decoder. The parallel output register contains a desired count value. The presettable asynchronous counter has its preset data inputs coupled to the output of the parallel output register. The decoder receives its input from the data outputs of the presettable asynchronous divider and its output coupled to the load input of the presettable asynchronous counter.

Abstract: A frequency divider is disclosed. The frequency divider includes a multi-modulus prescaler to perform a frequency division by a modulus M, wherein M is an integer between N and 2*N?1 and N is a power of 2. The frequency divider also includes a programmable counter to output the digital representation of M and an output clock signal. For the frequency divider, M equals N plus D minus D\N for each edge of the multi-modulus prescaler output clock CKpr wherein the counter samples the digital representation of D and D\N denotes an integer part of D divided by N, and M equals N for each subsequent edge of the prescaler output clock CKpr wherein the counter does not sample the digital representation of D.

Abstract: A multiple-modulus divider and an associated control method are provided. The multiple-modulus divider includes a divisor loader, a multiple-modulus dividing circuit and a modulus controller. The divisor loader downloads a divisor when a download signal indicates a start of a division period. The multiple-modulus circuit includes a plurality of cascaded divisors, and provides an output frequency according to an input frequency and the divisor. The dividers respectively output a plurality of modulus output signals, and each is operable under either a close-loop state or an open-loop state. The modulus controller selects and controls one of the dividers according to the divisor, and ensures the selected divider is maintained at the open-loop state when the division period ends. The download signal corresponds to one of the modulus output signals.

Abstract: A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd.

Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a high-frequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the high-frequency component reduced.

Abstract: A multi-modulus divider includes a chain of n dual modulus divider cells in cascade and connected in a ripple configuration where the last (n-k) of the divider cells are state-parked dual modulus divider cells. The state-parked dual modulus divider cells are forced to a given logical state when the divider cell is bypassed. The state-parked dual modulus divider cells ensure that the multi-modulus divider can change between different number of cells without clock glitches or clock errors. The multi-modulus divider is therefore capable of achieving a wide division range with seamless transition between division ratios.

Abstract: Fractional-N divider circuits include a multi-modulus divider, which is configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof. This division is performed in response to an overflow signal received at a second input thereof, where N is an integer greater than one. A phase correction circuit is configured to generate a second reference signal in response to a divider output signal generated by the multi-modulus divider. A divider modulation circuit is provided, which is configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by the multi-modulus divider. The divider modulation circuit includes a segmented accumulator, which is configured to generate a plurality of segments of a count value having at least one period of latency therebetween.

Abstract: A frequency divider based on a series of divide-by-2/3 cells and divide-by-1/2/3 cells using extended division range is disclosed. The frequency divider uses modified divide-by-1/2/3 cells and additional circuit elements to correctly divide an input frequency by a divisor on successive output cycles while the divisor transitions across an octave boundary. The frequency divider creates a divide-by-1 mode for unused divide-by-1/2/3 cells in the series of cells. The divide-by-1 mode passes the input clock in the unused latches of each unused divide-by-1/2/3 cell as opposed to having each unused divide-by-1/2/3 cell implement divide-by-3 mode.

Abstract: A clock divider circuit. The clock divider receives m input clock signals each of the same frequency. Each input clock signal after the first has a phase offset of 2?/m from the previous input clock signal. The clock divider divides the frequency of the input clock signals by an integer of division K. The clock divider includes a counter that receives the first input clock signal and provides one or more count signals. The clock divider also includes m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal. Each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2?K/m phase offset from the previous clock output signal.

Abstract: An integrated circuit includes a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal and a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal. The integrated circuit further includes a multiplexer circuit configured to selectively pass the first and second divided clock signals responsive to a third control input.

Abstract: A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.

Abstract: A frequency measurement device for measuring a frequency of a signal to be measured including a pulse signal, includes: a signal multiplier section that multiplies the signal to be measured by n (n is an integer) and outputs a multiplied signal; a counter section that counts the multiplied signal with a predetermined gate time and outputs a count value of the frequency of the signal to be measured at a predetermined period; and a low-pass filter that outputs a signal corresponding to the frequency of the signal to be measured based on the count value outputted at the predetermined period.

Abstract: A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle. Each of the logic circuit blocks includes a plurality of first transistors coupled in parallel between a first reference voltage and an output terminal, and a plurality of second transistors coupled in series between a second reference voltage and the output terminal.

Abstract: In one embodiment, a clock divider circuit preserves characteristics of both a rising edge and a falling edge of a source clock. The clock divider circuit may include a counter, a flip-flop, and an output. The counter is configured to divide a source clock signal into a divided clock signal. The flip-flop is configured to receive the divided clock signal and an inverse of the source clock signal to trigger the flip-flop. The output includes a logic gate configured to output a final clock signal based on a logical union of an output of the flip-flop and the divided clock signal. The final clock signal includes the jitter from the falling edge of the source clock and the jitter from the rising edge of the source clock.

Abstract: The timing generation circuit includes a binary counter constituted of three T-flip-flop circuits, and a binary state at reset of the binary counter is also used at system reset and in generation of the output pulses, to generate eight output pulses having different timings from eight binary states generated by the binary counter and including the state at the reset. At the system reset, a reset signal to the binary counter is delayed, so that an output of a decoder circuit at the reset of the binary counter is delayed. Therefore, the output of the decoder circuit is masked with a fast reset signal, so that the output of the decoder circuit at the system reset can be prevented from being reflected in an output terminal.

Abstract: A clock divider circuit. The clock divider receives m input clock signals each of the same frequency. Each input clock signal after the first has a phase offset of 2 ?/m from the previous input clock signal. The clock divider divides the frequency of the input clock signals by an integer of division K. The clock divider includes a counter that receives the first input clock signal and provides one or more count signals. The clock divider also includes m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal. Each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2 ?K/m phase offset from the previous clock output signal.

Abstract: A frequency measuring apparatus includes: a high-order digit calculation section adapted to measure an input signal and output a high-order digit value of a frequency value of the input signal; a low-order digit calculation section adapted to measure the input signal and output a low-order digit value of the frequency value of the input signal; and an adding section adapted to add the high-order digit value and the low-order digit value to each other to output the frequency value of the input signal.

Abstract: A multiphase clock generation circuit includes: a first frequency divider to generate a first intermediate clock and a second intermediate clock; a second frequency divider to generate output clocks of a first group including a first output clock and a second output clock; a third frequency divider to generate output clocks of a second group including a third output clock and a fourth output clock; a selector to supply one of the second intermediate clock and a value to the third frequency divider in response to a switching signal; an error detection circuit to detect an error in a phase relationship between the output clock of the first group and the output clock of the second group; and a re-reset circuit to output the switching signal to the selector based on the error.

Abstract: To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by subtracting (S?N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency division circuit generates a control signal used to preferentially subtract a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among S clock pulses of the input clock signal. Further, it generates the output clock signal by subtracting a clock pulse of the input clock signal according to the generated control signal.

Abstract: An apparatus includes an injection locking frequency divider, which includes a first resonant tank that has a first resonance frequency and a common mode path that includes a second resonant tank, and has a second resonance frequency that is a harmonic of the first resonance frequency. The second resonant tank is adapted to receive a first signal having an oscillation frequency near the harmonic of the first resonance frequency to cause the first resonant tank to provide a second signal that is locked to the first signal.

Abstract: A low-voltage high-speed frequency divider substantially reduces the power required to generate a half-rate in-phase clock signal and a half-rate quadrature-phase clock signal by reducing the number of pairs of transistors that respond to a full-rate clock signal and a full-rate inverse clock signal.

Abstract: Programmable divider circuitry is disclosed that utilizes two cascaded divider cells to generate division ratios from 4 to 7 and utilizes an output signal from one of the divider cells to sample and synchronize the divider output signal. The operation of the programmable divider circuitry improves the consistency of duty cycles generated across the different division ratios. Further techniques are also applied to make more consistent the duty cycles depending upon the division ratio selected.

Abstract: The present invention discloses a method and apparatus for clock frequency division, the method comprises: determining a current frequency division coefficient in real time according to input clock signals and output clock information; then, performing counting on the input clock signals according to an integer portion and a decimal portion of the frequency division coefficient and a decimal scale threshold of the decimal portion; and performing accumulation on the decimal portion according to the counting result; finally, controlling the output clock according to the counting result and the accumulation result. With the method and the apparatus, output signals can be adjusted dynamically according to input signals, and the bit width of the integer portion and the decimal portion of the frequency division coefficient and the decimal scale threshold of the decimal portion can be increased on demand, so that the precision of the frequency division coefficient can be adjusted.

Abstract: A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circuit supplies a feedback signal onto the first dynamic-flop of the chain. In a first mode, a signal from a slave stage of the first flip-flop and a signal from a slave stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. In a second mode, a signal from a master stage of the first flip-flop and a signal from a master stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. By proper selection of the mode, the frequency range of the overall divider is extended. Combinatorial logic converts thirty-three percent duty cycle signals from the flip-flop chain into fifty percent duty cycle quadrature signals.

Abstract: A clock generator is illustrated. The clock generator mentioned above includes a multimodulus frequency divider and a delta-sigma modulator. The multimodulus frequency divider is archived by switching the phase thereof. The multimodulus frequency divider increases the operating frequency of the clock generator effectively, and has a characteristic with half period resolution for reducing the jitter of an output clock signal when its spectrum is spread. Besides, the delta-sigma modulator increases the accuracy of the triangle modulation and reduces error of quantization by adding a few components therein. Thus, the clock generator could be expanded to a programmable clock generator.

Abstract: A clock frequency divider circuit in accordance with the present invention is capable of generating a clock signal that makes it possible to perform an expected proper communication operation in communication with a circuit operating by a clock having a different frequency, and includes a mask control circuit 20 and a mask circuit 10. The mask control circuit 20 includes a mask timing signal generation circuit 22 that generates a mask timing signal 29 used to preferentially mask a clock pulse at a timing other than communication timings among M clock pulses of the input clock signal based on a communication timing signal 26, and a mask restraint circuit 62 that carries out a process to restrain masking of a clock pulse at a communication timing. The mask circuit 10 generates an output clock signal by masking clock pulses of an input clock signal according to a mask signal 50 generated by the mask control circuit.

Abstract: A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clocked switches inside the frequency divider are operated to select one of multiple dividing ratios. An output signal is output with a second frequency that is the first frequency divided by the selected dividing ratio.

Abstract: A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle.

Abstract: Various apparatuses, methods and systems for frequency dividing a clock signal are disclosed herein. For example, some embodiments of the present invention provide an apparatus including a plurality of multiplexers connected in series with the clock signal, each having a plurality of inputs of different phase delays. The apparatus also includes a delta sigma modulator connected to control inputs on the plurality of multiplexers. The delta sigma modulator is adapted to repeatedly select different ones of the pluralities of inputs of different phase delays in the plurality of multiplexers to change a divide ratio between the clock signal and an output of the plurality of multiplexers. The apparatus also includes a multiplexer usage accumulator connected to the delta sigma modulator to track usage of the plurality of multiplexers.

Abstract: A low power frequency divider and a low power phase locked loop, which consume the least power. The low power frequency divider generates a frequency dividing signal by dividing a frequency of an input signal in a uniform ratio, and includes a phase to voltage converter, a comparator, a phase synchronization circuit, and a reset circuit. The phase to voltage converter generates a phase voltage signal corresponding to phase change of the input signal in response to a reset signal. The comparator generates a comparator signal by comparing the phase voltage signal and a reference phase voltage signal. The phase synchronization circuit generates the frequency dividing signal by matching phases of the input signal and the comparator signal. The reset circuit generates the reset signal in response to the comparator signal or the frequency dividing signal.

Abstract: A method and apparatus for dividing clock frequencies are disclosed. For example, a circuit according to one embodiment of includes a high-speed divider and a plurality of programmable dividers cascading with the high-speed divider, wherein the plurality of programmable dividers are of a lower speed than the high-speed divider.

Abstract: Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate.

Abstract: A frequency divider having a plurality of programmable latches connected in a feedback shift register configuration. A programmable latch of said plurality of latches comprises a program input to receive a program signal configured to select a polarity of the programmable latch among two opposite polarities. The frequency divider having a configuration module structured to provide at least the program signal to the program input to modify a divisor parameter of the frequency divider.

Abstract: Example embodiments are directed toward configuration of a phase lock loop (PLL) circuits for low power operation. In particular embodiments, a fraction related to a desired gain of a PLL circuit is determined. A set of possible frequency-divider values and a set of possible feedback divider values are determined. A PLL configuration is selected from a combination of the sets of frequency divider and feedback divider values that forms a ratio indicated the determined fraction.

Abstract: A clock divider and method of operating the same. In various embodiments, the clock divider may be configured to divide clock frequencies by both even and odd divisors. The divisor may be an integer that is represented by an N-bit value, and the clock divider may be programmable by writing the N-bit value to a register. The divisor may be even or odd. During operation, the clock divider may decrement a counter down from an initial value (derived from the N-bit value representing the divisor) to a trigger value. When the trigger value is detected, the clock divider may cause the output clock to toggle. The trigger value may depend on whether the divisor is even or odd. The clock divider may be re-programmed during operation by writing a new N-bit value into the register. Re-programming may include changing the divisor from an even value to an odd value.

Abstract: A latch module comprising a sense pair of transistor elements coupled together for sensing a differential input signal at input terminals, a level-shift module for producing a differential output signal at output terminals, and a regenerative pair of transistor elements coupled together and with the input pair for holding the output signal through the level-shift module. The latch module also includes a pair of gate transistor elements connected in series respectively with the sense pair of transistor elements and with the regenerative pair of transistor elements and responsive to an alternating differential gate signal to activate alternately the sense pair during sense periods and the regenerative pair during store periods. A current injector provides asymmetric operation by injecting current between at least one of the gate transistors and the corresponding sense or regenerative pair of transistor elements so that the sense periods are of different duration from the store periods.

Abstract: A frequency dividing circuit performs a frequency dividing operation on N input clock signals to obtain N output clock signals, wherein N is a natural number greater than 1. The frequency dividing circuit includes a frequency divider and a flip-flop. The frequency divider samples an initial signal according to a first input clock signal of the N input clock signals to accordingly generate a first output clock signal of the N output clock signals. The initial signal corresponds with an inverse signal of the first output clock signal. The flip-flop samples the first output clock signal to accordingly generate a second output clock signal of the N output clock signals according to a second input clock signal of the N input clock signals.

Abstract: A prescaler circuit according to an exemplary aspect of the present invention includes a first flip-flop circuit that detects second output data and outputs the detected data as first output data, and a second flip-flop circuit that detects the first output data and outputs the data as the second output data. The first flip-flop circuit includes a master-side latch circuit that generates intermediate data, a slave-side latch circuit that detects the intermediate data and outputs the data as the first output data, and a control signal switching circuit that selects and outputs the first output data as a control signal in a mode where the frequency is divided by 3, and selects and outputs a predefined fixed signal as a control signal in a mode where the frequency is divided by 4. The master-side latch circuit generates the intermediate data based on the second output data and the control signal.

Abstract: A signal source device is provided and includes a plurality of latch units, an inverter unit, and a voltage-shifting unit, which may include a capacitance unit. The plurality of latch units are substantially cascaded. The inverter unit is coupled to the latch units. The voltage-shifting unit has a first terminal coupled to the inverter unit and one of the latch units and a second terminal receiving a first input signal, for shifting a voltage level at the first terminal according to the first input signal.

Abstract: Frequency division methods and circuits are provided for producing an output clock signal with a frequency related to the frequency of an input clock signal by a predetermined factor. The method and circuit rely on the input clock signal and on feedback from the output signal to produce an intermediate signal. The frequency of the intermediate signal is divided to produce the output clock signal. The method and circuit may be implemented using few circuit components. In an exemplary embodiment, the method and circuit may be used to produce an output clock signal with a frequency that is two-and-a-half times lower than the frequency of the input clock signal.

Abstract: A 3D-IC detector for each layer of a stacked device comprises a pulse generator to receive an initial signal and generate a pulse-in signal to a next stage detector. A latch is coupled to the pulse generator to receive an output signal from the pulse generator and generate a layer identifying signal. A counter is coupled to previous stage detector and the initial signal to perform a counting operation; and an adder coupled to the counter to add a number to a counting output from the counter and input added signal to the pulse generator.

Abstract: To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and M are integers, includes an output clock selecting circuit (200) that selects one of three situations: an input clock signal is outputted as it is, the input clock signal is inverted and outputted and the input clock signal is not outputted; and a clock selection control circuit (100) that generates a control signal for controlling the foregoing selection of the output clock selecting circuit. The clock selection control circuit controls the foregoing selection of the output clock selecting circuit at every cycle of the input clock signal.

Abstract: In accordance with the present disclosure, a multi-modulus divider (MMD) circuit configured for operation at high frequencies may include a cascade of multiple divide-by-2-or-3 cells that divides an input clock signal to produce a pulse signal. The MMD circuit may also include a pulse stretching circuit that extends the duration of the pulse signal, thereby outputting an output clock signal. The cascade of divide-by-2-or-3 cells and the pulse stretching circuit may be implemented using full-swing complementary metal-oxide-semiconductor (CMOS) circuits. Each divide-by-2-or-3 cell may be organized so that a critical path of the divide-by-2-or-3 cell comprises a first dynamic flip flop, a second dynamic flip flop, and no more than two logic stages between the first dynamic flip flop and the second dynamic flip flop.

Abstract: Embodiments described herein are related to a counter. In some embodiments, the counter can be used as a divider, e.g., in a fractional PLL. In some embodiments, the counter (e.g., the main counter or counter C) includes a first counter (e.g., counter C1) and a second counter (e.g., counter C2), which, together with the first counter C1, perform the counting function for counter C. For example, if counter C is to count to the value N, then counter C1 counts, e.g., to N1, and counter C2 counts to N2 where N=N1+N2. For counter C1 to count to N1, N1 is loaded to counter C1. Similarly, for counter C2 to count to N2, N2 is loaded to counter C2. While counter C1 counts (e.g., to N1), N2 can be loaded to counter C2. After counter C1 finishes counting to N1, N2, if loaded, is available for counter C2 to start counting to this N2. Counters C1 and C2 can alternately count and thus provide continuous counting for counter C. Other embodiments and exemplary applications are also disclosed.

Abstract: A one-shot circuit capable of being integrated into a chip generates a frequency-dividing signal according to a reference clock signal of a clock signal generator by means of a frequency-dividing circuit. In this way, the order of the magnitude of the cycle length of the frequency-dividing signal can be raised up by increasing the frequency-dividing times in the frequency-dividing circuit, so that the resistance and the capacitance of an RC oscillator of the clock signal generator are effectively reduced. Therefore, the circuited area occupied by the RC oscillator of the clock signal generator is reduced, so that the one shot circuit can be integrated into a chip without increasing the cost.

Abstract: Aspects of a method and system for use of true single phase clock (TSPC) logic for a high-speed multi-modulus divider in a phase locked loop (PLL) are provided. A fractional-N PLL synthesizer may comprise a divider that generates a divider signal from a VCO output reference signal. The divider may comprise at least one divider stage that utilizes true single phase clock (TSCP) logic D flip-flops. The first divider stage may operate at substantially the same frequency as that of the VCO signal. The divider may also re-synchronize the VCO signal and the divider signal by using at least two re-synchronization stages that utilize a TSCP logic D flip-flop and a stage for adjusting duty-duty cycle of the divider signal. The TSCP logic D flip-flops circuitry may be integrated with a two-input NAND gate or a three-input NAND gate to speed up the operation of the divider.

Abstract: A frequency divider includes a first frequency divider stage coupled to a clock signal and operative to generate a first frequency divided signal. A second frequency divider stage is coupled to the clock signal and to the first frequency divider stage and is operative to generate a second frequency divided signal. A third frequency divider stage is coupled to the clock signal and to the second frequency divider stage and is configured to generate a third frequency divided signal using only i) the clock signal and ii) the second frequency divided signal so that any transition of the third frequency divided signal occurs at an edge of the clock signal at which the second frequency divided signal does not transition.