Abstract: A charge coupled device includes a second conductivity type first horizontal channel in a first conductivity type semiconductor substrate, a second conductivity type second horizontal channel in the substrate at a predetermined distance from the first horizontal channel, and a second conductivity type transfer channel connecting the first horizontal channel with the second horizontal channel to enable transfer of charges from the first horizontal channel to the second horizontal channel. The pinning potential of the transfer channel is larger in absolute value than the pinning potential of the first and second horizontal channels, and the gate voltage pinning the transfer channel is smaller in absolute value than the gate voltage pinning the first and second horizontal channels.

Abstract: An input structure of CCD comprises a primary register having an input gate and a source region and an automatic biasing system which generates a feedback signal to be fed back to input of the primary register. The output of the automatic biasing system is connected to one of the input gate and the source of the primary register for supplying the feedback signal thereto for adjusting input bias level of the primary register. The other one of the input gate and the source is connected to an information signal input terminal to receive therefrom an information signal to be transferred therethrough.

Abstract: The very accurate quantization of charge transport or electron current is achieved within a heterostructure substrate by defining a quantum wire within the substrate and propagating a a.c. potential characterized by a travelling wave envelope along the length of the quantum wire. The travelling wave a.c. potential is applied to the length of the quantum wire by two opposing lateral gate arrays defined within the substrate. For each gate on the array is provided a corresponding gate on the opposing array which is offset in the direction of the current transport by a predetermined distance. A succeeding space is then provided in both arrays where there is no gate. An offset a.c. potential is then applied to the gate of one array, the offset gate of the opposing array and to the array as a whole through an overlying gate running the longitudinal length of the quantum, wire which gate applies a spatially independent a.c. potential along the length of the quantum wire.

Abstract: An input bias circuit employs a gate input type CCD register and an inversion-type amplifier. An output node of the inversion-type amplifier is connected to the input gate electrode of the CCD register, and an input signal to be biased is supplied to the input gate electrode. An output node of the inversion-type amplifier is connected to the floating diffusion region of the CCD register, and a signal charge is picked up from the floating diffusion region. A comparator performs comparison among the low level of the injection pulse supplied to the input diffusion region (which serves as an input diode), the potential level of the input signal supplied to the input gate electrode of the CCD register, and the level of the low-level generated by a low-level signal generating means. On the basis of this comparison, the potential level of the input signal of the CCD register is controlled such that it is higher than the low level of the injection pulse.

Abstract: A charge-coupled device includes a semiconductor body (3) having a semiconductor layer (3) of a first conductivity type adjoining a surface and means for depleting the semiconductor layer throughout its thickness while avoiding breakdown. A sequence (row) of transport electrodes are provided on the surface above the semiconductor layer and are separated by a blocking (isolating) layer from the semiconductor layer and are connected to a clock voltage source to form in the semiconductor layer mutually separated potential wells for storing and transporting information-carrying charge packets. An input stage (I) has a supply zone for supplying majority charge carriers and an input electrode. The input electrode is located between the supply zone and the transport electrodes and is separated by the isolating layer from the semiconductor surface.

Abstract: A solid-state imaging device includes on a semiconductor substrate of a first conductivity type, a well of the opposite conductivity type and, in addition, a plurality of light-sensitive elements formed in the well. A reverse bias voltage applied to the semiconductor substrate with respect to the well causes charge stored in the light-sensitive elements less than or equal to a potential barrier voltage to leak out into the semiconductor substrate. On the substrate a detection circuit detects the resistance of the semiconductor substrate and a setting circuit sets the reverse bias voltage in such a manner as to keep the potential barrier voltage constant, based on the resistance detected by the detection circuit.

Abstract: A charge-coupled device (CCD) delay line having a temperature compensation circuit capable of compensating for temperature variations for providing an accurate and consistent delay of an input signal. The temperature compensation circuit includes first and second registers for transferring charges, and a sample-and-hold circuit connected between outputs of each register and two inputs of a differential amplifier. The differential amplifier supplies a signal which corresponds to temperature variations to properly bias the input signal.

Abstract: A device for operating a charge transfer device includes a driver for operating the charge transfer device and a power supply circuit which generates a voltage in accordance with a state in which the charge transfer device is operated. The power supply circuit includes a power supply unit and an auxiliary power supply circuit. The power supply unit generates one voltage which is supplied to the driver and another voltage, which is changed by the auxiliary power supply circuit, to an appropriate voltage to be supplied to the driver. The volume supplied by the auxiliary power supply circuit is changed from a value thereof supplied during a low speed operation of the charge transfer device, when the charge transfer device is operated at a high speed, or immediately after the charge transfer device is operated at a high speed.

Abstract: A charge transfer device and its driving method are disclosed such that transfer pulses each having an ampitude substantially equal to that of transfer pulses applied to transfer electrodes at transfer stages before a plurality of successively-arranged transfer stages including a final transfer stage and DC offset levels so decreased gradually as to gradually make shallow the depth of potential wells formed under the transfer electrode toward the final transfer stage are applied to transfer electrode at successively-arranged plural transfer stages including the final stage.

Abstract: An input structure of CCD comprises a primary register having an input gate and a source region and an automatic biasing system which generates a feedback signal to be fed back to input of the primary register. The output of the automatic biasing system is connected to one of the input gate and the source of the primary register for supplying the feedback signal thereto for adjusting input bias level of the primary register. The other one of the input gate and the source is connected to an information signal input terminal to receive therefrom an information signal to be transferred therethrough.

Abstract: The invention concerns a device for reading quantities of electrical charge supplied by photodiodes. These photodiodes (1) are arranged at the intersections of rows and columns (4,5) of a matrix (area) array. The device consists of means (6) for storing charges coming from a row of column of the array during scanning, a shift register (10) having an input stage and n-1 intermediate stages, means (18, 20) for injecting bias charges into the receiving potential wells, and skimming type transfer means (19) for transferring the stored charges and bias charges towards the shift register. The readout during scanning of the charges form a row or column of photodiodes is obtained after n charge transfers and n-1 shift operations. With known devices, n readouts are carried out per row or column, making them very slow and/or inefficient with large or high-signal photodiodes.

Abstract: A charge-coupled imager includes in a substrate of a semiconductor material a plurality of spaced photodetectors arranged in a line. The photodetectors are each of a type that can be completely depleted. A suitable photodetector is a pinned photodiode. A separate accumulation region is contiguous with one side of each of the photodetectors. A potential is applied to each accumulation region which forms an accumulation well therein which is lower than that in its respective photodiode so that charge carriers generated in the photodiode will continuously flow into the accumulation region. An anti-blooming drain is provided adjacent each accumulation region with the potential barrier between the anti-blooming drain and the accumulation region being below the potential well in the photodiode so that when the accumulation region fills with charge carriers to the level of the potential barrier any additional charge carriers will overflow into the anti-blooming drain.

Abstract: A solid-state image sensor comprises photoelectric converting devices (22) formed on a p type semiconductor substrate (1), transfer gates (26) for reading signal charges therefrom, scanning lines (21) for selecting the transfer gates (26), and transfer electrodes (11) of the first layer and transfer electrodes (12) of the second layer alternately disposed for transferring in the vertical direction the read signal charges. All the electrodes of the transfer gates (26) are formed integrally with the transfer electrodes (12) of the second layer, with the result that all the electrodes of the transfer gates (26) are common to the transfer electrodes of the same layer (the second layer). Although the potential wall (340) is formed in the transfer channel (3) beneath the transfer electrode (12) connected to the transfer gate (26), the same is insulated from adjacent the transfer electrode (11) on the charge transfer direction side.

Abstract: In a charge transfer device including spaced apart channels on a semiconductor substrate, first electrodes are disposed in gaps between the channels, second electrodes are disposed opposite alternate channels overlapping the adjacent first electrodes, and a third continuous electrode overlies the alternating channels and first and second electrodes in the charge transfer direction. A first clock phase is obtained by connecting alternate first electrodes with the adjacent second electrode in the direction of charge transfer, and a second clock phase is obtained by connecting the remaining first electrodes with the third electrode. The portion of the first electrode overlapped by the second electrode in the second clock phase is larger than that in the first clock phase for stable driving by first and second clock signals out of phase by 180.degree. and generated by a driver including a resonance circuit.

Abstract: A first charge storage electrode (21) has a first row (21b) of teeth interdigitated with a second row (22b) of teeth of a second charge storage electrode (22). The second storage electrode (22) has a third row (22c) of teeth interdigitated with a fourth row (23b) of teeth of a third charge storage electrode (23). The first and third rows (21b and 22c) overlie one group (11b) of a series of parallel conduction channels while the second and fourth rows (22b and 23b) overlie another group (11a) of the parallel channels. A first charge transfer electrode (24) is provided to transfer charge packets into sites beneath the first storage electrode.

Abstract: A uniphase, buried-channel, semiconductor charge transfer device wherein a portion of each cell includes an inversion layer, or "virtual electrode" at the semiconductor surface, shielding that region from any gate-induced change in potential. Each cell is comprised of four regions (I, II, III, IV) wherein the characteristic impurity profile of each region determines the maximum potential generated therein for the gate "on" and gate "off" conditions. Clocking the gate causes the potential maxima in regions I and II to cycle above and below the fixed potential maxima in regions III and IV beneath the virtual electrode. Directionality of charge transfer is thereby achieved, since the potential maximum for region II (.phi..sub.max II) remains greater than for region I (.phi..sub.max I) and .phi..sub.max IV>.phi..sub.max III, for both gate conditions.

Abstract: A charge coupled device includes a plurality of first CCD shift-registers transferring charge signals in parallel and a second CCD shift-register receiving the charge signals from the first CCD shift-registers for a parallel-serial coversion, the second CCD shift-register being connected to the first CCD shift-registers through barrier regions covered with electrodes in the second CCD shift-register.

Abstract: In dynamic memories, generally a fluctuation of 10% of the nominal value of the supply voltage is allowed. Since, when reading, the input gate is applied to the supply, this fluctuation in the supply results in 20% of fluctuation in the charge packet formed below the input gate. In order to eliminate this fluctuation and hence to increase the permitted interference margin for other interference sources, a voltage stabilization circuit is arranged between the supply voltage and the input gate so that the fluctuation in the supply also occurs at the source zone, as a result of which the size of the charge packet becomes independent of the supply. For the voltage stabilization circuit, use may advantageously be made of a band gap reference.

Abstract: There is disclosed an output circuit of a charge transfer device including an output section of the charge transfer device which has a floating diffusion region receiving charges transferred through the charge transfer section to detect the quantity of the charges, an output holding section which holds the DC level of the voltage outputted from the output section, a comparing section which compares the DC level held by the output holding section with a reference voltage Vref, and means for applying the output of the comparing section to the floating diffusion region to reset charges in the floating diffusion region.

Abstract: A serial-to-parallel analog CCD GaAs device provides high speed A/D or D/A conversion. A high speed analog signal is sampled by shifting the analog data serially into "n" CCD elements. Then a parallel load pulse transfers the analog data into multiple CCD holding elements. A bank of A/D converters converts the analog data. Conversely, the outputs of a bank of D/A converters are loaded in parallel into a serial CCD device of the "n" elements. The serial CCD device is shifted out serially to complete the conversion to an analog signal.

Abstract: A serial-parallel-serial, charged-coupled device includes an array of horizontal rows and columns of closely spaced charge storage cells. Each storage cell is formed by an electrode covering an insulation layer above a semiconductor substrate. The semiconductor substrate of each storage cell includes a channel region for conducting carriers laterally through the storage cell. The channel region of each storage cell included both in a first row of the array and in any column of the array has a tilted potential gradient providing an electric field facilitating charge carrier drift within the channel region in two lateral directions, toward a neighboring storage cell of the first row and also toward a neighboring storage cell of its column.

Abstract: A step-up circuit is comprised of plurality of charge pumping circuits connected in parallel to an output line. Each charge pumping circuit is activated by a pair of mutually opposite clock signals to produce a higher output voltage than its power source voltage. The clock signals applied to the charge pumping circuits are out of phase with respect to one another such that a stable output of higher voltage can be obtained.

Abstract: The semiconductor devices include a semiconductor substrate, a first CCD region formed at the surface of said substrate, and a second CCD region having a side connected to said first CCD. A channel region of the first CCD region has a different channel potential at a latter part of the end transfer electrode corresponding to the portion of the first CCD region connected to the second CCD region.

Abstract: A charge transfer device, suitable for use, for example, in a solid state imager device, having a floating gate electrode in a charge detecting section, a protruding portion provided in at least one of the floating gate electrodes or a gate electrode arranged adjacent to the floating gate electrode, wherein the floating gate electrode and the gate electrode arranged adjacent to the floating gate electrode overlap each other at the protruding portion within an insulating layer, and whereby the parasitic capacitance associated with the floating gate electrode is decreased and the charge voltage converting gain is increased, rendering it possible to obtain an image signal with a good signal/noise ratio, when the charge transfer device is used for a solid state imager device.

Abstract: A charge-coupled device for detecting spatial variation in the intensity of electromagnetic radiation comprises a body of semiconductor material that responds to electromagnetic radiation in a given spectral region by generating charge carriers. The body of semiconductor material has first and second sense volumes that are isolated from each other with respect to diffusion of charge carriers. A sense electrode structure overlies the sense volumes. First and second transfer regions are in communication with the first and second sense volumes respectively, and a transfer electrode structure overlies the transfer regions. A readout region has first and second zones in communication with the first and second transfer regions respectively and is connected to an output node. Charge can be accumulated in the sense volumes over an integration period and the resulting charge samples can be shifted separately through the transfer regions and applied to the output node.

Abstract: A serial-to-parallel analog CCD GaAs device provides high speed A/D or D/A conversion. A high speed analog signal is sampled by shifting the analog data serially into "n" CCD elements. Then a parallel load pulse transfers the analog data into multiple CCD holding elements. A bank of A/D converters converts the analog data. Conversely, the outputs of a bank of D/A converters are loaded in parallel into a serial CCD device of "n" elements. The serial CCD device is shifted out serially to complete the conversion to an analog signal.

Abstract: A charge-coupled device comprising two clock electrodes (4,5) on the two opposite sides of the charge transport channel (3) and which extend the entire length of the channel. Charge storage regions (6-9) are located zigzagwise on both sides of the channel, as a result of which during charge transport the charge is transferred from one side to the other. Due to the separation of the electrodes the parasitic capacitance between them is low, achieving low power dissipation. The electrodes are located in grooves at the sides of the channel, leaving the surface of the channel unobstructed. The device can therefore serve as an image sensor of high sensitivity.

Abstract: A charge transfer device (CTD) eliminating the background level of a detected signal provided with an input circuit comprising an injection source (12) and an electrode (16) controlling a storage potential well, which can be subdivided into an evacuation well (18) and an output well (19) separated by the separation potential produced by a separation electrode (27). This CTD is characterized in that its input circuit comprises a floating electrode (25) connected to the separation electrode (27) in order that the separation potential controls the background level and an insulation electrode (28) insulating the reference well (29) from the output well (19), during the measuring operations, the respective dopings under the floating electrode and under the separation electrode being obtained in order that the potential wells situated under each of these respective electrodes have different depths.

Abstract: A correlator, such as may be used in a phase detecting device of an automatic focusing circuit for a camera , has a simple arrangement that attains improved accuracy and high speed. A pair of charge storing elements is provided to which input signals are applied. When predetermined charges are supplied into potential wells formed in the charge storing elements, charge remaining in the potential wells depending on their depth can be detected as the absolute value of the difference between the two input signals. Therefore, the input signals can be subjected to correlation directly as they are, that is, in analog form, without conversion to digital form.

Abstract: A low 1/f noise amplifier has been provided for an output of a CCD imager. To reduce clock noise, the amplifier employs a differential detection scheme. Linear stages (54, 76) are coupled by capacitors (60, 82) to a differential amplifier (64). Differential amplifier (64) employs a first (112, 118) and a second (172, 198) differential transistor pair. The second differential pair (172, 198) is cross-coupled to the outputs of the first differential pair (112, 118) by load resistances (180, 206) with the voltage drop across them remaining substantially constant. To maintain stability, the positive and negative branches of the amplifier are periodically reset by a resetter (210). The input nodes (62, 86) are periodically reset to a voltage reference.

Abstract: An output circuit of a charge coupled device comprises a transistor (4, 5, 6) having a floating diffusion (5) provided to receive a series of signal charges from a charge transfer section. Each signal charge is transferred to the floating diffusion in synchronism with a drive clock applied to the charge transfer section. The transistor has a gate electrode (4) connected to receive a reset clock (.phi.R') applied at an interval longer than the period of the drive clock.

Abstract: A various CCD delay element in which extra delay stages are provided. The extra stages are either held at a given potential to pass all signals therethrough and thus to not contribute to the gain or are connected to the clock signals to thereby increase the delay.

Abstract: This device comprises transfer electrodes and read electrodes. The read electrode operates in accordance with two modes. Where it operates based on the charge detection mode, a charge below the read electrode is read out in accordance with the floating gate system, so that a charge detection signal is produced. On the other hand, where it operates based on the charge transfer mode, the read electrode performs a function equivalent to the transfer electrode. This device further comprises selector means, thus permitting the read electrode to select either of two modes to operate in a selected mode.

Abstract: In an SPS charge transfer device comprising a parallel register having a plurality of signal transfer channels for transferring signal charges, and a first and a second serial registers, a plurality of noise transfer channels for transferring noise charges due to a dark current are formed adjacent to and parallel with the signal transfer channels. The signal charges are transferred through the signal transfer channels toward the second serial register, and then through the second serial register, while the noise charges are transferred through the noise transfer channels toward the first serial register, and then through the first serial register. The signal charges at the output end of the second serial register and the noise charges at the output end of the first serial register are used to produce signals representing the signal charges which are originally introduced into the parallel register, i.e., the signal charges from which the noise components due to the dark current have been removed.

Abstract: Charge accumulation read-out device of photosensitive detectors comprising a charge transfer shift register which receives the information from N detectors disposed in the same line. This register has the same storage area over the whole of its length and conveys the information collected at different times from these detectors without mixing it, means provide simultaneously several read-outs of the charges stored by certain given stages of the register, which ensures in phase summation of the information. The invention concerns the application of TDI read-out to photosensitive detector matrices.

Abstract: A charge packet differencer is implemented in a charge coupled device in such a manner that a first charge packet may be subtracted from a second charge packet thus giving a resultant charge packet equal to the difference between the first and second charge packets. The charge coupled device differencer comprises a semiconductor substrate in which there is formed first and second charge transfer devices, first and second charge substraction mechanisms, and a charge reservoir cooperating to produce a charge packet output representative of the difference between two input charge packets using a gate charge subtraction technique.

Abstract: In a CCD, especially in an image sensor device, the information density can be doubled by sequentially switching the electrodes between a clock signal and a reference signal. Clock signals and reference signals are obtained as output signals of a shift register controlled by a monophase or multiphase clock. The register is provided, for example, using C-MOS technology. Information at the input terminal of the first stage of the shift register in combination with clock pulse signals at the register clock, determine the output signals of the next stage of the shift register. Hence, these input signals determine the voltage variations at the electrodes connected to the outputs of the register stages.

Abstract: A dynamic closed-loop circulating analog memory, preferably embodied with monolithic charge coupled devices and employing a minimum number of serial data transfers, additive refresh signal processing, and dark current subtraction for limiting crosstalk degradation of the circulated signals.

Abstract: Thin electrodes are coupled to a resistive film on an active semiconductive layer to form a gapless gate CCD (GGCCD). The active layer is formed ona semi-insulating substrate, and the resistive film is joined to the active layer by a Schottky barrier. The thin electrode coupled to the resistive film induce fringing fields near the surface to provide high speed charge transport and permit the use of a thin active layer.

Abstract: A digital memory comprises a charge coupled device (CCD) that includes a reference signal storage section. The digital input to the CCD includes an input reference signal and an information signal having a plurality of data levels, for example, a digital "0" and "1". The input reference signal includes a reference bit at the higher data level. The reference signal storage section divides the level of the reference bit to provide a reference level signal halfway between the two data levels. Thus, any shift in the data levels due, for example, to temperature changes in the CCD, affects the reference level signal to the same degree and the reference level can be kept exactly halfway between the data levels.

Abstract: Charge transfer device output signals typically include an information component which is contaminated with both on-chip amplifier noise and reset noise. For reducing these noise components, the device output signal is applied to first and second synchronous detectors. The first synchronous detector is responsive to a first reference carrier signal for maximizing at its output the information component while the second synchronous detector is responsive to a second reference carrier for maximizing at its output the noise components. The synchronous detector output signals are then differentially combined so as to substantially reduce the noise components from the contaminated information component.

Abstract: A charge coupled device (CCD) amplifier is utilized for amplification of charge packets as small as 500 electrons into usable signals. Very little noise is injected into the signal. The charge amplifier consists of two connecting electrodes, one designated as the detector G.sub.1 and the other designated as the response G.sub.2, physically separated by any convenient distance on the same LSI chip surface on which an NMOS field effect transistor (FET) is attached. Also coupled to the FET is another electrode G.sub.3 designated as the amplifier gate. The charge amplifier structure is embedded in the silicon dioxide layer, with the detector response, and amplifier electrode being located some convenient distance above the silicon-silicon dioxide interface.

Abstract: The present invention relates to a charge transfer device for multiplexing signals and eliminates an output circuit and level adjusting circuit necessary for multiplexing signals in the prior art. There are provided at least two first and second transfer channels (34) and (35) for transferring signal charges and a third transfer channel (36) for alternately multiplexing the signal charges which are transferred within the transfer channels (34) and (35). To the first and second transfer channels (34) and (35) is supplied the same transfer clock signal and to the third transfer channel is supplied a second transfer clock signal with a frequency of which is n times the transfer channels before the signals are multiplexed. a multiphase clock with different phases of the clock being applied to spatially corresponding electrodes is used in the invention.

Abstract: A bias voltage setting circuit for a main charge coupled device is disclosed in which first and second auxiliary charge coupled devices are formed on a semiconductor substrate together with the main charge coupled device, a reference voltage is generated by the first auxiliary charge coupled device, the output voltage of the second auxiliary charge coupled device is compared with the reference voltage by means of a comparator, the bias voltage applied to the second auxiliary charge coupled device is automatically changed by a feedback circuit so that the output voltage of the second auxiliary charge coupled device is approximately equal to the reference voltage, and the bias voltage applied to the second auxiliary charge coupled device is also used as the bias voltage applied to the main charge coupled device.

Abstract: An apparatus having a charge coupled device which is used as a solid state type image pickup apparatus and prior to inversion of the level of drive pulses supplied to two electrode groups from among a plurality of electrode groups of a CCD, each electrode group is disconnected once electrically from each drive pulse generating circuit, in which period two electrode groups whose level of drive pulse are inverted are electrically short-circuited, whereby all the charges in capacitors formed between the electrodes and a substrate are not discharged but about half of the charges can be reused for charging another capacitor which is formed between the electrodes and the substrate and is to be charged next, thus enabling a saving of power consumption, a reduction of heat dissipation losses, and enabling the miniaturization of the image pickup apparatus using a charge coupled device.

Abstract: A charge transfer device has one or more charge injection areas each having an input diffusion layer and two or more input gate electrodes. An input signal is applied to the input diffusion layer, a clock voltage is applied to one of the input gates and an input reference voltage is applied to the other input gate to inject a signal charge proportional to a difference between the input reference voltage and the input signal, and the signal charge is sequentially transferred. A magnitude of the input reference voltage is changed in accordance with a magnitude of a maximum value of the input signal so that transfer of charges which do not contribute to signal component is suppressed and a transfer efficiency is improved.

Abstract: Delay for a field time is introduced between the end of the time a field of pixel samples is transferred from the A register into the B register of a field-transfer CCD imager and the beginning of the time the field of pixel samples is transferred from the B register to the C register. Such field delay is useful in differentiating response to a radiant energy image with respect to time, for example. A field of pixel samples is delayed in a first B register sufficiently long to be in time registration with a succeeding field of pixel samples in a second B register and responses to these samples are differentially combined to provide indications of transient phenomena in one field and not the other or in one field for longer time than in the other. The two B registers may be in two CCD imagers receiving images in spatial registration or may be in a CCD imager in which one A register alternately supplies samples to the two B registers.

Abstract: D.C. reconstruction of sampled CCD output signals is achieved by subtracting the output current pulses of two CCDs (or subtracting parallel outputs of the same CCD) with a differencing circuit containing two biasing current mirrors, a current sink device and an output capacitor. The two current mirrors are used with each biasing the output of a complementary CCD to positive and acting to mirror the CCD output current. A third current mirror converts the output of one of the CCDs into a current sink. An output capacitor performs subtracting by converting all outputs to voltage and combining the positive biased output of one CCD with the current said output of the second CCD.

Abstract: A charge coupled device (CCD) with separately addressable input signal gates is operated in the potential equilibrium mode. With properly selected voltage potentials the CCD can be used as a high speed linear detector of a variable analog signal without the need of preceeding independent sample and hold or peak detector circuits. The result is the efficient minimum/maximum detection of an analog signal in a fast-in/slow-out digitizer.

Abstract: Sensor correction circuit for maintaining offset voltages in the shift registers of a multiple channel image sensor substantially equal having a pair of control gates to permit sampling the current offset voltages in the shift registers of each channel, a pair of capacitors for storing the offset voltage samples in each channel; a clock for actuating the control gates in preset timed relation between scan lines to sample and store the current shift register offset voltages on the capacitors; and an amplifier for amplifying any difference between the offset voltage samples held by the capacitors to provide an adjusted potential for balancing any differences between the shift registers.