Abstract: Methods of enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a dielectric. In some embodiments, a metal surface is functionalized to enhance or decrease its reactivity.

Abstract: A silver-coated particle (P1) is provided. The silver-coated particle (P1) includes a core particle (2) made of a resin particle or an inorganic particle and a silver coating layer (1) formed on a surface of the core particle (2), wherein, an amount of silver contained in the silver coating layer (1) is 5 to 90 parts by mass with respect to 100 parts of the silver-coated particle (P1), a crystallite diameter of the silver, which is calculated from a diffraction line obtained by filling a sample holder belonging to an X-ray diffraction apparatus with the silver-coated particle (P1); and irradiating X-ray in a range of 2?/?=30 to 120 deg., is in a range of 35 nm to 200 nm.

Abstract: A pretreatment agent for electroless plating is provided, which includes: a fluorine compound; a surfactant; and at least one solvent selected from ethylene-based glycol butyl ethers of formula: C4H9—(OC2H4)m—OH where m is an integer of 1 to 4, and propylene-based glycol butyl ethers of formula: C4H9—(OC3H6)n—OH where n is an integer of 1 to 4. Also provided are a method for pretreating a substrate to be used for a printed wiring board, and a process for producing a printed wiring board, both of which include using a pretreatment agent for electroless plating as described above.

Abstract: Catalysts include nanoparticles of catalytic metal and gallic acid or gallic acid derivatives or salts thereof. The catalysts are used in electroless metal plating. The catalysts are free of tin.

Abstract: The embodiments fill the need of improving electromigration and reducing stress-induced voids of copper interconnect by enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect. The adhesion between the barrier layer and the copper layer can be improved by making the barrier layer metal-rich prior copper deposition and by limiting the amount of oxygen the barrier layer is exposed prior to copper deposition. Alternatively, a functionalization layer can be deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect with good adhesion between the barrier layer and the copper layer. An exemplary method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in an integrated system in order to improve electromigration performance of the copper interconnect is provided.

Abstract: A method of manufacturing ULSI wiring in which wiring layers are separately formed via a diffusion prevention layer and an insulating interlayer portion made of SiO2. The method comprises the steps of treating, with a silane compound, a SiO2 surface of the insulating interlayer portion on which the diffusion layer is to be formed, performing catalyzation with an aqueous solution containing a palladium compound, forming the diffusion prevention layer by electroless plating, and then forming the wiring layer on this diffusion prevention layer. A capping layer may be formed on the wiring layer by electroless plating. Consequently, a diffusion prevention layer having good adhesive properties can be formed through a simple wet process, and, the wiring layer can directly be formed on this diffusion prevention layer by a wet process. The capping layer can also be directly formed on the wiring layer by electroless plating.

Abstract: The present disclosure describes an article and a method of forming a microstructure. The method includes providing a substrate having a structured surface region comprising one or more recessed features with recessed surfaces. The structured surface region is substantially free of plateaus. The method includes disposing a fluid composition comprising a functional material and a liquid onto the structured surface region. The method includes evaporating liquid from the fluid composition. The functional material collects on the recessed surfaces such that a remainder of the structured surface region is substantially free of the functional material.

Abstract: Stable zero-valent metal compositions and methods of making and using these compositions are provided. Such compositions are useful as catalysts for subsequent metallization of non-conductive substrates, and are particularly useful in the manufacture of electronic devices.

Abstract: Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings.

Abstract: A substrate structure is provided. The substrate structure includes a substrate, a first insulation layer, a conductive part, a second insulation layer, a seed layer and a conductive layer. The substrate has a first circuit pattern layer and a second circuit pattern layer, which are located on two opposite surfaces of the substrate respectively. The first insulation layer formed on the first circuit pattern layer has a first insulation hole, which exposes a first opening in the outer surface of the first insulation layer. The conductive part formed on the first insulation hole for electrically connecting with a chip is enclosed by the edge of the first opening. The second insulation layer formed on the second circuit pattern layer has a second insulation hole in which the seed layer is formed. The conductive layer is formed on the seed layer for electrically connecting with a circuit board.

Abstract: A curable resin with at least one electrically conductive metal region on its surface formed by depositing on the surface a composition comprising activator, contacting the activator with a solution of a reducing agent and a solution of a metal ion, the reducing agent and metal ion undergoing chemical reaction activated by the activator to form an electrically conductive metal region on the surface, and method of forming is provided.

Abstract: The present invention is directed to a method for manufacturing a printed circuit board in which a plurality of conductive layers forming a wiring pattern are laminated in the state where they are put between insulating layers, and a printed circuit board formed thereby. The printed circuit board manufacturing method for the present invention includes a step of forming a via fill (17) to allow electroless plating liquid to be in contact with the surface of the wiring pattern exposed to a bottom part of a via hole (14) formed at a insulating layer to laminate plating metallic film from the bottom part to a opening part of the via hole (14), to form the via fill (17), and a step of forming a wiring pattern to form electroless plating metallic film (20) serving as the wiring pattern onto a substrate where the via fill (17) is formed.

Abstract: The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve metal-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce an improved metal-to-metal interface, more specifically barrier-to-copper interface. An exemplary method of preparing a substrate surface of a substrate to deposit a metallic barrier layer to line a copper interconnect structure of the substrate and to deposit a thin copper seed layer on a surface of the metallic barrier layer in an integrated system to improve electromigration performance of the copper interconnect is provided. The method includes cleaning an exposed surface of a underlying metal to remove surface metal oxide in the integrated system, wherein the underlying metal is part of a underlying interconnect electrically connected to the copper interconnect.

Abstract: The invention provides a method of forming a metallic pattern including: (a) forming, in a pattern form on a substrate, a polymer layer which contains a polymer that has a functional group that interacts with an electroless plating catalyst or a precursor thereof; (b) imparting the electroless plating catalyst or precursor thereof onto the polymer layer; and (c) forming a metallic film in the pattern form by subjecting the substrate having the polymer layer to electroless plating using an electroless plating solution, wherein the substrate is treated using a solution comprising a surface charge modifier or 1×10?10 to 1×10?4 mmol/l of a plating catalyst poison before or during the (c) forming of the metallic film. The invention further provides a metallic pattern obtained thereby. Furthermore, the invention provides a printed wiring board and a TFT wiring board, each of which uses the metallic pattern as a conductive layer.

Abstract: The present invention provides a plated article that has a thin seed layer having a uniform thickness, formed by electroless plating and allowing formation of ultrafine wiring, and that avoids the complicated formation of a bilayer of a barrier layer and a catalytic metal layer prior to forming the seed layer. The present invention also provides a method for manufacturing the plated article. The plated article has an alloy thin film formed on a substrate and containing a catalytically active metal (A) for electroless plating and a metal (B) capable of undergoing displacement plating with a metal ion contained in an electroless plating solution, and a metal thin film formed on the alloy thin film by electroless displacement and reduction plating. The alloy thin film of the catalytically active metal (A) and the metal (B) capable of displacement plating has a composition comprising 5at% to 40at% of the metal (A).

Abstract: A method for reducing porosity of metal layers on a substrate may comprise depositing a precursor onto at least a portion of the substrate, and adding metal layers over the precursor comprising at least one cycle, wherein each cycle comprises: depositing a metal layer over the precursor, and exposing the metal layer to a breath-out solution.

Abstract: An article includes a polymeric film having a major surface, a discontinuous layer of a catalytic material on the major surface, and a metal pattern on the catalytic material. The discontinuous layer of catalytic material has an average thickness of less than 200 angstroms. Methods of forming these articles are also disclosed.

Abstract: Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings.

Abstract: The invention relates to a method for a structured application of molecules on a strip conductor and to a molecular memory matrix. The inventive method makes it possible, for the first time, to economically and simply apply any number of molecular memory elements on the strip conductor in a structured and targeted way, thereby making available, also for the first time, a memory matrix at a molecular level.

Abstract: The invention relates to a process for the metallization of an insulator and/or a dielectric, wherein the insulator is firstly activated, it is subsequently coated with another insulator and the latter is patterned, then the first is seeded and lastly metallized.

Abstract: The process of this invention involves first adsorbing a catalyst on the surface of a specimen by immersion in a catalyst-containing solution, followed by electrolytic deposition in a second solution that need not contain catalyst. This two-step superconformal process produces a seam-free and void-free metal microelectronic conductor.

Abstract: The present methods provide tools for growing conformal metal thin films, including metal nitride, metal carbide and metal nitride carbide thin films. In particular, methods are provided for growing such films from aggressive chemicals. The amount of corrosive chemical compounds, such as hydrogen halides, is reduced during the deposition of transition metal, transition metal carbide, transition metal nitride and transition metal nitride carbide thin films on various surfaces, such as metals and oxides. Getter compounds protect surfaces sensitive to hydrogen halides and ammonium halides, such as aluminum, copper, silicon oxide and the layers being deposited, against corrosion. Nanolaminate structures incorporating metallic thin films, and methods for forming the same, are also disclosed.

Abstract: A method for forming a plated microvia interconnect. An external dielectric layer (EDL) is mounted on a surface of the substrate and is in direct mechanical contact with a conductive element included in the surface. An opening formed in the EDL exposes the conductive element and creates a microvia in the EDL. A sidewall and bottom wall surface of the microvia is treated to promote copper adhesion to the sidewall and bottom wall surfaces. The sidewall and bottom wall surfaces are plated to form a layer of copper thereon. The layer of copper is in direct mechanical and electrical contact with the conductive element. A wet solder paste deposited on the layer of copper overfills a remaining portion of the microvia. The solder paste is reflowed to form a solder bump in and over the remaining portion of the microvia to form the plated microvia interconnect.

Abstract: The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve metal-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce an improved metal-to-metal interface, more specifically barrier-to-copper interface. An exemplary method of preparing a substrate surface of a substrate to deposit a metallic barrier layer to line a copper interconnect structure of the substrate and to deposit a thin copper seed layer on a surface of the metallic barrier layer in an integrated system to improve electromigration performance of the copper interconnect is provided. The method includes cleaning an exposed surface of a underlying metal to remove surface metal oxide in the integrated system, wherein the underlying metal is part of a underlying interconnect electrically connected to the copper interconnect.

Abstract: A dielectric composition which forms a dielectric layer usable in circuitized substrates such as PCBs, chip carriers and the like. As such a layer, it includes a cured resin material and a predetermined percentage by weight of particulate fillers, thus not including continuous fibers, semi-continuous fibers or the like as part thereof.

Abstract: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise an aluminum-containing compound and one or both of silane and silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.

Abstract: A process of providing a pattern of a metal on a non-conductive substrate to create loop antennae for wireless articles and for creating circuitry for smart cards, such as phone cards is provided. The method comprises the steps of catalyzing the non-conductive substrate by applying a catalytic ink, reducing a source of catalytic metal ions in the catalytic ink to its associated metal, depositing electroless metal on the pattern of catalytic ink on the surface of the substrate; and plating electrolytic metal on the electroless metal layer to produce the desired pattern of metal on the non-conductive substrate. The catalytic ink typically comprises one or more solvents, a source of catalytic metal ions, a crosslinking agent, one or more copolymers, a polyurethane polymer, and, optionally, one or more fillers.