Registration Or Layout Process Other Than Color Proofing Patents (Class 430/22)
  • Patent number: 8906584
    Abstract: A semiconductor device includes a cell mask pattern disposed in a cell region of a mask substrate and a vernier mask pattern disposed in a vernier region of the mask substrate. The vernier mask pattern includes a variable mask pattern portion to transfer a different shape of pattern depending on the magnitude of exposure energy.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Byoung Hoon Lee, Chang Moon Lim, Myoung Soo Kim, Jeong Su Park, Jun Taek Park, In Hwan Lee
  • Patent number: 8883380
    Abstract: On a film where an exposure material coating has been formed in a exposure pattern formation region on a film base material, a colored firing material, colored light-curable material, or colored ink is applied to at least one of two widthwise side edges to form a side part application coating, which is irradiated with laser light by an alignment mark formation unit to form an alignment mark. The alignment mark is then used to detect film meandering and adjust the positions of masks. This makes it easy to form the alignment mark and detect the alignment mark thus formed and makes it possible to accurately correct for meandering of a film and stably expose the film in the process of continuous exposure of a film where an exposure material coating has been formed in a exposure pattern formation region on a film base material.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: November 11, 2014
    Assignee: V Technology Co., Ltd.
    Inventors: Toshinari Arai, Kazushige Hashimoto
  • Patent number: 8859167
    Abstract: According to one embodiment, a positional deviation measuring method includes measuring a positional deviation of a device pattern formed in a lower layer portion using an alignment mark of the lower layer portion as a reference; measuring a positional deviation of a device pattern formed in an upper layer portion above the lower layer portion using an alignment mark of the upper layer portion as a reference; measuring a positional deviation between the alignment mark of the lower layer portion and the alignment mark of the upper layer portion; and calculating a positional deviation between the device patterns based on the positional deviation between the alignment marks.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Hagio, Yosuke Okamoto
  • Patent number: 8828632
    Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
  • Patent number: 8803542
    Abstract: A method for verifying stitching accuracy of a stitched chip on a wafer is disclosed. Initially, a set of test structures are inserted within a reticle layout. An exposure program is executed to control a photolithography equipment having a stepper to perform multiple exposures of the reticle on a wafer to generate a stitched chip on the wafer. Electrical measurements are then performed on the test structures at actual stitch boundaries of the stitched chip to evaluate stitching accuracy of the stitched chip.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: August 12, 2014
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Thomas J. McIntyre, Charles N. Alcorn, Matthew A. Gregory
  • Patent number: 8796645
    Abstract: An exposure apparatus for a photoalignment process includes; a first photomask including a plurality of transmission parts; and a second photomask including a plurality of transmission parts, where the first photomask and the second photomask partially overlap each other such that each of the first photomask and the second photomask includes an overlapping region and a non-overlapping region, the overlapping region of at least one of the first photomask and the overlapping region of the second photomask includes at least two subregions, and shapes or arrangements of the transmission parts in the at least two subregions are different from each other.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 5, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Soo-Ryun Cho, Jun Woo Lee, Kyoung Tae Kim, Joo Seok Yeom, Suk Hoon Kang, Eun Ju Kim
  • Patent number: 8790851
    Abstract: A photo mask for exposing according to an embodiment includes a mark pattern arranged in a mark region that is different from an effective region to form a semiconductor device; and a regular pattern arranged in the mark region and around the mark pattern and smaller than the mark pattern in size and pitch.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Okamoto, Kazutaka Ishigo, Taketo Kuriyama
  • Patent number: 8765495
    Abstract: A method of forming a pattern of doped region includes the following steps. At first, a device layout pattern including a gate layout pattern and a doped region layout pattern is provided to a computer system. Subsequently, the device layout pattern is split into a plurality of sub regions, and the sub regions have different pattern densities of the gate layout pattern. Then, at least an optical proximity correction (OPC) calculation is respectively performed on the doped region layout pattern in each of the sub regions to respectively form a corrected sub doped region layout pattern in each of the sub regions. Afterwards, the corrected sub doped region layout patterns are combined to form a corrected doped region layout pattern, and the corrected doped region layout pattern is outputted onto a mask through the computer system.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: July 1, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Hsiu Lee, Guo-Xin Hu, Qiao-Yuan Liu, Yen-Sheng Wang
  • Patent number: 8758964
    Abstract: Disclosed is an LCD panel photolithography process, employed in a lithography system for manufacturing a plurality of LCD panel, comprising steps of: performing photolithography to a glass substrate with a first mask, and the first mask comprises a plurality of sets of alignment marks corresponding to a plurality of following masks thereafter, and a plurality of sets of alignment marks corresponding to the plurality of following masks thereafter are formed on the glass substrate; and employing the plurality of sets of alignment marks on the glass substrate respectively, to perform alignment procedure and photolithography for the plurality of following masks with the plurality of sets of alignment marks on the glass substrate to form patterns; wherein corresponding to the same LCD panel area, the plurality of sets of alignment marks on the glass substrate have different position coordinates respectively.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: June 24, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co. Ltd.
    Inventor: Cai-li Zhang
  • Patent number: 8748065
    Abstract: Reflection type blank masks are provided. The blank mask includes a substrate, a reflection layer substantially on the substrate, at least one fiducial mark substantially on the reflection layer, an absorption layer substantially on the at least one fiducial mark and the reflection layer, and a resist layer substantially on the absorption layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 10, 2014
    Assignee: SK Hynix Inc.
    Inventors: Yong Dae Kim, Byung Ho Nam
  • Patent number: 8741506
    Abstract: The present invention provides a mask and a repairing method therefor. A reference area is selected in a configuration pattern of a mask template, the reference area is corresponding to a to-be-shaded area of a mask; a repair area is formed on a drillable member according to the reference area; a hollow area is formed in the repair area of the drillable member, the hollow area is corresponding to the to-be-shaded area; the drillable member is attached to the mask, the hollow area is corresponding to the to-be-shaded area; and shading material is coated on the drillable member, so as to form a shaded layer on the to-be-shaded layer.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: June 3, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Jiaxing Ma
  • Patent number: 8735051
    Abstract: Exposure apparatus is equipped with an illumination optical device which illuminates a mask with an exposure beam, a mask table which holds a periphery of a pattern area of the mask from above so that a pattern surface of the mask becomes substantially parallel to an XY plane and makes a force at least parallel to an XY plane and on the mask, and a wafer stage which moves along the XY plane, holding a wafer substantially parallel to the XY plane. Therefore, an overlay with high precision of a pattern of a mask and an underlying pattern on the substrate can be realized, even though the exposure apparatus employs a proximity method, that is, the exposure apparatus does not use a projection optical system.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: May 27, 2014
    Assignee: Nikon Corporation
    Inventor: Yuichi Shibazaki
  • Patent number: 8728713
    Abstract: A method for producing a measurement structure for measuring alignment of patterns formed in one or more layers of patternable material uses multiple exposure tools having different resolution limits and maximum expose field sizes. The measurement structure includes multiple complementary and coincident parts. An abutting field pattern is exposed and stitched in a layer of patternable material using a first exposure tool and a first mask. The abutting field pattern includes a first portion of the multiple complementary parts. A periphery pattern is exposed in the same layer or in a different layer of patternable material using a second exposure tool and a second mask. The periphery pattern includes a second portion of the multiple complementary parts. A maximum expose field of the first exposure tool is smaller than the maximum expose field of the second exposure tool.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: May 20, 2014
    Assignee: Truesense Imaging, Inc.
    Inventors: Robert P. Fabinski, Eric J. Meisenzahl, James E. Doran
  • Patent number: 8717544
    Abstract: In the present invention, a number of times the brightness changes detected at the same position while a substrate conveys are added up in the conveying direction, thereby obtaining a plurality of edge count data, and then, a plurality of positions of long sides of patterns parallel to the conveying direction is identified based on the plurality of edge count data exceeding a predetermined threshold value, middle point positions of a plurality of proximity pairs are calculated, and a middle point position close to the target position preset in the imaging device is selected from the plurality of middle point positions of the proximity pairs, an amount of position displacement between the selected middle point position and the target position of imaging device is calculated, and the photomask in the direction substantially perpendicular to the conveying direction so that the amount of position displacement is a predetermined value.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: May 6, 2014
    Assignee: V Technology Co., Ltd.
    Inventor: Takamitsu Iwamoto
  • Patent number: 8709687
    Abstract: A pattern from a patterning device is applied to a substrate by a lithographic apparatus. The applied pattern includes product features and metrology targets. The metrology targets include large targets and small targets which are for measuring overlay. Some of the smaller targets are distributed at locations between the larger targets, while other small targets are placed at the same locations as a large target. By comparing values measured using a small target and large target at the same location, parameter values measured using all the small targets can be corrected for better accuracy. The large targets can be located primarily within scribe lanes while the small targets are distributed within product areas.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: April 29, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Maurits Van Der Schaar, Patrick Warnaar, Kaustuve Bhattacharyya, Hendrik Jan Hidde Smilde, Michael Kubis
  • Patent number: 8703405
    Abstract: In a method of generating a three-dimensional process window qualification, a photoresist layer is coated on a substrate including an underlying structure. A plurality of circular-shaped regions of the substrate are distinguished into 1 to n regions to partition the substrate into a center portion and an edge portion, n being a natural number greater than 2. 1 to n exposing ranges are set, including a common exposing condition for the 1 to n regions. A photoresist pattern is fox led by exposing each shot portion in the 1 to n regions using a split exposing condition in the 1 to n exposing ranges. The photoresist pattern is detected, and a normal photoresist pattern with respect to each of the 1 to n regions is selected to generate the three-dimensional process window qualification.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: April 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hoon Sohn, Sang-Kil Lee, Yu-Sin Yang
  • Patent number: 8703368
    Abstract: A process for use in lithography, such as photolithography for patterning a semiconductor wafer, is disclosed. The process includes receiving an incoming semiconductor wafer having various features and layers formed thereon. A unit-induced overlay (uniiOVL) correction is received and a deformation measurement is performed on the incoming semiconductor wafer in an overlay module. A deformation-induced overlay (defiOVL) correction is generated from the deformation measurement results by employing a predetermined algorithm on the deformation measurement results. The defiOVL and uniiOVL corrections are fed-forward to an exposure module and an exposure process is performed on the incoming semiconductor wafer.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Yao Lee, Ying Ying Wang, Heng-Hsin Liu, Chin-Hsiang Lin
  • Patent number: 8685633
    Abstract: A method of printing an image on a wafer. The method includes the steps of printing a main image, wherein the main image includes fields which are fully on the wafer, and printing an alternate image, wherein the alternate image includes fields which are only partially on the wafer. The alternate image could be placed on a separate mask which is loaded onto the exposure tool after the mask with the main image has completed printing. Alternatively, it could be an extra image specially inserted on the mask with the main image for that layer.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: April 1, 2014
    Assignee: LSI Corporation
    Inventors: Duane B. Barber, David J. Sturtevant
  • Publication number: 20140072904
    Abstract: There is provided a photomask capable of improving alignment accuracy with respective photomasks disposed on the front and rear faces of a substrate. A photomask has a drawing pattern for exposure formed on one face opposing a substrate, a first alignment mark for alignment with a substrate side mark formed on the substrate, the first alignment mark being provided in a region of the one face, the region opposing the substrate when the substrate is retained and the drawing pattern is not formed in the region, and a second alignment mark for alignment with a third alignment mark provided on another photomask, the second alignment mark being provided in a region which does not oppose the substrate when the substrate is retained.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 13, 2014
    Applicant: NIPPON MEKTRON, LTD.
    Inventors: Shoji TAKANO, Fumihiko MATSUDA, Yoshihiko NARISAWA
  • Patent number: 8663877
    Abstract: Lithography masks, lithography systems, methods of manufacturing lithography masks, methods of altering material layers of semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a lithography mask includes a first pattern for at least one material layer of at least one die, the first pattern being oriented in a first position. The lithography mask includes a second pattern for at least one material layer of the at least one die, the second pattern being oriented in a second position. The second position is different than the first position.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: March 4, 2014
    Assignee: Infineon Technologies AG
    Inventor: Uwe Paul Schroeder
  • Patent number: 8625096
    Abstract: A semiconductor wafer is aligned using a double patterning process. A first resist layer having a first optical characteristic is deposited and foams at least one alignment mark. The first resist layer is developed. A second resist layer having a second optical characteristic is deposited over the first resist layer. The combination of first and second resist layers and alignment mark has a characteristic such that radiation of a pre-determined wavelength incident on the alignment mark produces a first or higher order diffraction as a function of the first and second optical characteristics.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: January 7, 2014
    Assignees: ASML Holding N.V., ASML Netherlands B.V.
    Inventors: Harry Sewell, Mircea Dusa, Richard Johannes Franciscus Van Haren, Manfred Gawein Tenner, Maya Angelova Doytcheva
  • Patent number: 8625109
    Abstract: An apparatus and a method for determining an overlap distance of an optical head is disclosed. Positions and light amount distributions of each light spot can be measured, which may be provided from an optical head to a substrate. Gaussian distribution may be applied to the positions and the light amount distributions to calculate a compensation model of each of the light spots. A first accumulated light amount corresponding to each first area of the substrate may be calculated if the optical head is scanning along a first direction of the substrate using the compensation model. A second accumulated light amount corresponding to each second area overlapped with the each first area is calculated if the optical head is scanning along the first direction, which is moved in a second direction by a first distance using the compensation model. An overlap distance may be determined based on a uniformity of summations of the first and second accumulated light amount.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: January 7, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang-Hyun Yun, Hi-Kuk Lee, Sang-Woo Bae, Cha-Dong Kim, Jung-In Park
  • Patent number: 8617774
    Abstract: A method for calibrating an apparatus for the position measurement of measurement structures on a lithography mask comprises the following steps: qualifying a calibration mask comprising diffractive structures arranged thereon by determining positions of the diffractive structures with respect to one another by means of interferometric measurement, determining positions of measurement structures arranged on the calibration mask with respect to one another by means of the apparatus, and calibrating the apparatus by means of the positions determined for the measurement structures and also the positions determined for the diffractive structures.
    Type: Grant
    Filed: April 10, 2010
    Date of Patent: December 31, 2013
    Assignee: Carl Zeiss SMS GmbH
    Inventors: Norbert Kerwien, Jochen Hetzler
  • Patent number: 8610944
    Abstract: A method of achieving process-direction sub-raster magnification adjustment using non-redundant overwriting. The raster imager provides overwriting while the image path provides non-redundant data for each pass according to the desired magnification adjustment. The same laser power level can be used for the multiple writes, or optionally, it may be varied to further improve spatial resolution of the adjustment.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: December 17, 2013
    Assignee: Xerox Corporation
    Inventors: Beilei Xu, Robert P. Loce, Jess R. Gentner
  • Patent number: 8609301
    Abstract: A circular cylinder-shaped mask is used to form an image of a pattern on a substrate via a projection optical system. The mask has a pattern formation surface on which the pattern is formed and that is placed around a predetermined axis, and the mask is able to rotate, with the predetermined axis taken as an axis of rotation, in synchronization with a movement of the substrate in at least a predetermined one-dimensional direction. When a diameter of the mask on the pattern formation surface is taken as D, and a maximum length of the substrate in the one-dimensional direction is taken as L, and a projection ratio of the projection optical system is taken as ?, and circumference ratio is taken as ?, then the conditions for D?(?√óL)/? are satisfied.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: December 17, 2013
    Assignee: Nikon Corporation
    Inventor: Yuichi Shibazaki
  • Patent number: 8592111
    Abstract: Disclosed is an LCD panel photolithography process, employed in a lithography system for manufacturing a plurality of LCD panel, comprising steps of: performing photolithography to a glass substrate with a first mask, and the first mask comprises a plurality of sets of alignment marks corresponding to a plurality of following masks thereafter, and a plurality of sets of alignment marks corresponding to the plurality of following masks thereafter are formed on the glass substrate; and employing the plurality of sets of alignment marks on the glass substrate respectively, to perform alignment procedure and photolithography for the plurality of following masks with the plurality of sets of alignment marks on the glass substrate to form patterns; wherein corresponding to the same LCD panel area, the plurality of sets of alignment marks on the glass substrate have different position coordinates respectively.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: November 26, 2013
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Cai Ii Zhang
  • Patent number: 8592107
    Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: November 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guo-Tsai Huang, Fu-Jye Liang, Li-Jui Chen, Chih-Ming Ke
  • Patent number: 8592110
    Abstract: A plurality of reticles for printing structures in the same lithography level includes an alignment structure pattern within a same relative location in each reticle. Each set of process segmentations in a grating has a reticle segmentation pitch, which is common across all gratings in the plurality of reticles. Within each pair of alignment structure patterns that occupy the same relative location in any two of the plurality of reticles, the process segmentations in one reticle are shifted relative to the process segmentations in the other reticle by a fraction of a reticle segmentation pitch. After printing all patterns in the plurality of reticles, a composite printed process segmentation structure on the substrate includes printed segmentation structures that are spaced by 1/n times the printed segmentation pitch. The pattern for the next level can be aligned to the composite printed process segmentation structure in a single alignment operation.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Allen H. Gabor, Vinayan C. Menon
  • Patent number: 8587782
    Abstract: An optical-component fabricating method includes arranging a mask that has both an optical component pattern and an alignment mark pattern and a wafer that is developed through the mask at predetermined positions; exposing the optical component pattern and the alignment mark pattern onto the wafer; developing the alignment mark pattern that is exposed on the wafer; observing a position of the developed alignment mark pattern and moving the wafer in accordance with the position; repeating the exposing, the developing, and the moving a predetermined number of times; developing all the optical component patterns on the wafer; and etching the developed optical component patterns.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: November 19, 2013
    Assignee: Fujitsu Limited
    Inventor: Satoshi Kai
  • Patent number: 8585915
    Abstract: A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one sub-resolution alignment mark extending partially into the dielectric material. At least one opening is formed in the dielectric material. Semiconductor structures comprising the sub-resolution alignment marks are also disclosed.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: November 19, 2013
    Assignee: Micron Technology, Inc.
    Inventors: David S. Pratt, Marc A. Sulfridge
  • Patent number: 8563952
    Abstract: A charged particle beam writing apparatus, includes a unit to input information about a stripe region height, and to judge, when a write region is divided into stripe regions in a thin rectangular shape by the stripe region height, whether a height of a last stripe region is narrower than the stripe region height; and a unit to divide the write region into stripe regions in the thin rectangular shape in such a way that the last stripe region and a stripe region prior to the last stripe region are combined to create one stripe region and stripe regions at least two stripe regions prior to the last stripe region are each created as stripe regions of the stripe region height if the height of the last stripe region is narrower than the stripe region height.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: October 22, 2013
    Assignee: NuFlare Technology, Inc.
    Inventors: Jun Yashima, Akihito Anpo
  • Patent number: 8563202
    Abstract: A method for stitching a first field mask to a second field mask on a wafer includes providing a photomask with a first set of targets and a second set of targets, printing images of the first set of targets and the second set of targets onto the wafer where the photomask is applied to the wafer having no previous alignment marks formed thereon for the photomask to align to. A first set of alignment marks is formed from the first set of targets and a second set of alignment marks is formed from the second set of targets. The method includes aligning a first field mask to the first set of alignment marks and aligning a second field mask to the second set of alignment marks. The images of the first field mask and the second field mask are thereby stitched together on the wafer.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: October 22, 2013
    Assignee: Micrel, Inc.
    Inventor: Arthur Lam
  • Patent number: 8554510
    Abstract: Movements of a lithographic apparatus include dynamic positioning errors on one or more axes which cause corresponding errors which can be measured in the applied pattern. A test method includes operating the apparatus several times while deliberately imposing a relatively large dynamic positioning error at different specific frequencies and axes. Variations in the error in the applied pattern are measured for different frequencies and amplitudes of the injected error across a frequency band of interest for a given axis or axes. Calculation using said measurements and knowledge of the frequencies injected allows analysis of dynamic positioning error variations in frequency bands correlated with each injected error frequency.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: October 8, 2013
    Assignee: ASML Netherlands B.V.
    Inventors: Frank Staals, Hans Van Der Laan, Hans Butler, Gerardus Carolus Johannus Hofmans, Sven Gunnar Krister Magnusson
  • Patent number: 8555208
    Abstract: Methods, systems, and tool sets involving reticles and photolithography processing. Several embodiments include obtaining qualitative data from within the pattern area of a reticle indicative of the physical characteristics of the pattern area. Additional embodiments include obtaining qualitative data indicative of the physical characteristics of the reticle remotely from a photolithography tool. In further embodiments qualitative data is obtained from within the pattern area of a reticle in a tool that is located remotely from the photolithography tool. Several embodiments provide data taken from within the pattern area to more accurately reflect the contour of the pattern area of the reticle without using the photolithography tool to obtain such measurements. This is expected to provide accurate data for correcting the photolithography tool to compensate for variances in the pattern area, and to increase throughput because the photolithography tool is not used to measure the reticle.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: October 8, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Craig A. Hickman
  • Patent number: 8535858
    Abstract: The present invention relates to a photomask and a method for forming an overlay mark in a substrate using the same. The photomask comprises a plurality of patterns. At least one of the patterns comprises a plurality of ring areas and a plurality of inner areas enclosed by the ring areas, wherein the light transmittancy of the ring areas is different from that of the inner areas. When the photomask is applied in a photolithography process, the formed overlay mark has a large thickness. Therefore, the contrast is high when a metrology process is performed, and it is easy to find the overlay mark.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: September 17, 2013
    Assignee: Nanya Technology Corp.
    Inventor: Chui Fu Chiu
  • Patent number: 8530120
    Abstract: A method for patterning a second layer of a work piece in a direct write machine in the manufacturing of a multilayer system-in-package stack. The work piece having a first layer with a plurality of electrical components in the form of dies arbitrarily placed. Each component having connection points where some need to be connected between the components. A first pattern wherein different zones comprising connection points of dies distributed in the first layer are associated with different requirements on alignment. The method comprising the steps of: a. Detecting sacred zones in first pattern that have a high requirement on alignment to selected features of the system-in-package stack or to the placed components; b. Detecting stretch zones of the first pattern that are allowed to have a lower requirement on alignment to other features of the system-in-package stack; c.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: September 10, 2013
    Assignee: Micronic Mydata AB
    Inventors: Mikael Wahlsten, Per-Erik Gustafsson
  • Patent number: 8530121
    Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: September 10, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
  • Patent number: 8524426
    Abstract: A method for correcting a position error of a lithography apparatus comprises inputting position data of exposure pattern, irradiating laser light onto a position reference mask from a position measurement laser system, calculating actual position data of the laser light irradiated onto the position reference mask, and comparing the position data of the exposure pattern with the actual position data of the laser light irradiated onto the position reference mask. With this method, circuit patterns can be accurately formed at predetermined positions on a photomask, and the circuit patterns on the photomask can be accurately formed at predetermined positions on a wafer.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: September 3, 2013
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Jin Choi, Dong-Seok Nam
  • Patent number: 8512918
    Abstract: By forming on a substrate a reference point mark having a concave or convex shape with its side walls being generally upright, even if a multilayer reflective film, an absorber film, and so on are formed over the reference point mark, sufficient contrast for inspection light is obtained so that the position of the reference point mark can be identified with high accuracy.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: August 20, 2013
    Assignee: Hoya Corporation
    Inventor: Tsutomu Shoki
  • Patent number: 8486587
    Abstract: A method for correcting a layout pattern includes the following steps. A first layout pattern, a second layout pattern, and a mis-alignment value are provided. The first layout pattern includes a first conducting line pattern, and the second layout pattern includes at least one contact via pattern. The contact via pattern at least partially overlaps the first conducting line pattern. The layout pattern is verified whether spacing between the contact via pattern and the first conducting line pattern is smaller than the mis-alignment value by a computing system. A first modified contact via pattern is then obtained by expanding the contact via pattern along a direction away from the spacing smaller than the mis-alignment value.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 16, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chen-Hua Tsai, Chia-Wei Huang
  • Patent number: 8486593
    Abstract: Methods of making flexible circuit films include providing a polymer film or other flexible substrate having a plurality of alignment marks and a photosensitive material thereon. The substrate passes around a suitable roller, belt, or other inelastic conveyor such that the substrate and the conveyor move together at least from a first location to a second location. Positions of a first set of the alignment marks on a first portion of the substrate are measured when such portion is at the first location, and the measured positions can be used to calculate a distortion of the substrate. The photosensitive material is then patternwise exposed when the first portion of the substrate has moved to the second location. The patternwise exposing is based on the measured positions of the first set of alignment marks, and may include exposing the web with a distortion-adjusted pattern. Related systems and articles are also disclosed.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: July 16, 2013
    Assignee: 3M Innovative Properties Company
    Inventors: Michael A. Haase, Jeffrey H. Tokie, Daniel J. Theis, Brian K. Nelson
  • Patent number: 8455162
    Abstract: A plurality of reticles for printing structures in the same lithography level includes an alignment structure pattern within a same relative location in each reticle. Each set of process segmentations in a grating has a reticle segmentation pitch, which is common across all gratings in the plurality of reticles. Within each pair of alignment structure patterns that occupy the same relative location in any two of the plurality of reticles, the process segmentations in one reticle are shifted relative to the process segmentations in the other reticle by a fraction of a reticle segmentation pitch. After printing all patterns in the plurality of reticles, a composite printed process segmentation structure on the substrate includes printed segmentation structures that are spaced by 1/n times the printed segmentation pitch. The pattern for the next level can be aligned to the composite printed process segmentation structure in a single alignment operation.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Allen H. Gabor, Vinayan C. Menon
  • Patent number: 8440372
    Abstract: A single field photomask includes a first set of targets formed on a first side of the photomask, and a second set of targets formed on a second side of the photomask, opposite the first side. In operation, the photomask is to be applied to a wafer without any alignment marks. The photomask forms a first set of alignment marks in the wafer from the first set of targets, and the photomask further forms a second set of alignment marks in the wafer from the second set of targets. The first set of alignment marks is used to align to a first field mask and the second set of alignment marks is used to align to a second field mask to stitch an image of the first field mask to an image of the second field mask.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: May 14, 2013
    Assignee: Micrel, Inc.
    Inventor: Arthur Lam
  • Patent number: 8435702
    Abstract: Provided is a technique capable of improving the dimensional accuracy of a transfer pattern in a lithography technique in which EUV light is used and the EUV light is incident obliquely on a mask and an image of the EUV light reflected from the mask is formed on a semiconductor substrate (resist film), thereby transferring the pattern formed on the mask onto the semiconductor substrate. The present invention is based on a lithography technique in which EUV light is used and an exposure optical system in which the EUV light is obliquely incident on a mask is used. In this lithography technique, an absorber and a difference in level are formed on the mask, and a projective component projected on a mask surface out of a direction cosine component of the incident light is set to be almost orthogonal to an extending direction of the difference in level.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: May 7, 2013
    Assignees: Renesas Electronics Corporation, Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Terasawa, Takeshi Yamane
  • Patent number: 8432548
    Abstract: Systems and methods for alignment of template and substrate at the edge of substrate are described.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: April 30, 2013
    Assignee: Molecular Imprints, Inc.
    Inventors: Byung-Jin Choi, Pawan Kumar Nimmakayala, Philip D. Schumaker
  • Patent number: 8431827
    Abstract: Circuit modules including identification codes and a method of managing them are provided. A module substrate includes signal input output terminals and outer ground terminals provided at the peripheral portions of a surface which becomes a mounting surface when the circuit module is completed. An inner-ground-terminal formation area surrounded by the signal input output terminals and the outer ground terminals includes a plurality of inner ground terminals arranged in a matrix of rows and columns. One of the edge portions is a direction identification area. The inner ground terminal is not provided in the direction identification area, and a first identification code having information about the position of the module substrate is provided in the direction identification area.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: April 30, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroshi Nishikawa, Taro Hirai
  • Patent number: 8411271
    Abstract: A plurality of wafer marks on a wafer is detected while a wafer stage moves from a loading position where a wafer is delivered onto the wafer stage to an exposure starting position where exposure of a wafer begins, with a part of an alignment system also moving, using the alignment system. Accordingly, the time required for mark detection can be reduced, therefore, it becomes possible to increase the throughput of the entire exposure process.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: April 2, 2013
    Assignee: Nikon Corporation
    Inventor: Yuichi Shibazaki
  • Patent number: 8404410
    Abstract: An exposure system includes an exposure device and an image processing device. The exposure device includes a plurality of cameras. Each of the cameras is configured so as to be selectively set to a full scan mode and a partial scan mode. The camera transmits all of obtained image data in the full scan mode, and extracts part of the obtained image data and transmits the partial image data in the partial scan mode. The image processing device paratactically performs processing using the image data transmitted from the camera and processing using the image data transmitted from the camera.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: March 26, 2013
    Assignee: Nitto Denko Corporation
    Inventors: Kousuke Murakami, Akira Arima, Tomohiro Hattori, Shuuhei Miyazaki
  • Patent number: 8399160
    Abstract: Provided is a reflective mask blank, wherein even if inspection light for defect inspection is irradiated onto an uppermost surface of a multilayer reflective film or of an absorber film formed over a reference point mark, sufficient contrast is obtained between a position of the reference point mark and its peripheral portion so that the position of the reference point mark can be identified with high accuracy. By forming a reference point mark (11) in the form of a recess having a depth of 10 ?m or more and a width of 80 ?m or more on a main surface of a substrate (12), even if a multilayer reflective film (13), an absorber film (15), and so on are formed over the reference point mark (11), sufficient contrast for the inspection light is obtained so that the position of the reference point mark (11) can be identified with high accuracy.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: March 19, 2013
    Assignee: Hoya Corporation
    Inventor: Tsutomu Shoki
  • Patent number: 8399163
    Abstract: When an alignment mark does not exist within an area of an image obtained by a camera, the coordinate of the alignment mark is calculated based on an identification mark existing in the area of the image and a previously stored positional relationship between the alignment mark and the identification mark. A distance by which a long-sized base material is to be moved for causing the alignment mark to be positioned within the imaging area of the camera is calculated based on the calculated coordinate of the alignment mark, and the long-sized base material is moved by the calculated distance.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: March 19, 2013
    Assignee: Nitto Denko Corporation
    Inventors: Kousuke Murakami, Akira Arima, Tomohiro Hattori, Shuuhei Miyazaki