Abstract: A method of correcting an image characteristic of a substrate onto which one or more product features have been formed using a lithographic process, and an associated inspection apparatus method. The method includes measuring an error in the image characteristic of the substrate, and determining a correction for a subsequent formation of the product features based upon the measured error and a characteristic of one or more of the product feature(s).

Abstract: A lithography apparatus has a plurality of processing units configured to respectively perform patternings on a plurality of substrates that belong to a lot, and a controller configured to perform, based on specific information that specifies one of the plurality of substrates, determination of one of the plurality of processing units that processes the one of the plurality of substrates, and control the plurality of processing units such that the patternings are performed on the plurality of substrates respectively with the plurality of processing units in parallel based on recipe information corresponding to the lot.

Abstract: One feature pertains to an advanced computer device configured for storing data on a plurality of non-volatile memory mass storage devices. The mass storage devices may interface with the computer device through a plurality of base boards mounted in an enclosure that are configured to couple with at least one non-volatile memory storage drive. Each base board may further be configured to couple with a high speed interconnect cable to exchange data to be loaded or stored with the computer device. According to one aspect, the high speed cable transfers Serially Attached SCSI (SAS) or PCIe data packets or frames.

Abstract: The present invention provides a color resist mask sheet and a method of use thereof. The color resist mask sheet includes an align coat mark region and an align test mark region. The align coat mark region includes a plurality of equally spaced align coat marks of coat color resist; the align test mark region includes a plurality of equally spaced align test marks for coating the test color resist, wherein each align test mark corresponds to each align coat mark.

Abstract: Disclosed are methods and systems for determining and displaying a simulated deformation of a 3D object data model. In one aspect, a method is disclosed that includes causing a force to be applied to an object to cause a deformation of the object and causing a plurality of reference scans of the object to be captured. The method further includes, based on the plurality of reference scans, generating a 3D object data model representing the object and, further based on the plurality of reference scans, identifying a constraint point of the 3D object data model, where the constraint point represents a point of minimum deformation of the object. The method still further includes selecting a predefined deformation model, where the predefined deformation model defines a simulated deformation, and where the simulated deformation simulates at least a portion of the deformation of the object proximate to the point of minimum deformation.

Abstract: A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.

Abstract: A method for classification includes receiving an image of an area of a semiconductor wafer on which a pattern has been formed, the area containing an image location of interest, and receiving computer-aided design (CAD) data relating to the pattern comprising a CAD location of interest corresponding to the image location of interest. At least one value for one or more attributes of the image location of interest is computed based on a context of the CAD location of interest with respect to the CAD data.

Abstract: The present disclosure relates to a method of semiconductor processing. The method includes, receiving a first wafer having a photoresist coating on a face of the first wafer. An exposure unit is used to perform a first number of radiation exposures on the photoresist coating, thereby forming an exposed photoresist coating. The exposed photoresist coating is developed, thereby forming a developed photoresist coating. An OVL measurement zone pattern is selected from a number of different, pre-determined OVL measurement zone patterns based on at least one of: the first number of radiation exposures performed on the first wafer or a previous number of radiation exposures performed on a previously processed wafer, which was processed before the first wafer. A number of OVL measurements are performed on the developed photoresist coating within the selected OVL measurement zone pattern.

Abstract: The present invention provides a method of aligning a quadrate wafer in a first photolithography process. The method includes: step A: fabricating mask aligning markers in a periphery region of a mask, which is used for a first exposure process of the quadrate wafer, around a mask pattern of the mask; step B: during the first exposure process, positioning the quadrate wafer in a preset region by using the mask aligning markers on the mask, and exposing the quadrate wafer through the mask; and step C: performing alignment for the quadrate wafer during a second exposure process and subsequent exposure processes by using aligning markers on the quadrate wafer that are obtained during the first exposure process. The method may be easily and reliably performed to ensure intact dies at periphery of a quadrate wafer to be produced and thus render increased yield of chips.

Abstract: An overlay measurement and correction method and device is provided. In an embodiment the measurement device takes measurements of a first semiconductor wafer and uses the measurements in a plurality of correction techniques to generate an overlay correction model. The plurality of correction techniques include a first order correction, a first intra-field high order parameter correction and a first inter-field high order parameter correction. The model is used to adjust the exposure parameters for the exposure of the next semiconductor wafer. The process is repeated on each semiconductor wafer for a run-to-run analysis.

Abstract: A method of manufacturing a deposition mask is disclosed. In one aspect, the method includes depositing a first photoresist layer on a substrate, aligning a first photomask over the first photoresist layer and developing the first photoresist layer to form a plurality of first photoresist patterns having sides that gradually narrow toward the substrate. The method also includes forming a metal layer over the first photoresist patterns and a portion of the substrate exposed by the first photoresist patterns, depositing a second photoresist layer over the metal layer and aligning a second photomask over the second photoresist layer and developing the second photoresist layer to form a plurality of second photoresist patterns between the first photoresist patterns. The method further includes etching the metal layer to form a pattern hole, removing the first and second photoresist patterns and separating the substrate so as to form a deposition mask.

Abstract: A projection exposure tool for microlithography for imaging mask structures of an image-providing substrate onto a substrate to be structured includes a measuring apparatus configured to determine a relative position of measurement structures disposed on a surface of one of the substrates in relation to one another in at least one lateral direction with respect to the substrate surface and to thereby simultaneously measure a number of measurement structures disposed laterally offset in relation to one another.

Abstract: Methods and apparatus for front-to-back alignment using narrow scribe lines are disclosed. An apparatus is disclosed that includes a semiconductor wafer comprising a plurality of areas for the fabrication of integrated circuit devices on a device side, the integrated circuit devices arranged in rows and columns and spaced from one another by a plurality of scribe lines disposed on the semiconductor wafer in areas between the integrated circuit devices and free from integrated circuit devices; and one or more alignment marks disposed on the semiconductor wafer, the alignment marks positioned in an intersection of two of the scribe lines; wherein the scribe lines have a first minimum dimension and the one or more alignment marks have a second minimum dimension that is greater than the first minimum dimension. Methods and additional apparatus are disclosed.

Abstract: The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. The aligning mark is disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern. The aligning mark comprises a plurality of second patterns in the middle region and a plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the L-shapes. The present invention further provides a method of forming the same.

Abstract: Among other things, one or more systems and techniques for scanner alignment sampling are provided. A set of scan region pairs are defined along a periphery of a sampling area associated with a semiconductor wafer. Alignment marks are formed within scan regions of the set of scan region pairs, but are not formed within other regions of the sampling area. In this way, scan region pairs are scanned to determine alignment factors for respective scan region pairs. An alignment for the sampling area, such as layers or masks used to form patterns onto such layers, is determined based upon alignment factors determined for the scan region pairs.

Abstract: Methods and apparatuses for manufacturing self-aligned integrated back contact heterojunction solar cells are provided. In some embodiments, systems for forming a solar cell on a substrate are provided, the systems comprising: a master shadow mask positioned adjacent to the substrate on a first side of the master shadow mask; a first blocking mask placed adjacent to a second side of the master shadow mask; and a deposition machine that deposits material on the substrate through holes in the master shadow mask and the first blocking mask.

Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.

Abstract: The present invention provides a measuring apparatus for measuring a position of an alignment mark formed on a substrate and including a first mark having position information in a first direction and a second mark having position information in a second direction different from the first direction, the apparatus including a detector configured to detect an image of the alignment mark, a controller configured to control movement of a stage for holding the substrate and detection by the detector, and a processor configured to obtain a position of the alignment mark whose image is detected by the detector, wherein the controller is configured to cause the detector to detect the image of the alignment mark with the stage moving in the first direction, and cause the detector to detect the image of the alignment mark with the stage moving in the second direction.

Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force.

Abstract: A photo mask includes a pre-alignment key used in a pre-alignment process performed in a photolithography apparatus. The pre-alignment key includes a pre-alignment pattern including a light transmitting area and a light blocking area surrounding the pre-alignment pattern. The light blocking area includes a plurality of light blocking patterns and a diffraction grating pattern separating the plurality of light blocking patterns from each other.

Abstract: The exposure apparatus includes a first detector, a first alignment unit, a second detector, and a second alignment unit, and a controller, wherein the controller controls the second alignment unit so that alignment of a substrate is conducted based on a detection result from detection of the mark by the second detector in a first view when alignment of the substrate can be conducted by the first alignment unit at a prescribed alignment accuracy, and controls the second alignment unit so that alignment of the substrate is conducted based on a detection result from detection of the mark by the second detector in a second view that is wider than the first view when alignment of the substrate cannot be conducted by the first alignment unit at the prescribed alignment accuracy.

Abstract: A lithographic or exposure apparatus has a projection system and a controller. The projection system includes a stationary part and a moving part. The projection system is configured to project a plurality of radiation beams onto locations on a target. The locations are selected based on a pattern. The controller is configured to control the apparatus to operate in a first mode or a second mode. In the first mode the projection system delivers a first amount of energy to the selected locations. In the second mode the projection system delivers a second amount of energy to the selected locations. The second amount of energy is greater than the first amount of energy.

Abstract: The invention relates to an illumination device (1) specifically a packaged LED (2), which is embedded in a casing body leaving the bottom side of the LED (2) exposed; on the bottom side, a contacting element (7) is vacuum deposited onto the LED (2), which contacting element protrudes laterally above the LED (2) and allows on a macroscopic level for an electric contacting of the LED (2), namely by connection of flat surfaces, such as welding.

Abstract: A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.

Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.

Abstract: The present invention relates to a nanoimprint lithography method.

Abstract: A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.

Abstract: An imprinting method of this disclosure includes supplying an imprint material on a substrate having a pattern including a mark on the substrate formed thereon; bringing a mold having a pattern including a mark on the mold into contact with the imprint material; curing the imprint material in a state in which the mold is in contact therewith; and forming a pattern including the mark on the imprint material, and characterized in that an optical system configured to form an image of the mark on the imprint material and an image of the mark on the substrate are used to detect the mark on the imprint material and the mark on the substrate after the space between the substrate and the mold has been increased until the mark on the mold is positioned out of a focal depth of the optical system, thereby obtaining a relative positional deviation between the pattern on the substrate and the pattern on the imprint material.

Abstract: A projection exposure tool for microlithography for imaging mask structures of an image-providing substrate onto a substrate to be structured includes a measuring apparatus configured to determine a relative position of measurement structures disposed on a surface of one of the substrates in relation to one another in at least one lateral direction with respect to the substrate surface and to thereby simultaneously measure a number of measurement structures disposed laterally offset in relation to one another.

Abstract: A photo-mask for use in extreme ultraviolet (EUV) lithography, in which the photo-mask has low coefficient of thermal expansion and high specific stiffness.

Abstract: The present invention provides a film edge detecting method and a film edge detecting device. The film edge detecting method is used for detecting a film edge of a film layer formed on a substrate, the film layer comprises a patterned film layer, the method includes: forming at least one scale pattern in the patterned film layer, a film edge of the patterned film layer corresponding to an edge of the scale pattern; obtaining a patterned film edge indication value of the edge of the scale pattern; and obtaining a second distance, which is a distance between the film edge of the non-patterned film layer and a corresponding edge of the substrate, based on the non-patterned film edge indication value and a preset reference value of the corresponding edge of the substrate.

Abstract: An exposure apparatus includes a controller configured to control scanning of an original holding unit and a substrate holding unit to expose a first pattern forming area onto a plurality of second pattern forming areas formed in advance on the substrate. The first pattern forming area is superimposed on the plurality of second pattern forming areas. An original may include the first pattern forming area in plural. The controller is configured to change the operation of the original holding unit or the substrate holding unit among the plurality of second pattern forming areas based on a state of the second pattern forming areas or a state of the first pattern forming areas while the first pattern forming areas are scanning-exposed onto the plurality of second pattern forming areas in a single scanning between the original holding unit and the substrate holding unit.

Abstract: Embodiments described herein relate to apparatus and methods of thermal processing. More specifically, apparatus and methods described herein relate to laser thermal treatment of semiconductor substrates by increasing the uniformity of energy distribution in an image at a surface of a substrate.

Abstract: Provided is an integrated circuit (IC) testline layout. The layout has a device boundary and a main pattern boundary inside the device boundary. The layout includes at least one main pattern inside the main pattern boundary. The layout further includes a plurality of dummy patterns in a region that is between the main pattern boundary and the device boundary. The plurality of dummy patterns is printable in a photolithography process and is arranged in a ring with a uniform spacing between two adjacent dummy patterns.

Abstract: Systems, methods, and devices for reducing an occlusion in an image are described herein. For example, one or more embodiments include a method including providing image information from a first image taken from a light field camera, analyzing image information from multiple sub-aperture images extracted from the image information of the first image to separate foreground and background appearance information, creating a mask of an occlusion based on the separated foreground and background appearance information, and rendering a second, modified image where the mask has been applied to reduce the occlusion in the modified image.

Abstract: A method of coating a workpiece is provided. In the method, a coating device is provided. The coating device includes a transparent covering plate and an ultraviolet light source device. The workpiece is placed in the coating device. Coating material is injected into the coating device to coat the workpiece. The coating material is ultraviolet light curable material. The ultraviolet light source device emits ultraviolet light and the ultraviolet light passes through the transparent covering plate to cure the coating material on the workpiece. The workpiece is taken out of the coating device.

Abstract: A method for establishing distortion properties of an optical system in a microlithographic measurement system is provided. The optical system has at least one pupil plane, in which the distortion properties of the optical system are established on the basis of measuring at least one distortion pattern, which the optical system generates when imaging a predetermined structure in an image field. The distortion properties of the optical system are established on the basis of a plurality of measurements of distortion patterns, in which these measurements differ from one another in respect of the intensity distribution present in each case in the pupil plane.

Abstract: A mark detecting method of detecting a notch as a mark formed on the outer circumference of a wafer held on a holding table. The mark detecting method includes the steps of index-rotating the holding table to image at least three points on the outer circumference of the wafer and to thereby detect the coordinates at the three points on the outer circumference of the wafer, calculating the center of the wafer from the coordinates at the three points, centering the wafer with respect to the holding table, and continuously rotating the holding table through 360° to image the whole of the outer circumference of the wafer by using a minimum imaging area corresponding to the outer circumference of the wafer and to thereby detect the angle where the notch is located.

Abstract: In an overlay displacement amount measuring method according to an embodiment, a temperature distribution of a substrate during a pattern forming process and a temperature distribution of the substrate during a measuring process for measuring a positional displacement amount between patterns on the substrate by an electron microscope are measured. An expansion/contraction amount of the substrate between two processes is calculated based upon the two temperature distributions, and the positional displacement amount is corrected based upon the expansion/contraction amount. An overlay displacement amount between the pattern and a pattern formed on a layer different from the pattern is measured by an optical measuring apparatus, and the overlay displacement amount is corrected based upon the corrected positional displacement amount.

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.

Abstract: Aspects of the present disclosure describe systems and methods for calibrating a metrology tool by using proportionality factors. The proportionality factors may be obtained by measuring a substrate under different measurement conditions. Then calculating the measured metrology value and one or more quality merits. From this information, proportionality factors may be determined. Thereafter the proportionality factors may be used to quantify the inaccuracy in a metrology measurement. The proportionality factors may also be used to determine an optimize measurement recipe. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A substrate is loaded onto a substrate support of a lithographic apparatus, after which the apparatus measures locations of substrate alignment marks. These measurements define first correction information allowing the apparatus to apply a pattern at one or more desired locations on the substrate. Additional second correction information is used to enhance accuracy of pattern positioning, in particular to correct higher order distortions of a nominal alignment grid. The second correction information may be based on measurements of locations of alignment marks made when applying a previous pattern to the same substrate. The second correction information may alternatively or in addition be based on measurements made on similar substrates that have been patterned prior to the current substrate.

Abstract: The present invention provides a method of forming a detection mark from line patterns formed on a substrate, including a first step of deciding a first region for forming the detection mark on the substrate, and a second region which surrounds the first region and in which formation of the detection mark is forbidden, and a second step of projecting, onto the substrate by a projection optical system, patterns including a first cut pattern for partially cutting the line pattern in the first region to form a plurality of mark elements, and a removal pattern for removing the line pattern in the second region, and forming the detection mark including the plurality of mark elements.

Abstract: The present invention discloses a test method for monitoring the stability of process and a test module device thereof. The test module device comprises: a substrate, a certain number of the first metal wires, a certain number of the second metal wires, an insulating block is disposed between the adjacent first metal wires. The method comprises: a preconfigured value of the test current in the test module is provided in the process; the multiple test module devices are provided. The present invention adopts a method adopting an offset to set the upper metal wire and lower metal wire in the test module instead of regular equal interval setting. Consequently, the safety zone of the overlay in the process can be determined. The present invention can monitor the stability of the process.

Abstract: A substrate stage is used in a lithographic apparatus. The substrate stage includes a substrate table constructed to hold a substrate and a positioning device for in use positioning the substrate table relative to a projection system of the lithographic apparatus. The positioning device includes a first positioning member mounted to the substrate table and a second positioning member co-operating with the first positioning member to position the substrate table. The second positioning member is mounted to a support structure. The substrate stage further comprises an actuator that is arranged to exert a vertical force on a bottom surface of the substrate table at a substantially fixed horizontal position relative to the support structure.

Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.

Abstract: The general inventive concepts relate to the field of display technology, and provide a mask plate and a method for producing a substrate mark to increase the accuracy of the production of a substrate mark, and decrease the difficulty in monitoring products and the production cost. An exemplary mask plate comprises: a display region mask part; at least one pair of test mark mask parts, a test mark mask part being located on either side of the display region mask part and their positions being opposite to each other; and a protection mark mask part correspondingly disposed on the outside of each test mark mask part relative to the display region mask part, wherein the pattern outline of the protection mark mask part is larger than that of the test mark mask part.

Abstract: According to one embodiment, a method for measuring pattern misalignment, includes: a first step obtaining image data; a second step specifying a measurement region; a third step calculating a first shift amount (x1, y1); a fourth step determining, after calculating the first shift amount, a first distribution; a fifth step executing a plurality of times the second step, the third step, and the fourth step; a seventh step calculating a second shift amount (x2, y2); an eighth step determining, after calculating the second shift amount, a second distribution; a ninth step executing a plurality of times the sixth step, the seventh step, and the eighth step; and a tenth step calculating a difference (x2?x1, y2?y1) between the second pattern misalignment and the first pattern misalignment.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first surface and a second surface opposite the first surface, forming an alignment key and a connection contact that penetrate a portion of the semiconductor substrate and extend from the first surface toward the second surface, forming a first circuit on the first surface of the semiconductor substrate such that the first circuit is electrically connected to the connection contact, recessing the second surface of the semiconductor substrate to form a third surface exposing the alignment key and the connection contact, and forming a second circuit on the third surface of the semiconductor substrate such that the second circuit is electrically connected to the connection contact.