Registration Or Layout Process Other Than Color Proofing Patents (Class 430/22)
  • Patent number: 8007959
    Abstract: A photomask includes a transparent substrate having a transparent property against exposing light and a halftone portion formed on the transparent substrate. In the halftone portion, a first opening having a first dimension and a second opening having a second dimension larger than the first dimension are formed. A light-shielding portion is formed on the transparent substrate to be disposed around the second opening.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: August 30, 2011
    Assignee: Panasonic Corporation
    Inventors: Yuji Nonami, Akio Misaka, Shigeo Irie
  • Patent number: 7998641
    Abstract: A photomask includes a transparent substrate having a transparent property against exposing light, a semi-light-shielding portion formed on the transparent substrate, a first opening formed in the semi-light-shielding portion and having a first dimension and a second opening formed in the semi-light-shielding portion and having a second dimension lager than the first dimension. A phase-shifting portion which transmits the exposing light in an opposite phase with respect to the first opening is formed on the transparent substrate around the first opening. A light-shielding portion is formed on the transparent substrate around the second opening.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: August 16, 2011
    Assignee: Panasonic Corporation
    Inventors: Shigeo Irie, Akio Misaka, Yuji Nonami, Tetsuya Nakamura, Chika Harada
  • Patent number: 7999399
    Abstract: An overlay vernier key includes a semiconductor substrate on which a cell region and a scribe lane region are defined, and a plurality of vernier patterns which are formed in the scribe lane region of the semiconductor substrate and arranged in a polygonal shape. Each of the vernier patterns has a hollow polygonal shape.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: August 16, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Byeong Ho Cho, Sung Woo Ko
  • Patent number: 7968258
    Abstract: A method for photolithography in semiconductor manufacturing includes providing one or more masks for a wafer; defining a reference focus plane of a first mask of the one or more masks; defining a reference focus plane of a second mask of the one or more masks; and determining the best focus for the second mask based on the best focus of the first mask and the Z direction difference of the first and second masks, using the reference focus planes of the first and second masks.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: June 28, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Su, Yi-Ming Dai, Chi-Hung Liao, Chun-Hung Kung
  • Patent number: 7952696
    Abstract: An exposure measurement apparatus is configured by including a size measurer measuring respective sizes of at least a pair of transferred patterns having mutually different optimal focus positions out of a plurality of transferred patterns formed by being transferred onto a transfer object, a difference value calculator obtaining a difference value between the size of one transferred pattern and the size of the other transferred pattern, a focus variation amount calculator calculating a focus variation amount of the transfer object using the difference value, and an exposure variation amount calculator calculating an exposure error amount of a wafer.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: May 31, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tomohiko Yamamoto
  • Patent number: 7951512
    Abstract: In order to provide a reticle capable of increasing the number of chips per wafer and of enabling highly accurate alignment, and an exposure method using the reticle, a first alignment mark arrangement region (8) and a second alignment mark arrangement region (9) are provided on both sides of a multi-chip region (2) so that a sum of a size of the first alignment mark arrangement region and a size of the second alignment mark arrangement region is made the same as a size of a chip region (1).
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 31, 2011
    Assignee: Seiko Instruments Inc.
    Inventor: Daisuke Okano
  • Patent number: 7947429
    Abstract: Disclosed is a method for making long flexible circuits. Some of the long circuits may be made using a single photoimaging mask. Also disclosed are flexible circuits made by this method.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: May 24, 2011
    Assignee: 3M Innovative Properties Company
    Inventor: Ronald L. Imken
  • Patent number: 7947433
    Abstract: An exposure method includes the steps of illuminating a mask that has a contact hole pattern using an illumination light, and projecting, via a projection optical system, the contact hole pattern onto a substrate to be exposed, wherein three lights among diffracted lights from the contact hole pattern interfere with each other, wherein said mask is an attenuated phase shift mask, and wherein said illumination light forms a radial polarization illumination.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: May 24, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Miyoko Kawashima
  • Patent number: 7941232
    Abstract: By repeatedly executing a predetermined measurement at set intervals, data on a predetermined performance (a best focus position) of a predetermined apparatus and data on variation factors of the performance are obtained (Steps 204 to 214). Based on the obtained data, multivariate analysis is performed and a model equation that is used to predict a variation amount of the performance and includes at least one of the variation factors as a variable is derived (Step 214). Therefore, after deriving the model equation, a variation amount of the performance can be predicted using the model equation by obtaining data on the variation factor that serves as the variable (Step 238). Accordingly, it becomes possible to maintain the performance described above with good accuracy in accordance with the prediction results and also optimize the implementation timing of maintenance and the like.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: May 10, 2011
    Assignee: Nikon Corporation
    Inventors: Yuuki Ishii, Shinichi Okita
  • Patent number: 7935464
    Abstract: A system and a method for self-aligned dual patterning are described. The system includes a platform for supporting a plurality of process chambers. An etch process chamber coupled to the platform. An ultra-violet radiation photo-resist curing process chamber is also coupled to the platform.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: May 3, 2011
    Assignee: Applied Materials, Inc.
    Inventor: Christopher Siu Wing Ngai
  • Patent number: 7933015
    Abstract: A mark for alignment and overlay, a mask having the same, and a method of using the same are provided. The mark includes a first mark pattern and a second mark pattern. The first mark pattern includes a first pattern and a second pattern, and the second mark pattern includes a third pattern and a fourth pattern. The first pattern includes a plurality of rectangular regions arranged in a first direction, and for each rectangular region, a sideline in a second direction is longer than a sideline in the first direction, wherein the first direction is perpendicular to the second direction. The second pattern is disposed on both sides of the first pattern in the second direction and includes a plurality of rectangular regions arranged in the second direction, and for each rectangular region, the sideline in the first direction is longer than a sideline in the second direction.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: April 26, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Chui-Fu Chiu, Jung-Chih Kuo
  • Patent number: 7927768
    Abstract: A lithography mask is disclosed, comprising an alignment mark, including a first bar, a second bar crossing the first bar, and a specific pattern having different signatures with the first and second bars connecting to the second bar.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: April 19, 2011
    Assignee: VisEra Technologies Company Limited
    Inventors: Chih-Shen Fan, Li-Wei Chen, I-Chin Sung, Fa-Cheng Wang
  • Patent number: 7916276
    Abstract: A device manufacturing method includes a transfer of a pattern from a patterning device onto a substrate. The device manufacturing method further includes transferring a pattern of a main mark to a base layer for forming an alignment mark; depositing a pattern receiving layer on the base layer; in a first lithographic process, aligning, by using the main mark, a first mask that includes a first pattern and a local mark pattern, and transferring the first pattern and the local mark pattern to the pattern receiving layer; aligning, by using the local mark pattern, a second mask including a second pattern relative to the pattern receiving layer; and in a second lithographic process, transferring the second pattern to the pattern receiving layer; the first and second patterns being configured to form an assembled pattern.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: March 29, 2011
    Assignee: ASML Netherlands B.V.
    Inventors: Maurits Van Der Schaar, Richard Johannes Franciscus Van Haren
  • Patent number: 7914958
    Abstract: A semiconductor device manufacturing method has forming a first resist pattern on the semiconductor substrate, and then, forming a first pattern on the semiconductor substrate by the use of the first resist pattern, and forming a second resist pattern on the semiconductor substrate by using an imprinter, and then, forming a second pattern on the semiconductor substrate by the use of the second resist pattern. The forming the first pattern, the first pattern smaller than a design pattern corresponding to the design data for forming a plurality of patterns on a semiconductor substrate being formed.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: March 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryoichi Inanami, Shinji Mikami, Hirofumi Inoue
  • Patent number: 7916284
    Abstract: In a scatterometric method differential targets with different sensitivities to parameters of interest are printed in a calibration matrix and difference spectra obtained. principal component analysis is applied to the difference spectra to obtain a calibration function that is less sensitive to variations in the underlying structure than a calibration function obtained from spectra obtained from a single target.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: March 29, 2011
    Assignee: ASML Netherlands B.V.
    Inventors: Mircea Dusa, Arie Jeffrey Den Boef, Hugo Augustinus Joseph Cramer
  • Patent number: 7911612
    Abstract: An overlay target on a substrate is disclosed, the overlay target including a periodic array of structures wherein every nth structure is different from the rest of the structures. The periodic array is desirably made of two interlaced gratings, one of the gratings having a different pitch from the other grating in order to create an asymmetry in the array. This asymmetry can then be measured by measuring the diffraction spectra of radiation reflected from the overlay target. Variation in the asymmetry indicates the presence of an overlay error in layers on the substrate, where overlay targets are printed on subsequent layers.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: March 22, 2011
    Assignee: ASML Netherlands B.V.
    Inventors: Antoine Gaston Marie Kiers, Arie Jeffrey Den Boef, Maurits Van Der Schaar
  • Patent number: 7906258
    Abstract: In a photomask in which a device pattern, an alignment mark and a superimposition inspection mark are formed on a light transmitting base, each of the alignment mark and the superimposition inspection mark includes a main mark portion, and first and second auxiliary pattern portions. The main mark portion is constituted of one of a space pattern and a line pattern, the pattern having a linear width to be resolved on a photosensitive film formed on a semiconductor wafer, and each of the first and second auxiliary pattern portions includes an auxiliary pattern constituted of one of a repeated pattern of a space pattern and a repeated pattern of a line pattern, the repeated pattern having a linear width not to be resolved on the photosensitive film. The pitch of the repeated pattern is equal to the minimum pitch of the device pattern.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: March 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro Komine, Kazutaka Ishigo, Noriaki Sasaki, Masayuki Hatano
  • Patent number: 7892712
    Abstract: An exposure method suitable for a photolithography process is described. First, a wafer with a group of alignment marks formed thereon is provided. A first alignment step is conducted by using the group of the alignment marks on the wafer to obtain a first calibration data. Next, a second alignment step is conducted by using a portion of the group of alignment marks on the wafer to obtain a second calibration data. The first calibration data is then compared with the second calibration data to obtain a comparison result. Next, a photoresist exposure step is conducted on the wafer according to the comparison result.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: February 22, 2011
    Assignee: Nanya Technology Corporation
    Inventors: Chiang-Lin Shih, Feng-Yi Chen, Kuo-Yao Cho
  • Patent number: 7887997
    Abstract: A manufacturing method for conducting films on two opposite surfaces of a transparent substrate of a touch control circuit, includes: contacting a first photoresist layer having photosensitive and discolored emulsion on a first conducting coat formed on a first surface of the transparent substrate, and contacting a second photoresist layer on a second conducting coat formed on a second surface of the transparent substrate; exposing the first photoresist layer to form a circuit pattern with distinguishable color on exposed regions of the first photoresist layer; employing the circuit pattern as an aligning benchmark for the second photoresist layer, and exposing the second photoresist layer accordingly; developing and etching those arranged on the two surfaces of the transparent substrate at the same time to form a first conducting film of a touch control circuit from the first conducting coat and form a second conducting film of the touch control circuit from the second conducting coat.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: February 15, 2011
    Assignee: TPK Touch Solutions Inc.
    Inventor: Wei-Ping Chou
  • Patent number: 7890203
    Abstract: A wiring forming system comprises: maskless exposure unit which directly exposes an unexposed board by using exposure data generated based on design data relating to an wiring board; post-development inspect unit which tests the board after development, by using the exposure data and the image data of the board exposed and developed by the maskless exposure unit; etching unit which etches the developed board; and post-etching inspect unit which tests an etching pattern formed on the etched board, by using etching inspect data generated based on the design data and the image data of the board etched by the etching unit.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: February 15, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masatoshi Akagawa, Kazunari Sekigawa, Shinichi Wakabayashi
  • Patent number: 7883823
    Abstract: A method of manufacturing a semiconductor device that includes: a first exposing step using a photomask in a first area of a semiconductor substrate; and a second exposing step using the photomask in a second area adjacent to the first area of the semiconductor substrate. The photomask includes a first transmitting pattern having a ring shape that is missing a part, and a supplemental second transmitting pattern having a shape corresponding to the missing part of the first transmitting pattern, so that a closed loop pattern is exposed by the first exposing step and the second exposing step on the semiconductor substrate.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: February 8, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyuki Ishiwata
  • Patent number: 7879514
    Abstract: A lithographic method includes patterning a beam of radiation with a patterning device. The patterning device includes at least two image patterning portions and at least two metrology mark patterning portions. The method also includes projecting at least two image portions of the patterned beam of radiation sequentially onto target portions of a substrate such that the projected image portions are substantially adjacent to each other on the substrate and collectively form a composite image on the substrate. The method also includes projecting a metrology mark onto the substrate outside of the area of the composite image at the same time as projecting each of at least two of the image portions, and measuring the alignment of the metrology marks to determine the relative positions of the at least two image portions.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: February 1, 2011
    Assignee: ASML Netherlands B.V.
    Inventors: Geoffrey Norman Phillipps, Cheng-Qun Gui, Rudy Jan Maria Pellens, Paulus Wilhelmus Leonardus Van Dijk
  • Patent number: 7880152
    Abstract: The invention relates to a device and a method for producing resist profiled elements. According to the invention, an electron beam lithography system is used to produce an electron beam, the axis of the beam being essentially perpendicular to a resist layer in which the resist profiled element is to be produced. The electron beam can be adjusted in terms of the electron surface dose in such a way that a non-orthogonal resist profiled element can be produced as a result of the irradiation by the electron beam.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: February 1, 2011
    Assignees: Giesecke & Devrient GmbH, Vistec Electron Beam GmbH
    Inventors: Wittich Kaule, Rainer Plontke, Ines Stolberg, Andreas Schubert, Marius Dichtl
  • Patent number: 7879515
    Abstract: A method of determining positioning error between lithographically produced integrated circuit patterns on at least two different lithographic levels of a semiconductor wafer comprising. The method includes exposing, developing and etching one or more lithographic levels to create one or more groups of marks comprising a target at one or more wafer locations. The method then includes exposing and developing a subsequent group of marks within the target on a subsequent lithographic level. The method then comprises measuring the position of the marks on each level with respect to a common reference point, and using the measured positions of the groups of marks to determine the relative positioning error between one or more pairs of the developed and etched lithographic levels on which the marks are located.
    Type: Grant
    Filed: January 21, 2008
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Christopher P. Ausschnitt, William A. Muth
  • Patent number: 7876439
    Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: January 25, 2011
    Assignee: International Business Machines Corporation
    Inventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
  • Patent number: 7875409
    Abstract: A method of manufacturing a semiconductor device answerable to refinement of circuits by correctly connecting adjacent small patterns with each other with excellent reproducibility in connective exposure and a semiconductor device manufactured by this method are proposed. According to this method of manufacturing a semiconductor device, connective exposure is performed by dividing a pattern formed on a semiconductor substrate into a plurality of patterns and exposing the plurality of divided patterns in a connective manner, by forming marks for adjusting arrangement of the patterns to be connected with each other on the semiconductor substrate before exposing patterns of a semiconductor element and connectively exposing the patterns of the semiconductor element in coincidence with the marks for adjusting arrangement.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: January 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shinroku Maejima, Seiichiro Shirai, Takahiro Machida
  • Patent number: 7871745
    Abstract: The invention provides an exposure method for manufacturing a device. The method includes providing a wafer having several exposure regions with a photoresist layer covering thereon. A feedback parameter map with several exposure-region feedback parameter sets respectively corresponds to the exposure regions of the wafer. At least one of the exposure-region feedback parameter sets is different from the rest of the exposure-region feedback parameter sets. According to the feedback parameter map, an exposure process is sequentially performed on each of the exposure regions of the wafer through an exposure tool to pattern the photoresist layer on the wafer. While the exposure tool performs the exposure process on each of the exposure regions, an exposure process parameter set of the exposure tool is adjusted based on the exposure-region feedback parameter sets corresponding to the exposure region in the feedback parameter map.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: January 18, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Ju-Te Chen, Wen-Tsung Wu
  • Patent number: 7871744
    Abstract: A near-field exposure apparatus includes a near-field exposure mask and a mechanism places a substrate, to be exposed, opposed to the near-field exposure mask. A mechanism performs relative alignment of the near-field exposure mask and the substrate to be exposed. A mechanism closely contacts the near-field exposure mask and the substrate to be exposed, with each other. A mechanism projects exposure light to the near-field exposure mask, and a soft X-ray irradiating device removes static electricity charged in at least one of the near-field exposure mask and the substrate to be exposed. The soft X-ray irradiating device is disposed such that the near-field exposure mask is located between the soft X-ray irradiating device and the substrate to be exposed.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: January 18, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhisa Inao, Toshiki Ito, Natsuhiko Mizutani
  • Patent number: 7867692
    Abstract: Aspects of the invention can provide a method for manufacturing a microstructure, including forming a photosensitive film above a work piece, exposing the photosensitive film, as a first exposure, by irradiating interference light generated by intersecting two laser beams having a wavelength shorter than a wavelength of visible light, developing the exposed photosensitive film so as to develop a shape corresponding to a pattern of the interference light to the photosensitive film, and etching the work piece using the developed photosensitive film as an etching mask.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: January 11, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Jun Amako, Atsushi Takakuwa, Daisuke Sawaki
  • Patent number: 7862756
    Abstract: A method of making a substantial replica of a first imprint template which bears a first pattern is disclosed. The method includes filling recesses of the first pattern with a first material, removing the first material from the first imprint template to form a second imprint template which bears a second pattern, the second pattern being the substantial inverse of the first pattern, filling recesses of the second pattern with a photo-curable medium, curing the photo-curable medium by illuminating it with radiation, and removing the cured medium from the second imprint template to form a third imprint template which bears a pattern that is a substantial replica of the first pattern.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: January 4, 2011
    Assignee: ASML Netherland B.V.
    Inventors: Sander Frederik Wuister, Johan Frederik Dijksman, Yvonne Wendela Kruijt-Stegeman, Ivar Schram
  • Patent number: 7858404
    Abstract: A method of semiconductor manufacturing including forming an overlay offset measurement target including a first feature on a first layer and a second feature on a second layer. The first feature and the second feature have a first predetermined overlay offset. The target is irradiated. The reflectivity of the irradiated target is determined. An overlay offset for the first layer and the second layer is calculated using the determined reflectivity.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: December 28, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Chih Huang, Chih-Ming Ke, Tsai-Sheng Gau
  • Patent number: 7855035
    Abstract: According to the present invention, provided is a method of manufacturing a electronic device including forming a film over a substrate, performing a photoresist over the film, performing a first exposure by using an exposure mask which includes a scribe region and a inspection mark formed in a first side of the scribe region, and performing a second exposure so that a region that is exposed to the first side in the first exposure is exposed to a second side of the scribe region which is opposite to the first side, wherein, in the second exposure, an exposure light is incident on a region where the inspection mark is projected in the first exposure.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: December 21, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Mitsufumi Naoe
  • Patent number: 7846624
    Abstract: An apparatus and method for the simultaneous determination of focus and source boresighting error for photolithographic steppers and scanners is described. A reticle containing custom arrays of box-in-box test structures specifically designed for performing source or exit pupil division using an aperture plate is exposed onto a resist coated wafer several times. The resulting exposure patterns are measured with a conventional overlay tool. The overlay data is processed with a slope-shift algorithm for the simultaneous determination of both focus and source telecentricity as a function of field position. Additionally, methods for ameliorating metrology induced effects and methods for producing precision Bossung curves are also described. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules, it shall not be used to interpret or to limit the scope or the meaning of the claims.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: December 7, 2010
    Assignee: Litel Instruments
    Inventors: Adlai H. Smith, Robert O. Hunter, Jr.
  • Patent number: 7842933
    Abstract: A system and method for detecting overlay errors, the method includes (i) directing a primary electron beam to interact with an inspected object; whereas the inspected object comprises a first feature formed on a first layer of the inspected object and a second feature formed on a second layer of the object, wherein the second feature is buried under the first layer and wherein the second feature affects a shape of an area of the first layer; (ii) detecting electrons reflected or scattered from the area of the first layer; and (iii) receiving detection signals from at least one detector and determining overlay errors.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: November 30, 2010
    Assignee: Applied Materials Israel, Ltd.
    Inventors: Dimitry Shur, Alexander Kadyshevitch
  • Patent number: 7842442
    Abstract: By taking into consideration tool-specific distortion signatures and reticle-specific placement characteristics in an alignment control system, the control quality of sophisticated APC strategies may be significantly enhanced. Respective correction data may be established on the basis of any combinations of tool/reticles and layers to be aligned to each other, which may modify the respective target values of alignment parameters used for controlling the alignment process on the basis of standard overlay measurement data obtained from dedicated overlay marks.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: November 30, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rolf Seltmann, Bernd Schulz, Fritjof Hempel, Uwe Schulze
  • Patent number: 7816060
    Abstract: A manufacturing method of a semiconductor device including a pattern forming method, a reticle correcting method, and a reticle pattern data correcting method are disclosed.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: October 19, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroko Nakamura
  • Patent number: 7807322
    Abstract: A photomask for double exposure, and a double exposure method using the same are disclosed. The photomask for double exposure comprises a mask substrate divided into first and second regions equally arranged to upper and lower sides on different sides, respectively, a first mask pattern formed on the first region of the mask substrate, and a second mask pattern formed on the second region of the mask substrate. The photomask and the double exposure method using the same enable a finer photoresist pattern to be formed on a semiconductor wafer, while minimizing reduction in yield and productivity due to misalignment and replacement.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: October 5, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chan Ha Park
  • Patent number: 7807320
    Abstract: A target and method for use in polarized light lithography. A preferred embodiment comprises a first structure located on a reference layer, wherein the first structure is visible through a second layer, and a second structure located on the second layer, wherein the second structure is formed from a photomask containing a plurality of sub-structures oriented in a first orientation, wherein a polarized light is used to pattern the second structure onto the second layer, and wherein a polarization of the polarized light is the same as the orientation of the plurality of sub-structures. The position, size, and shape of the second structure is dependent upon a polarity of the polarized light, permitting a single design for an overlay target to be used with different polarities of polarized light.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: October 5, 2010
    Assignee: Infineon Technologies AG
    Inventor: Sajan Marokkey
  • Publication number: 20100248098
    Abstract: An image forming apparatus is provided. An exposure component is equipped with a plurality of light emitting elements arrayed along a first direction. An output component is equipped with output ends corresponding to each of the light emitting elements and the output component, when correcting an amount of misalignment in the first direction, outputs drive signals of one line corresponding to a line on a most upstream side of drive signals of plural lines from the output ends that have been shifted by a number corresponding to the amount of misalignment in the first direction. A plurality of connecting wires interconnect each of the output ends and each of the light emitting elements. A judging component is connected to each of the connecting wires, and judges whether or not the drive signals are being normally transmitted through the connecting wire that the judging component has selected.
    Type: Application
    Filed: September 23, 2009
    Publication date: September 30, 2010
    Applicant: FUJI XEROX CO., LTD
    Inventors: Hayato YOSHIKAWA, Yasuhiro Arai, Masaki Fujise, Kenji Koizumi
  • Patent number: 7803500
    Abstract: A photomask capable of preventing a pattern outside a chip region from being transferred onto a wafer. A non-circuit pattern (a monitor pattern for measuring the accuracy of the position of a mask pattern, for example) formed by making openings in which a phase shift layer is exposed only in a light shielding layer is located around the chip region where the light shielding layer is removed and where the phase shift layer in which openings corresponding to circuit patterns are made is exposed. This prevents the non-circuit pattern from being transferred onto the wafer by the influence of a flare.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: September 28, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyuki Ishiwata
  • Patent number: 7804584
    Abstract: Methods of manufacturing an integrated circuit by a lithographic apparatus are disclosed. The methods include patterning a radiation beam with a patterning device, projecting the patterned beam onto a substrate using a projection system, and determining the position of the patterning device. In one example, the patterning device's position relative to the projection system is determined by measuring the position of the patterning device's support structure. In another example, the position can be determined by measuring a position of the patterning device relative to its support and by measuring a position of the support. In another example, a Z-position of the patterning device is determined by directing at least one beam of radiation onto a part of the patterning device located outside a pattern area. This can be done by directing a pair of laser beams from sensors on the projection system to reflecting strips on the patterning device.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: September 28, 2010
    Assignee: ASML Netherland B.V.
    Inventors: Petrus Rutgerus Bartray, Wilhelmus Josephus Box, Dominicus Jacobus Petrus Adrianus Franken, Bernardus Antonius Johannes Luttikhuis, Engelbertus Antonius Franciscus Van Der Pasch, Marc Wilhelmus Maria Van Der Wijst, Marc Johannes Martinus Engels
  • Patent number: 7804994
    Abstract: An overlay method for determining the overlay error of a device structure formed during semiconductor processing is disclosed. The overlay method includes producing calibration data that contains overlay information relating the overlay error of a first target at a first location to the overlay error of a second target at a second location for a given set of process conditions. The overlay method also includes producing production data that contains overlay information associated with a production target formed with the device structure. The overlay method further includes correcting the overlay error of the production target based on the calibration data.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: September 28, 2010
    Assignee: KLA-Tencor Technologies Corporation
    Inventors: Michael Adel, Mark Ghinovker, Elyakim Kassel, Boris Golovanevsky, John C. Robinson, Chris A. Mack, Jorge Poplawski, Pavel Izikson, Moshe Preil
  • Patent number: 7800084
    Abstract: A charged-particle beam lithography system is provided. A region to be patterned is divided into plural frames, a main deflection positions a beam to a subfield within the frame, and an auxiliary deflection draws a pattern in units of subfield. The deflection control portion draws a pattern in units of stripe including a first frame drawing region and a second frame drawing region. The first frame drawing region corresponds to one of the frames, and the second frame drawing region is a region moved by a distance C from the first frame drawing region toward a frame to be drawn next. The deflection control portion controls the driver to alternately pattern a first sub-field drawing region in the first frame drawing region and a second sub-field drawing region in the second frame drawing region. The distance C satisfies 0<C<Ws. Ws is a width of the subfield.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: September 21, 2010
    Assignee: NuFlare Technology, Inc.
    Inventor: Shuichi Tamamushi
  • Patent number: 7790336
    Abstract: A method for joining a plurality of reticles is used for producing a semiconductor layout pattern, so that the reticles will collectively map a circuit arrangement on a semiconductor substrate. A plurality of matching patterns is provided that are each geometrically linked to a respective particular reticle and through detecting pairwise correspondence among the matching patterns likewise correspondence among the associated reticles is ascertained. In particular, the method has bulk sub-reticles and peripheral sub-reticles, and a first matching pattern associates to a peripheral sub-reticle that abuts a bulk sub-reticle and a second matching pattern to the bulk sub-reticle at such distance therefrom that fitting of the peripheral sub-reticle between the second matching pattern and the bulk sub-reticle allows matching of the first and second matching patterns. The bulk sub-reticles are used to constitute an array of sub-reticles.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: September 7, 2010
    Assignee: DALSA Corporation
    Inventor: Daniel Wilhelmus Elisabeth Verbugt
  • Patent number: 7790480
    Abstract: A process (300) is disclosed to measure predetermined wavelength reflectance spectra of a photo resist coated wafer (305,310,315,320) at a nominal thickness. After coating, the predetermined wavelength reflectance (325,330) is measured and the peak heights and valleys in the vicinity of the predetermined wavelength are tabulated. The relative swing ratio is computed (335) as the average peak height of the spectra at the exposure wavelength. This relative swing ratio is then compared to similar computations on other processes to determine which provides the best critical dimension (CD) control.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: September 7, 2010
    Assignee: NXP B.V.
    Inventor: David Ziger
  • Patent number: 7771905
    Abstract: A method for calculating an offset of an exposure dose and a focus position in an exposure apparatus that exposes a substrate via an original includes the steps of obtaining information of a shape of a pattern formed on the substrate using the exposure apparatus, calculating a shift amount between a critical dimension contained in the information of the shape of the pattern and a reference value of the critical dimension, and calculating an offset of the focus position based on the information of the shape of the pattern, and calculating the offset of the exposure dose based on the shift amount and the offset of the focus position.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: August 10, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koichi Sentoku, Hideki Ina, Koji Mikami, Yoshiaki Sugimura, Hiroto Yoshii, Tomoyuki Miyashita
  • Patent number: 7771897
    Abstract: A method includes; a step of setting square mask cells in rows and columns on a transparent mask-substrate surface by demarcating by orthogonal lines of equal intervals, each of which has one side having a length smaller than a resolution limit of an optical system; a step of setting the resist thicknesses corresponding to the mask cells; a step of assigning normalized light-intensities respectively to the mask cells as transmission intensities, corresponding to the film thicknesses and having three or more different values; a step of setting each of the mask cells a light-transmission area and a shade-area and determining a transmission-light intensity by an transmission area ratio; a step of providing shade films on the shade areas of the mask substrate.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: August 10, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Takamitsu Furukawa
  • Patent number: 7761984
    Abstract: A multi-layer printed wiring board includes a board covered with a conductor layer, an interlayer insulating resin layer, an etched metal film on the interlayer insulating resin layer, and a via hole. The interlayer insulating resin layer has a fibrous substrate. The via hole has an electrolytic plated film and an electrolessly plated film and connects the conductor layer of the board and the etched metal film.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: July 27, 2010
    Assignee: IBIDEN Co., Ltd.
    Inventors: Yasuji Hiramatsu, Motoo Asai, Naohiro Hirose, Takashi Kariya
  • Patent number: 7763397
    Abstract: Provided are photomask registration errors of which have been corrected and a method of correcting the registration errors of a photomask. The photomask includes a photomask substrate, an optical pattern formed on one surface of the photomask substrate, and a plurality of stress generation portions formed in the photomask substrate. A method of correcting the registration errors of a photomask includes the steps of forming an optical pattern on a photomask substrate, measuring the registration errors of the optical pattern, and forming a plurality of stress generation portions in the photomask substrate so that the stress generation portions correspond to the measured registration errors.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: July 27, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-Soo Lee, Suk-Jong Bae, Jung-Hoon Lee, Seong-Woo Choi, Byung-Gook Kim
  • Patent number: 7763403
    Abstract: A system and method are provided for determining an overlay of a first layer N?1 and a second layer N that are positioned one over the other on a substrate. The first layer includes a first overlay portion. The second layer includes a first complementary overlay portion. The first overlay portion and first complementary overlay portion are arranged to form an overlay mark for determining the overlay of the first and second layers. In the second layer a stitching portion and a complementary stitching portion are formed. The stitching portion and complementary stitching portion are arranged to form a stitching mark for determining a stitching overlay between the second layer and an adjacent second layer, with the adjacent second layer being positioned adjacent to the second layer.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: July 27, 2010
    Assignee: ASML Netherlands B.V.
    Inventor: Franciscus Bernardus Maria Van Bilsen