Including Multiple Resist Image Formation Patents (Class 430/312)
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Patent number: 8697339Abstract: Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. A polymer material is disposed over the masking material. The masking material and the polymer layer are used to pattern the material layer of the workpiece.Type: GrantFiled: April 6, 2011Date of Patent: April 15, 2014Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd., Infineon Technologies AGInventors: Haoren Zhuang, Chong Kwang Chang, Alois Gutmann, Jingyu Lian, Matthias Lipinski, Len Yuan Tsou, Helen Wang
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Patent number: 8691495Abstract: A photoresist pattern forming method, comprising a first step of forming on an underlayer a photoresist film which includes a convex portion and a concave portion having a thickness thinner than a thickness of the convex portion, and a second step of processing the photoresist film to form, in a portion which has been the convex portion, an opening having a width narrower than a width of the convex portion, wherein in the second step, the convex portion of the photoresist film is at least partially exposed, and the photoresist film is then developed, and exposure light is condensed by the convex portion in exposing the photoresist film.Type: GrantFiled: August 24, 2012Date of Patent: April 8, 2014Assignee: Canon Kabushiki KaishaInventors: Kousei Uehira, Satoshi Hirayama
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Patent number: 8685615Abstract: A resist underlayer film forming composition used in a lithography process includes: a polymer (A) containing a unit structure having a hydroxy group, a unit structure having a carboxy group, or combination thereof; a crosslinkable compound (B) having at least two vinyl ether groups; a photoacid generator (C); a C4-20 fluoroalkylcarboxylic acid or a salt of the fluoroalkylcarboxylic acid (D); and a solvent (E).Type: GrantFiled: June 17, 2010Date of Patent: April 1, 2014Assignee: Nissan Chemical Industries, Ltd.Inventors: Shigeo Kimura, Hirokazu Nishimaki, Tomoya Ohashi, Yuki Usui, Takahiro Kishioka
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Patent number: 8685633Abstract: A method of printing an image on a wafer. The method includes the steps of printing a main image, wherein the main image includes fields which are fully on the wafer, and printing an alternate image, wherein the alternate image includes fields which are only partially on the wafer. The alternate image could be placed on a separate mask which is loaded onto the exposure tool after the mask with the main image has completed printing. Alternatively, it could be an extra image specially inserted on the mask with the main image for that layer.Type: GrantFiled: August 30, 2004Date of Patent: April 1, 2014Assignee: LSI CorporationInventors: Duane B. Barber, David J. Sturtevant
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Publication number: 20140080066Abstract: A double patterning method includes providing a first resist film on a substrate using a first photoresist composition. The first resist film is exposed. The exposed first resist film is developed using a first developer to form a first resist pattern. A second resist film is provided in at least space areas of the first resist pattern using a second photoresist composition. The second resist film is exposed. The exposed second resist film is developed using a second developer that includes an organic solvent to form a second resist pattern. The first resist pattern is insoluble or scarcely soluble in the second developer.Type: ApplicationFiled: October 22, 2013Publication date: March 20, 2014Applicant: JSR CORPORATIONInventors: Kanako MEYA, Takeo SHIOYA, Motoyuki SHIMA
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Publication number: 20140065552Abstract: A method for forming a pattern on a substrate is described. The method includes providing a substrate, forming a photosensitive layer over the substrate, exposing the photosensitive layer to a first exposure energy through a first mask, exposing the photosensitive layer to a second exposure energy through a second mask, baking the photosensitive layer, and developing the exposed photosensitive layer. The photosensitive layer includes a polymer that turns soluble to a developer solution, at least one photo-acid generator (PAG), and at least one photo-base generator (PBG). A portion of the layer exposed to the second exposure energy overlaps with a portion exposed to the first exposure energy.Type: ApplicationFiled: November 18, 2013Publication date: March 6, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Hui Chang, Chia-Chu Liu
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Publication number: 20140054073Abstract: The present invention relates to a method for forming solder resist and a substrate for a package. The method for forming solder resist including: forming a first solder resist inner region by primarily coating, exposing, and developing a solder resist on a substrate on which an outer PoP pad and an inner chip pad are formed, and removing the solder resist's outer portion on the substrate's outer region and curing the solder resist's inner portion on the substrate's inner region; forming a plugged SR region which does not expose the substrate; changing a surface roughness by performing a desmear process on a surface of the first solder resist inner region in which the plugged SR region is formed; and forming a second solder resist SMD region which covers an edge of the PoP pad, exposing, and developing the solder resist on the substrate after the desmear process is provided.Type: ApplicationFiled: August 27, 2013Publication date: February 27, 2014Applicant: Samsung Electro-Mechannics Co., LtdInventors: Chang Bo LEE, Chang Sup RYU, Hyo Bin PARK, Cheol Ho CHOI
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Patent number: 8658346Abstract: A pattern is formed by (1) coating a first positive resist composition onto a substrate, baking, patternwise exposing, PEB, and developing to form a first positive resist pattern including a large area feature, (2) applying a resist-modifying composition comprising a basic nitrogen-containing compound and heating to modify the first resist pattern, and (3) coating a second positive resist composition thereon, patternwise exposing, and developing to form a second resist pattern. The large area feature in the first resist pattern has a film retentivity of at least 50% after the second pattern formation.Type: GrantFiled: August 4, 2010Date of Patent: February 25, 2014Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Takeru Watanabe, Tsunehiro Nishi, Masashi Iio
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Patent number: 8652764Abstract: A substrate 20 is prepared. “A piezoelectric material layer 32a which has not been fired” and which will become a piezoelectric membrane is formed above a first principal surface 20a of the substrate 20. A first mask 131 is formed above the piezoelectric material layer 32a. “The piezoelectric material layer 32a existing within a portion where the first mask 131 does not exist” is eliminated by injecting a blast media including at least one of abrasive grains or an organic solvent onto the first principal surface 20a of the substrate 20. Thereafter, the first mask 131 is eliminated, and the piezoelectric material layer 32a is fired. The substrate has a hollow portion, however, it does not necessarily have the hollow portion.Type: GrantFiled: March 31, 2011Date of Patent: February 18, 2014Assignee: NGK Insulators, Ltd.Inventors: Hideki Shimizu, Mutsumi Kitagawa
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Publication number: 20140034209Abstract: A phase difference layer laminated body used in a three-dimensional liquid crystal display device, wherein unit cells are divided into groups for left and right eyes, which are given different degrees of polarization, thereby creating a three-dimensional image, further wherein the phase difference layer laminated body has a base material having orientability, and a phase difference layer made of a liquid crystal material that can form a nematic phase and formed in a pattern with two different portions, and the liquid crystal material in each of two different portions is oriented to have different refractive index anisotropy each other that conforms to the two different degrees of polarization and fixed as it is.Type: ApplicationFiled: October 11, 2013Publication date: February 6, 2014Applicant: DAI NIPPON PRINTING CO., LTD.Inventor: Keiji KASHIMA
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Publication number: 20140034359Abstract: Disclosed herein is a printed circuit board including a base substrate, a photosensitive insulating layer formed on an upper portion of the base substrate, and a circuit pattern formed to be buried within the photosensitive insulating film.Type: ApplicationFiled: August 2, 2013Publication date: February 6, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jeong Woo Lee, Going Sik Kim
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Publication number: 20140017772Abstract: A biosensor includes a flexible foil with an electrode layer positioned on the foil. An adhesive layer is positioned on the foil layer, and a first photo-definable hydrogel membrane is positioned over the electrode layer and the adhesive layer. A second photo-definable hydrogel membrane with an immobilized bio-recognition element is positioned over the first hydrogel membrane in contact with the electrode layer through an opening in the first hydrogel membrane.Type: ApplicationFiled: June 27, 2013Publication date: January 16, 2014Inventors: Andrea Di Matteo, Vincenza Di Palma, Maria Fortuna Bevilacqua, Angela Cimmino
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Patent number: 8623458Abstract: A layered structure comprising a self-assembled material is formed by a method that includes forming a photochemically, thermally and/or chemically treated patterned photoresist layer disposed on a first surface of a substrate. The treated patterned photoresist layer comprises a non-crosslinked treated photoresist. An orientation control material is cast on the treated patterned photoresist layer, forming a layer containing orientation control material bound to a second surface of the substrate. The treated photoresist and, optionally, any non-bound orientation control material are removed by a development process, resulting in a pre-pattern for self-assembly. A material capable of self-assembly is cast on the pre-pattern. The casted material is allowed to self-assemble with optional heating and/or annealing to produce the layered structure.Type: GrantFiled: December 18, 2009Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Joy Cheng, Matthew E. Colburn, Stefan Harrer, William D. Hinsberg, Steven J. Holmes, Ho-Cheol Kim, Daniel Paul Sanders
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Publication number: 20140001475Abstract: A manufacturing method of the array substrate includes the steps: A. A first mask manufacturing process is adopted to from scan lines and thin film transistor (TFT) gates on a surface of a substrate. B. A second mask manufacturing process is adopted to form scan lines and data lines of the array substrate, a source electrode and a drain electrode of TFT and a conducting channel positioned between the source electrode and the drain electrode. C. A photoresistor formed in the second mask manufacturing process is incinerated, and then, an a-Si film is paved on the surface of the array substrate. D. The photoresistor is stripped to form an undoped active layer. E. A third mask manufacturing process is adopted to form a transparent conducting layer on the surface of the drain electrode of the TFT. Only three mask manufacturing process in the present disclosure are needed to manufacture the entire array substrate.Type: ApplicationFiled: July 12, 2012Publication date: January 2, 2014Inventor: Jun Wang
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Patent number: 8617797Abstract: A method for manufacturing a semiconductor device that includes a plurality of gate patterns in parallel with each other within one circuit block provided over a semiconductor substrate includes preparing a first photomask, performing a first photolithography process upon a photoresist layer within a circuit block by using the first photomask, preparing a second photomask that includes a trim photomask having at least one trim opening corresponding to a dummy gate pattern to remove a portion of the photoresist layer corresponding to the dummy gate pattern, and performing a second photolithography process upon the photoresist layer by using the second photomask.Type: GrantFiled: May 31, 2012Date of Patent: December 31, 2013Assignee: Renesas Electronics CorporationInventor: Masashi Fujimoto
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Patent number: 8617653Abstract: It is disclosed an over-coating agent for forming fine patterns which is applied to cover a substrate having photoresist patterns thereon and allowed to shrink under heat so that the spacing between adjacent photoresist patterns is lessened, with the applied film of the over-coating agent being removed to form fine patterns, further characterized by comprising a water-soluble polymer which contains a monomeric component and a dimeric component, wherein the total content of the monomeric component and the dimeric component in the water-soluble polymer is reduced to 10 mass % or less, and a method of forming fine patterns using the same. By the present invention, even in reducing the pattern size on a substrate having thereon patterns having different pitches, the heat shrinkage of the over-coating agent can be controlled, irrespective whether the pitch is dense or isolate, thus achieving the pattern size reduction.Type: GrantFiled: September 20, 2010Date of Patent: December 31, 2013Assignee: Tokyo Ohka Okgyo Co., Ltd.Inventors: Tsunehiro Watanabe, Toshiki Takedutsumi, Masanori Yagishita, Kiyofumi Mitome, Takahito Imai, Masatoshi Hashimoto, Masaji Uetsuka
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Patent number: 8603732Abstract: There is disclosed a resist underlayer film-forming composition comprising, at least: a resin (A) obtained by condensing a compound represented by the following general formula (1) with a compound represented by the following general formula (2) by the aid of an acid catalyst; a compound (B) represented by the general formula (1); a fullerene compound (C); and an organic solvent. There can be a resist underlayer film composition in a multi-layer resist film to be used in lithography, which underlayer film is excellent in property for filling up a height difference of a substrate, possesses a solvent resistance, and is not only capable of preventing occurrence of twisting during etching of a substrate, but also capable of providing an excellently decreased pattern roughness; a process for forming a resist underlayer film by using the composition; and a patterning process.Type: GrantFiled: December 27, 2010Date of Patent: December 10, 2013Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Tsutomu Ogihara, Takeru Watanabe, Takeshi Kinsho, Katsuya Takemura, Toshihiko Fujii, Daisuke Kori
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Publication number: 20130323924Abstract: Methods of forming a pattern in a material and methods of forming openings in a material to be patterned are disclosed, such as a method that includes exposing first portions of a first material to radiation through at least two apertures of a mask arranged over the first material, shifting the mask so that the at least two apertures overlap a portion of the first portions of the first material, and exposing second portions of the first material to radiation through the at least two apertures. The first portions and the second portions will overlap in such a way that non-exposed portions of the first material are arranged between the first portions and second portions. The non-exposed or exposed portions of the first material may then be removed. The remaining first material may be used as a photoresist mask to form vias in an integrated circuit. The pattern of vias produced have the capability to exceed the current imaging resolution of a single exposure treatment.Type: ApplicationFiled: August 9, 2013Publication date: December 5, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Anton DeVilliers, Michael Hyatt
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Patent number: 8574971Abstract: An approach for patterning and etching without a mask is provided in a manufacturing a thin-film transistor, a gate electrode, a gate insulating layer, a semiconductor layer, an ohmic contact layer and source metal layer of a substrate. A first photoresist pattern including a first photo pattern and a second photo pattern is formed using a digital exposure device by generating a plurality of spot beams, the first photo pattern is formed to a first region of the base substrate and has a first thickness, and the second photo pattern is formed to a second region adjacent to the first region, and has a second thickness and a width in a range of about 50% to about 60% of a diameter of the spot beam. The source metal layer is patterned to form a source electrode and a drain electrode, and the source electrode and the drain electrode are spaced apart from each other in the first region of an active pattern.Type: GrantFiled: October 8, 2010Date of Patent: November 5, 2013Assignee: Samsung Display Co., Ltd.Inventors: Sang-Hyun Yun, Cha-Dong Kim, Jung-In Park, Hi-Kuk Lee
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Patent number: 8563410Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.Type: GrantFiled: November 25, 2009Date of Patent: October 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Te S. Lin, Meng Jun Wang, Ya Hui Chang, Hui Ouyang
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Patent number: 8563202Abstract: A method for stitching a first field mask to a second field mask on a wafer includes providing a photomask with a first set of targets and a second set of targets, printing images of the first set of targets and the second set of targets onto the wafer where the photomask is applied to the wafer having no previous alignment marks formed thereon for the photomask to align to. A first set of alignment marks is formed from the first set of targets and a second set of alignment marks is formed from the second set of targets. The method includes aligning a first field mask to the first set of alignment marks and aligning a second field mask to the second set of alignment marks. The images of the first field mask and the second field mask are thereby stitched together on the wafer.Type: GrantFiled: April 17, 2013Date of Patent: October 22, 2013Assignee: Micrel, Inc.Inventor: Arthur Lam
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Patent number: 8563226Abstract: The invention relates to a method (3) of fabricating a mold (39, 39?) including the following steps: (a) depositing (9) an electrically conductive layer on the top (20) and bottom (22) of a wafer (21) made of silicon-based material; (b) securing (13) the wafer to a substrate (23) using an adhesive layer; (c) removing (15) one part (26) of the conductive layer from the top of the wafer (21); and (d) etching (17) the wafer as far as the bottom conductive layer (22) thereof in the shape (26) of the one part removed from the top conductive layer (22) to form at least one cavity (25) in the mold. The invention concerns the field of micromechanical parts, particularly, for timepiece movements.Type: GrantFiled: March 12, 2010Date of Patent: October 22, 2013Assignee: Nivarox-FAR S.A.Inventors: Pierre Cusin, Clare Golfier, Jean-Philippe Thiebaud
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Publication number: 20130271675Abstract: A conductive connection part (33) electrically connecting a conductive pattern (17) in a touch region (T1) to a lead line (30) includes a first connection layer (34A) formed below an interlayer insulating film (23) and connected so as to overlap with a base end part (30s) of the lead line (30), and a second connection layer (34B) connected to the first connection layer (34A) and crossing over a peripheral line (32) with the interlayer insulating film (23) being interposed between the second connection layer (34B) and the peripheral line (32).Type: ApplicationFiled: December 21, 2011Publication date: October 17, 2013Applicant: SHARP KABUSHIKI KAISHAInventor: Katsunori Misaki
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Publication number: 20130249863Abstract: An internal connecting terminal (33) includes a first interconnect layer (34A) formed of a same film as a first conductive pattern for touch position detection under an interlayer insulating film (23), and a second interconnect layer (34B) formed of a same film as a second conductive pattern for touch position detection on the interlayer insulating film (23). The first and the second interconnect layers are electrically connected to a lead line (31) at a portion overlapping the lead line (31), and electrically connected together at a portion outside the lead line (31).Type: ApplicationFiled: December 2, 2011Publication date: September 26, 2013Applicant: SHARP KABUSHIKI KAISHAInventor: Katsunori Misaki
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Publication number: 20130252174Abstract: A method for forming fine patterns of a semiconductor device employs a double patterning characteristic using a mask for forming a first pattern including a line pattern and a mask for separating the line pattern, and a reflow characteristic of a photoresist pattern.Type: ApplicationFiled: May 15, 2013Publication date: September 26, 2013Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Jae Seung Choi
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Patent number: 8535858Abstract: The present invention relates to a photomask and a method for forming an overlay mark in a substrate using the same. The photomask comprises a plurality of patterns. At least one of the patterns comprises a plurality of ring areas and a plurality of inner areas enclosed by the ring areas, wherein the light transmittancy of the ring areas is different from that of the inner areas. When the photomask is applied in a photolithography process, the formed overlay mark has a large thickness. Therefore, the contrast is high when a metrology process is performed, and it is easy to find the overlay mark.Type: GrantFiled: February 25, 2013Date of Patent: September 17, 2013Assignee: Nanya Technology Corp.Inventor: Chui Fu Chiu
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Publication number: 20130234302Abstract: A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A positive photoresist layer is formed on a negative photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist layer and to form a second exposure region in the negative photoresist layer in response to a first and a second intensity thresholds of the exposure energy. A positive-tone development process is performed to remove the first exposure region from the positive photoresist layer to form first opening(s). The second exposure region in the negative photoresist layer is then etched along the first opening(s) to form second opening(s) therein. A negative-tone development process is performed to remove portions of the negative photoresist layer outside of remaining second exposure region to form a double patterned negative photoresist layer.Type: ApplicationFiled: March 7, 2013Publication date: September 12, 2013Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.Inventor: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.
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Publication number: 20130234294Abstract: A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A negative photoresist layer is formed on a positive photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist layer and to form a second exposure region in the negative photoresist layer in response to a first and a second intensity thresholds of the exposure energy. A negative-tone development process is performed to remove portions of the negative photoresist layer to form first opening(s). The positive photoresist layer is then etched along the first opening(s) to form second opening(s) therein. A positive-tone development process is performed to remove the first exposure region therefrom to form a double patterned positive photoresist layer.Type: ApplicationFiled: March 7, 2013Publication date: September 12, 2013Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.Inventors: DANIEL HU, KEN WU, YIMING GU
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Patent number: 8530145Abstract: In an exposure step, a combination of a first photomask and a second mask is used. The first mask has a real pattern corresponding to the pattern actually formed on the film to be processed, and a dummy pattern added for controlling pattern pitch in the first photomask within a prescribed range; and the second photomask has a pattern isolating a real-pattern-formed region from a dummy-pattern-formed region. In forming the pattern, after forming a film to be processed on a substrate, a first mask is formed on the film to be processed,by lithography, using the first photomask, and a second mask is formed on the film to be processed, by lithography, using the second photomask. Thereafter, the film to be processed is etched and removed using the first and second masks as masks to form the pattern.Type: GrantFiled: December 28, 2010Date of Patent: September 10, 2013Assignee: Renesas Electronics CorporationInventor: Takuya Hagiwara
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Publication number: 20130224664Abstract: A solid-state image sensor is manufactured through a plurality of photolithography processes. The plurality of photolithography processes includes at least one first lithography process including a dividing exposure step of exposing a substrate using a plurality of photomasks, and at least one second lithography process including a non-dividing exposure step of exposing the substrate using one photomask. The at least one first lithography process includes a process for forming a resist pattern to define active regions on the substrate, and a process for forming a resist pattern to define charge accumulation region.Type: ApplicationFiled: February 21, 2013Publication date: August 29, 2013Applicant: CANON KABUSHIKI KAISHAInventor: CANON KABUSHIKI KAISHA
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Patent number: 8518632Abstract: In a method of manufacturing an electroforming mold, a first photoresist layer is formed on an upper surface of a bottom conductive film of a substrate, and the first photoresist layer is divided into a first soluble portion and a first insoluble portion. A conductive material is thermally deposited on an upper surface of the first photoresist layer within a predetermined temperature range, to thereby form an intermediate conductive film. An intermediate conductive film is patterned. A second photoresist layer is formed on an exposed upper surface of the first photoresist layer after the intermediate conductive film is removed, and on an upper surface of the intermediate conductive film remaining after patterning. The second photoresist layer is divided into a second soluble portion and a second insoluble portion. Next, the first and second photoresist layers are developed, and the first and second soluble portions are removed.Type: GrantFiled: July 10, 2007Date of Patent: August 27, 2013Assignee: Seiko Instruments Inc.Inventors: Takashi Niwa, Matsuo Kishi, Koichiro Jujo, Hiroyuki Hoshina
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Patent number: 8507173Abstract: A pattern is formed by applying a first positive resist composition onto a substrate, heat treatment, exposure, heat treatment and development to form a first resist pattern; causing the first resist pattern to crosslink and cure by irradiation of high-energy radiation of 200-320 nm wavelength; further applying a second positive resist composition onto the substrate, heat treatment, exposure, heat treatment and development to form a second resist pattern. The double patterning process reduces the pitch between patterns to one half.Type: GrantFiled: December 8, 2009Date of Patent: August 13, 2013Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Jun Hatakeyama, Kazuhiro Katayama
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Patent number: 8507185Abstract: Methods of forming electronic devices are provided. The methods involve alkaline treatment of photoresist patterns and allow for the formation of high density resist patterns. The methods find particular applicability in semiconductor device manufacture.Type: GrantFiled: June 28, 2010Date of Patent: August 13, 2013Assignee: Rohm and Haas Electronic Materials LLCInventors: Young Cheol Bae, Thomas Cardolaccia, Yi Liu
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Patent number: 8507187Abstract: A first photoresist is applied over an optically dense layer and lithographically patterned to form an array of first photoresist portions having a pitch near twice a minimum feature size. The pattern in the first photoresist portions, or a first pattern, is transferred into the ARC layer and partly into the optically dense layer. A second photoresist is applied and patterned into another array having a pitch near twice the minimum feature size and interlaced with the first pattern. The pattern in the second photoresist, or a second pattern, is transferred through the ARC portions and partly into the optically dense layer. The ARC portions are patterned with a composite pattern including the first pattern and the second pattern. The composite pattern is transferred through the optically dense layer and into the underlayer to form a sublithographic pattern in the underlayer.Type: GrantFiled: July 9, 2008Date of Patent: August 13, 2013Assignees: International Business Machines Corporation, Freescale Semiconductor, Inc.Inventors: Veeraraghavan S. Basker, Willard E. Conley, Steven J. Holmes, David V. Horak
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Patent number: 8507184Abstract: Disclosed herein is a method of manufacturing a semiconductor device that includes: performing a first exposure process with a first exposure mask having a first space pattern formed in a first direction; performing a second exposure process with a second exposure mask different from the first exposure mask, the second exposure mask having a second space pattern formed in a second direction intersected with the first direction; and forming a contact hole by a developing process.Type: GrantFiled: June 27, 2008Date of Patent: August 13, 2013Assignee: SK hynix Inc.Inventor: Sang Man Bae
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Patent number: 8497060Abstract: A manufacturing method includes forming a stacked film including first/second/third layers on a substrate, forming a first resist pattern on the stacked film, forming a first film pattern by etching the first layer through the first resist pattern, removing the first resist pattern, partially covering the first film pattern with a second resist pattern, slimming the first film pattern exposed from the second resist pattern, forming a second film pattern by etching the second layer exposed from the first layer through the first film pattern, partially covering the second film pattern with a third resist pattern, removing the first film pattern exposed from the third resist pattern, forming sidewall spacers to the second film pattern and remained second layer, removing the remained second layer portion, followed by etching the third layer through the second film pattern and sidewall spacers to form a third film pattern.Type: GrantFiled: May 11, 2010Date of Patent: July 30, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Koji Hashimoto
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Patent number: 8492075Abstract: Methods of forming electronic devices are provided. The methods involve alkaline treatment of photoresist patterns and allow for the formation of high density resist patterns. The methods find particular applicability in semiconductor device manufacture.Type: GrantFiled: June 28, 2010Date of Patent: July 23, 2013Assignee: Rohm and Haas Electronic Materials LLCInventors: Young Cheol Bae, Thomas Cardolaccia, Yi Liu
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Patent number: 8492072Abstract: A description is given of methods and devices for product marking of objects using a light-sensitive layer applied to the objects and a light source. The invention may be used, for example, to simultaneously mark or label a first plurality of objects at a first time with individual marks or labels, and to mark or label a second plurality of objects at a second time with individual marks or labels.Type: GrantFiled: April 30, 2009Date of Patent: July 23, 2013Assignee: Infineon Technologies AGInventor: Klaus Heinz Sandtner
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Patent number: 8486605Abstract: A positive resist composition including: a base material component (A) which exhibits increased solubility in an alkali developing solution under the action of acid; and an acid generator component (B) which generates acid upon exposure; dissolved in an organic solvent (S), wherein the base material component (A) includes a resin component (A1) having 4 types of specific structural units, and the organic solvent (S) includes from 60 to 99% by weight of an alcohol-based organic solvent (S1) and from 1 to 40% by weight of at least one organic solvent (S2) selected from the group consisting of propylene glycol monomethyl ether acetate, propylene glycol monomethyl ether and cyclohexanone.Type: GrantFiled: January 21, 2010Date of Patent: July 16, 2013Assignee: Tokyo Ohka Kogyo Co., Ltd.Inventors: Masaru Takeshita, Yasuhiro Yoshii, Jiro Yokoya, Hirokuni Saito, Tsuyoshi Nakamura
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Publication number: 20130157200Abstract: A suspension board with circuit includes a metal supporting board, an insulating base layer formed on the metal supporting board, a conductive pattern formed on the insulating base layer, an insulating cover layer formed on the insulating base layer so as to cover the conductive pattern, and an insertion portion to be inserted into an E-block. A thickness of the insulating cover layer in the insertion portion is larger than a thickness of the insulating cover layer in a portion other than the insertion portion.Type: ApplicationFiled: February 8, 2013Publication date: June 20, 2013Applicant: NITTO DENKO CORPORATIONInventor: Nitto Denko Corporation
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Patent number: 8465908Abstract: A method for forming fine patterns of a semiconductor device employs a double patterning characteristic using a mask for forming a first pattern including a line pattern and a mask for separating the line pattern, and a reflow characteristic of a photoresist pattern.Type: GrantFiled: November 17, 2008Date of Patent: June 18, 2013Assignee: Hynix Semiconductor Inc.Inventor: Jae Seung Choi
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Patent number: 8465901Abstract: Methods of adjusting dimensions of resist patterns are provided. The methods allow for control of photoresist pattern dimensions and find particular applicability in resist pattern rework in semiconductor device manufacturing.Type: GrantFiled: June 28, 2010Date of Patent: June 18, 2013Assignee: Rohm and Haas Electronic Materials LLCInventors: Young Cheol Bae, Thomas Cardolaccia, Yi Liu
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Patent number: 8460857Abstract: In the case in which a film for a resist is formed by spin coating, there is a resist material to be wasted, and the process of edge cleaning is added as required. Further, when a thin film is formed on a substrate using a vacuum apparatus, a special apparatus or equipment to evacuate the inside of a chamber vacuum is necessary, which increases manufacturing cost. The invention is characterized by including: a step of forming conductive layers on a substrate having a dielectric surface in a selective manner with a CVD method, an evaporation method, or a sputtering method; a step of discharging a compound to form resist masks so as to come into contact with the conductive layer; a step of etching the conductive layers with plasma generating means using the resist masks under the atmospheric pressure or a pressure close to the atmospheric pressure; and a step of ashing the resist masks with the plasma generating means under the atmospheric pressure or a pressure close to the atmospheric pressure.Type: GrantFiled: October 3, 2008Date of Patent: June 11, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideaki Kuwabara
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Patent number: 8455179Abstract: A method of forming a semiconductor device, including exposing a first shot to light on a semiconductor wafer, the first shot including a plurality of elongated chip patterns, the plurality of elongated chip patterns being arranged in parallel to each other and exposing a second shot to light on the semiconductor wafer, the second shot including a plurality of elongated chip patterns, so that the plurality of elongated chip patterns of the second shot and the plurality of elongated chip patterns of the first shot are arranged perpendicular to each other. The plurality of elongated chip patterns of the second shot are generated by rotating the plurality of elongated chip patterns of the first shot by 90 degrees.Type: GrantFiled: May 16, 2012Date of Patent: June 4, 2013Assignee: Renesas Electronics CorporationInventor: Takanori Yamamoto
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Patent number: 8455162Abstract: A plurality of reticles for printing structures in the same lithography level includes an alignment structure pattern within a same relative location in each reticle. Each set of process segmentations in a grating has a reticle segmentation pitch, which is common across all gratings in the plurality of reticles. Within each pair of alignment structure patterns that occupy the same relative location in any two of the plurality of reticles, the process segmentations in one reticle are shifted relative to the process segmentations in the other reticle by a fraction of a reticle segmentation pitch. After printing all patterns in the plurality of reticles, a composite printed process segmentation structure on the substrate includes printed segmentation structures that are spaced by 1/n times the printed segmentation pitch. The pattern for the next level can be aligned to the composite printed process segmentation structure in a single alignment operation.Type: GrantFiled: June 28, 2011Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: Allen H. Gabor, Vinayan C. Menon
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Patent number: 8450045Abstract: A pattern forming method includes providing and curing a under-layer film containing a radiation-sensitive acid generator which generates an acid upon exposure to radiation on a substrate. The under-layer film is irradiated with radiation through a mask to cause an acid to be selectively generated in an exposed area of the under-layer film. An upper-layer film which does not contain a radiation-sensitive acid generator and which contains a composition capable of polymerizing or crosslinking by an action of an acid is provided. A cured film is provided by polymerization or crosslinking selectively in an area of the upper-layer film corresponding to the exposed area of the under-layer film in which the acid has been generated. An area of the upper-layer film corresponding to an area of the under-layer film in which the acid has not been generated is removed.Type: GrantFiled: January 18, 2012Date of Patent: May 28, 2013Assignee: JSR CorporationInventors: Hikaru Sugita, Nobuji Matsumura, Daisuke Shimizu, Toshiyuki Kai, Tsutomu Shimokawa
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Patent number: 8435722Abstract: A method for fabricating a liquid crystal display includes: forming a gate electrode on a substrate; sequentially providing an insulation layer, a semiconductor layer and an etch stopper layer on the gate electrode; patterning the etch stopper layer and the semiconductor layer to form an etch stopper layer pattern and a semiconductor layer pattern; removing both side portions of the etch stopper layer pattern to expose the lower semiconductor layer pattern portion; forming a conductive layer on an entire surface of the substrate; patterning the conductive layer to form source and drain electrodes and defining a channel region; forming a passivation layer having a contact part on the entire surface of the substrate; and forming a pixel electrode connected with the drain electrode via the contact part on the passivation layer. An etch stopper can be used without additionally performing a masking process.Type: GrantFiled: December 15, 2006Date of Patent: May 7, 2013Assignee: LG Display Co., Ltd.Inventors: Dong-Su Shin, Joon-Young Yang, Jung-Il Lee
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Patent number: 8431329Abstract: Self-aligned spacer multiple patterning method are provided. The methods involve alkaline treatment of photoresist patterns and allow for the formation of high density resist patterns. The methods find particular applicability in semiconductor device manufacture.Type: GrantFiled: June 28, 2010Date of Patent: April 30, 2013Assignee: Rohm and Haas Electronic Materials LLCInventors: Young Cheol Bae, Thomas Cardolaccia, Yi Liu
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Patent number: 8431291Abstract: An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.Type: GrantFiled: October 25, 2011Date of Patent: April 30, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
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Patent number: 8431330Abstract: A surface-treating agent for forming a resist pattern, includes: a compound represented by formula (1) as defined in the specification, wherein the surface-treating agent is used in a step between a formation of a first resist pattern on a first resist film and a formation of a second resist film on the first resist pattern to form a second resist pattern, and a pattern-forming method uses the surface-treating agent.Type: GrantFiled: November 30, 2011Date of Patent: April 30, 2013Assignee: FUJIFILM CorporationInventors: Wataru Hoshino, Hideaki Tsubaki, Masahiro Yoshidome