Abstract: A method of fabricating a mask pattern includes providing numerous masks on a substrate. A wider trench and a narrower trench are respectively defined between the mask. Subsequently, a mask material is formed to fill in the wider trench and the narrower trench. The top surface of the mask material overlapping the wider trench is lower than the top surface of the mask material overlapping the narrower trench. A photoresist layer is formed on the mask material overlapping the wider trench. Later, the mask material overlapping the narrower trench is etched while the mask material overlapping the wider trench is protected by the photoresist layer.

Abstract: Methods of fabricating a semiconductor structure using a photoresist cross link process and a photoresist de-cross link process are described. A cross link bottom layer is employed during the fabricating process and the photoresist de-cross link process de-cross links the cross link bottom layer before the bottom layer is removed. The incorporation of the photoresist de-cross link process with the usage of the cross link bottom layer provides a cost effective and low defect level solution to fabricate the semiconductor structure.

Abstract: In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.

Abstract: A display apparatus includes a plurality of first brackets adhered to the rear panel. A first bracket has a recess on a first surface where an adhesive is applied, and a first protrusion extending from a second surface and a second protrusion extending from the first protrusion. A connection bracket has a side wall and a plurality of first tab portions. The tab portion is provided into an opening of the first protrusion. A second bracket is provided adjacent to the plurality of the first brackets and attached to the connection bracket. A frame is mounted to the at least one second bracket. A light source is provided between the frame and the second bracket.

Abstract: The present disclosure provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer with enhanced electron spinning control. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a processing chamber having a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a support pedestal disposed in the interior processing region of the processing chamber, and a plasma generator source disposed in the processing chamber operable to provide predominantly an electron beam source to the interior processing region.

Abstract: A method for forming a semiconductor device includes steps as follows: Firstly, a semiconductor substrate having a circuit element with at least one spacer formed thereon is provided. Next, an acid treatment is performed on a surface of the spacer. A disposable layer is then formed on the circuit element and the spacer. Thereafter, an etching process is performed to form at least one recess in the semiconductor substrate adjacent to the circuit element. Subsequently, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer in the recess.

Abstract: A method of processing semiconductor chips includes measuring locations of semiconductor dies placed on a carrier with a scanner to generate die location information. The method includes applying a dielectric layer over the semiconductor dies and communicating the die location information to a laser assembly. The method includes aligning the laser assembly with the carrier and laser structuring the dielectric layer with the laser assembly based on the die location information generated by the scanner.

Abstract: A developing method can perform a developing process on a resist film that is exposed to light. The developing method includes forming a developing solution film by supplying a developing solution onto a surface of a substrate having thereon a resist film that is exposed to light; thinning the developing solution film by pushing out the developing solution containing components dissolved from the resist film; and supplying a new developing solution onto the thinned developing solution film.

Abstract: A method includes forming a mask layer over a target layer. A merge cut feature is formed in the mask layer. A first mandrel layer is formed over the mask layer and the merge cut feature. The first mandrel layer is patterned to form first openings therein. First spacers are formed on sidewalls of the first openings. The first openings are filled with a dielectric material to form plugs. The first mandrel layer is patterned to remove portions of the first mandrel layer interposed between adjacent first spacers. The merge cut feature is patterned using the first spacers and the plugs as a combined mask. The plugs are removed. The mask layer is patterned using the first spacers as a mask. The target layer is patterned, using the mask layer and the merge cut feature as a combined mask, to form second openings therein.

Abstract: Embodiments herein provide apparatus and methods for performing an etching process on a spacer layer with good profile control in multiple patterning processes. In one embodiment, a method for patterning a spacer layer during a multiple patterning process includes conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has having a first group of openings defined therebetween and etching the spacer layer disposed on the substrate while forming an oxidation layer on the spacer layer.

Abstract: Embodiments in accordance with the present invention encompass positive-tone, aqueous developable, self-imageable polymer compositions useful for forming films that can be patterned to create structures for microelectronic devices, microelectronic packaging, microelectromechanical systems, optoelectronic devices and displays.

Abstract: A substrate processing method performs a photolithography processing on a wafer to form a resist pattern on the wafer. Ultraviolet ray is irradiated onto the resist pattern to cut side chains of the resist pattern to improve line edge roughness of the resist pattern. A processing agent is caused to enter the resist pattern and a metal is caused to be infiltrated into the resist pattern through the processing agent. Thereafter, the wafer is heated to vaporize the processing agent from the resist pattern to form a cured resist pattern.

Abstract: In order to provide a semiconductor device with high reliability while manufacturing cost is being suppressed, dry etching for an insulating film is performed by using mixed gas containing at least CF4 gas and C3H2F4 gas as its components.

Abstract: The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect.

Abstract: Methods and computer program products for decomposing and etching a circuit pattern layout are provided. The methods may include decomposing a circuit pattern layout into a first sub-pattern and second sub-pattern, where the decomposing includes: identifying, from the circuit pattern layout, a design line and a design via location associated with the design line; forming a first pattern line for the first sub-pattern corresponding to a first portion of the design line, and a second pattern line for the second sub-pattern corresponding to a second portion of the design line, with the first and second pattern lines overlapping at the design via location in an overlay of the first sub-pattern with the second sub-pattern. The first sub-pattern may be etched in a first circuit structure layer and the second sub-pattern etched in a second circuit structure layer, the etching at least partially forming a via at the design via location.

Abstract: A substrate is successively provided with a support (7), an electrically insulating layer (8), and a semi-conductor material layer (2). A first protective mask (1) completely covers a second area (B) of the semi-conductor material layer and leaves a first area (A) of the semi-conductor material layer uncovered. A second etching mask (3) partially covers the first area (A) and at least partially covers the second area (B), so as to define and separate a first area and a second area. Lateral spacers are formed on the lateral surfaces of the second etching mask (3) so as to form a third etching mask. The semi-conductor material layer (2) is etched by means of the third etching mask so as to form a pattern made from semi-conductor material in the first area (A), the first etching mask (3) protecting the second area (B).

Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.

Abstract: The present disclosure is related to a method for treating a photoresist structure on a substrate, the method comprising producing one or more resist structures on a substrate, introducing the substrate in a plasma reactor, and subjecting the substrate to a plasma treatment at a temperature lower than zero degrees Celsius, such as between zero and ?110° C. The plasma treatment may be a H2 plasma treatment performed in an inductively coupled plasma reactor. The treatment time may be at least 30s.

Abstract: A method for processing a substrate includes providing the substrate including a photoresist/bottom anti-reflection coating (PR/BARC) layer, a hard mask layer, a stop layer, a carbon layer and a stack including a plurality of layers. The method includes defining a hole pattern including a plurality of holes in the PR/BARC layer using photolithography; transferring the hole pattern into the carbon layer; filling the plurality of holes in the hole pattern with oxide to create oxide pillars; using a planarization technique to remove the hard mask layer, a remaining portion of the PR/BARC layer and the stop layer; stripping the carbon layer to expose the oxide pillars; filling space between the oxide pillars with hard a mask material including metal; planarizing at least part of the hard mask material; and stripping the oxide pillars to expose the hole pattern in the hard mask material.

Abstract: Various embodiments provide FinFETs and methods for forming the same. In an exemplary method, a semiconductor substrate having sacrificial layers formed thereon is provided. First sidewall spacers and second sidewall spacers are sequentially formed on both sides of each sacrificial layer. The sacrificial layers can be removed. A first width is measured as a distance between adjacent first sidewall spacers, and a second width is measured as a distance between adjacent second sidewall spacers. When the first width is not equal to the second width, the first sidewall spacers or the second sidewall spacers are correspondingly etched such that the first width is equal to the second width. The semiconductor substrate is etched using the first sidewall spacers and the second sidewall spacers as an etch mask, to form fins, such that a top of each fin has a symmetrical morphology.

Abstract: Provided are photoresist compositions useful in forming photolithographic patterns by a negative tone development process. Also provided are methods of forming photolithographic patterns by a negative tone development process and substrates coated with the photoresist compositions. The photoresist compositions include one or more polymer additive that contains a basic moiety and which is substantially non-miscible with a resin component of the resist. The compositions, methods and coated substrates find particular applicability in the manufacture of semiconductor devices.

Abstract: Provided is a plasma etching method of etching OCOC film in which HTO films and carbon films are alternately laminated by plasma of mixed gas containing first CF-based gas or second CF-based gas and oxygen gas using a silicon film formed on OCOC film as a mask. The etching of OCOC film includes a first etching process of etching a region spanning from the top surface to the middle of OCOC film by plasma of mixed gas containing first CF-based gas having a predetermined ratio of content of carbon to content of fluorine and oxygen gas and a second etching process of etching a region spanning from the middle of OCOC film to the lowest layer by plasma of mixed gas containing second CF-based gas having a ratio of content of carbon to content of fluorine, which is higher than the predetermined ratio of first CF-based gas, and oxygen gas.

Abstract: A stripping solution for photolithography which can effectively strip away residual materials of a photoresist pattern and etching residual materials, and has excellent anticorrosion properties on SiO2 and a variety of metal materials; and a method for forming a pattern using the stripping solution. A prescribed basic compound is used as a counter amine of the hydrofluoric acid contained in the stripping solution for photolithography, and the stripping solution for photolithography is adjusted to a pH measured at 23° C. of not more than 6.0 or 8.5 or more.

Abstract: A maskless exposure device includes an exposure head including a digital micro-mirror device. The digital micro-mirror device is configured to transmit a source beam applied from an exposure source to a substrate. A system control part is configured to control the digital micro-mirror device by using a graphic data system file. The graphic data system file includes data for forming a source electrode, a drain electrode and a channel portion disposed between the source electrode and the drain electrode. The graphic system file includes data for forming the channel portion extending in a diagonal direction with respect to a scan direction of the exposure head.

Abstract: An interconnect structure is provided that may include at least one cured permanent patterned dielectric material located on a surface of a substrate. The at least one cured permanent patterned dielectric material is a cured product of a patterned photoresist that includes a dielectric enabling element therein. The structure further includes at least one conductively filled region embedded within the at least one cured permanent patterned dielectric material.

Abstract: In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.

Abstract: A device comprises a first group of nanowires having a first pattern, a second group of nanowires having a second pattern, a third group of nanowires having a third pattern and a fourth group of nanowires having a fourth pattern, wherein the first pattern, the second pattern, the third pattern and the fourth pattern form a repeating pattern.

Abstract: Easily removable heteroatom-doped carbon-containing layers are deposited. The carbon-containing layers may be used as hardmasks. The heteroatom-doped carbon-containing hardmasks have high etch selectivity and density and also a low compressive stress, which will reduce or eliminate problems with wafer bow. Heteroatoms incorporated into the hardmask include sulfur, phosphorous, nitrogen, oxygen, and fluorine, all of which have low reactivity towards commonly used etchants. When sulfur is used as the heteroatom, the hardmask is easily removed, which simplifies the fabrication of NAND devices, DRAM devices, and other devices.

Abstract: Provided is a method for forming a pattern on a layer on a substrate. The method includes forming a line-and-space pattern on the layer; coating a resist on the line-and-space pattern and filling the resist in a space portion of the line-and-space pattern; exposing a pattern to the resist, developing the exposed resist, and forming a resist pattern on the space portion; and forming a pattern on the layer using a pattern which is a combination of a line portion of the line-and-space pattern and the resist pattern as a mask.

Abstract: Present example embodiments relate generally to semiconductor devices, masks, wafers, and methods of fabricating semiconductor devices, masks, and wafers. Example methods comprise providing a substrate having a photoresist layer. Example methods further comprise providing a mask having a substantially rectangular pattern and an elongated pattern, at least a portion of the elongated pattern positioned at least proximate to a corner of the substantially rectangular pattern, wherein the elongated pattern extends outwardly from the substantially rectangular pattern. Example methods further comprise forming a substantially rectangular shaped pattern on the photoresist layer resembling the substantially rectangular pattern using a cooperation of the substantially rectangular pattern and the elongated pattern.

Abstract: A method of forming an array of recessed access device gate constructions includes using the width of an anisotropically etched sidewall spacer in forming mask openings in an etch mask for forming all recessed access device trenches within semiconductor material within all of the array. The etch mask is used while etching all of the recessed access device trenches into the semiconductor material within all of the array through the mask openings. Individual recessed access gate constructions are formed in the individual recessed access device trenches. Other methods are contemplated, including arrays of recessed access devices independent of method of manufacture.

Abstract: In one example, a reticle disclosed herein includes a body having a center, an arrangement of a plurality of exposure patterns, wherein a center of the arrangement is offset from the center of the body, and at least one open feature defined on or through the body of the reticle. In another example, a method is disclosed that includes forming a layer of photoresist above a plurality of functional die and a plurality of incomplete die, exposing the photoresist material positioned above at least one of the functional die and/or at least one of the incomplete die, performing an incomplete die exposure processes via an open feature of the reticle to expose substantially all of the photoresist material positioned above the plurality of incomplete die, and developing the photoresist to remove the portions of the photoresist material positioned above the incomplete die.

Abstract: In a first aspect, methods are provided that comprise: (a) applying a curable composition on a substrate; (b) applying a hardmask composition above the curable composition; (c) applying a photoresist composition layer above the hard mask composition, wherein one or more of the compositions are removed in an ash-free process. In a second aspect, methods are provided that comprise (a) applying an organic composition on a substrate; (b) applying a photoresist composition layer above the organic composition, wherein the organic composition comprises a material that produce an alkaline-soluble group upon thermal and/or radiation treatment. Related compositions also are provided.

Abstract: Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device. A first polysilicon region can then be formed over the core and periphery regions of the semiconductor device. A first mask is formed on the first poly silicon layer and a second polysilicon layer is disposed such that the second polysilicon layer covers the first mask. A second mask can then be formed on the second polysilicon layer. After forming the second mask, portions of the first and second polysilicon layers that are uncovered by either the first or second masks are removed.

Abstract: A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

Abstract: A method for forming semiconductor layout patterns providing a pair of first layout patterns being symmetrical along an axial line, each of the first layout patterns comprising a first side proximal to the axial line and a second side far from the axial line; shifting a portion of the first layout patterns toward a direction opposite to the axial line to form at least a first shifted portion in each first layout pattern, and outputting the first layout patterns and the first shifted portions on a first mask.

Abstract: Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases.

Abstract: Methods disclosed herein apply an electric field and/or a magnetic field during photolithography processes. The field application may control the diffusion of the charged species generated by the photoacid generator along the line and spacing direction, preventing the line edge/width roughness that results from random diffusion. The field application may additionally or alternatively control the diffusion of the charged species in a direction perpendicular to a plane formed by the photoresist layer. Such controlled perpendicular diffusion may increase the photoresist sensitivity. In other embodiments, the field may control the diffusion of the charged species within the plane of the photoresist layer but in a direction perpendicular or non-parallel to the line and spacing direction. Apparatuses for carrying out the aforementioned methods are also disclosed herein.

Abstract: A method for forming a layout pattern includes the following processes. First, a first layout pattern consisting of mandrel patterns and dummy mandrel patterns, a second layout pattern consisting of geometric patterns, and a third layout pattern consisting of pad patterns and dummy pad patterns, are respectively defined on a first mask, a second mask, and a third mask. Then, the first layout pattern is transferred to form a first patterned layer. Afterwards, spacers having a first critical dimension are formed on the sidewalls of the first patterned layer so as to constitute loop-shaped patterns. Then, the third layout pattern is transferred to form a second patterned layer having a second critical dimension, wherein the second critical dimension is greater than the first critical dimension. Finally, the loop-shaped patterns, the pad patterns, and the dummy pad patterns are transferred into a target layer on the substrate.

Abstract: The method of fabricating a multi-level, metallic microstructure includes the steps consisting in structuring a first layer of photosensitive resin so as to obtain a first level of a resin mould, the aperture in the first resin layer revealing a conductive surface of a substrate, structuring a second photosensitive resin layer over the first level of a resin mould so as to obtain a multi-level resin mould, the apertures in the multi-level mould revealing the conductive surface of the substrate, galvanically depositing a metal or alloy in the apertures of the multi-level resin mould and separating a multi-level metallic structure formed by the metal or alloy deposited in the apertures from the substrate and the multi-level resin mould.

Abstract: The present invention provides a method for forming a resist under layer film used in a lithography process, comprising: a process for applying a composition for forming a resist under layer film containing an organic compound having an aromatic unit on a substrate; and a process for heat-treating the resist under layer film applied in an atmosphere whose oxygen concentration is 10% or more at 150° C. to 600° C. for 10 to 600 seconds after heat-treating the same in an atmosphere whose oxygen concentration is less than 10% at 50 to 350° C. There can be provided a method for forming a resist under layer film having excellent filling/flattening properties so that unevenness on a substrate can be flattened even in complex processes such as multi-layer resist method and double patterning.

Abstract: A method includes coating a photo resist on a wafer in a first production tool, and performing a pre-exposure baking on the photo resist in a second production tool separate from the first production tool. After the pre-exposure baking, the photo resist is exposed using a lithography mask. After the step of exposing the photo resist, a post-exposure baking is performed on the photo resist. The photo resist is then developed.

Abstract: The disclosure describes dry acrylate resin particles, optionally, with a C/O of at least about 4, comprising a heterocycle comprising sulfur, exhibiting high charge and improved RH sensitivity.

Abstract: There is provided a method of manufacturing a field-effect transistor, in which on a electroconductive layer including a source electrode, a drain electrode and pixel electrode formed by a conductive layer-forming, an inorganic insulating layer containing an inorganic material as a main component is formed so as to cover the electroconductive layer and an oxide semiconductive layer, and after a photoresist film is formed on the inorganic insulating layer and is exposed in a pattern shape, a resist pattern is formed by being developed using a developer in development, and by removing the area exposed from the resist pattern in the inorganic insulating layer by using the developer as an etching liquid, a part of the electroconductive layer is exposed, thereby forming a contact hole; a field-effect transistor, a display device and an electromagnetic wave detector.

Abstract: The present disclosure provides methods of forming patterning features in a semiconductor structure using a sidewall image transfer technique. The method includes first forming a plurality of sacrificial mandrels over a dielectric hard mask layer. Each sacrificial mandrel has a width greater than a minimum spacing between adjacent patterning features subsequently formed according to a circuit design. After forming a plurality of spacer material layer portions on sidewalls of the sacrificial mandrels, a plurality of filler material layer portions are formed adjacent the spacer material layer portions. The cycle of forming the spacer material layer portions and filler material layer portions may be repeated until spaces between sacrificial mandrels are completely filled. Removal of the sacrificial mandrels and the filler material layer portions provides patterning features.

Abstract: Described herein are compositions for forming an underlayer film for a solvent-developable resist. These compositions can include a hydrolyzable organosilane having a silicon atom bonded to an organic group containing a protected aliphatic alcohol group, a hydrolysate of the hydrolyzable organosilane, a hydrolysis-condensation product of the hydrolyzable organosilane, or a combination thereof and a solvent. The composition can form a resist underlayer film including, a hydrolyzable organosilane, a hydrolysate of the hydrolyzable organosilane, a hydrolysis-condensation product of the hydrolyzable organosilane, or a combination thereof, the silicon atom in the silane compound having a silicon atom bonded to an organic group containing a protected aliphatic alcohol group in a ratio of 0.1 to 40% by mol based on the total amount of silicon atoms. Also described is a method for applying the composition onto a semiconductor substrate and baking the composition to form a resist underlayer film.

Abstract: A method for etching a desired complex pattern in a first face of a substrate, including: simultaneous etching of at least a first and a second sub-pattern through the first face of the substrate, the etched sub-patterns being separated by at least one separating wall, a width of the first sub-pattern being greater than a width of the second sub-pattern at the first face, and a depth of the first sub-pattern being greater than a depth of the second sub-pattern in a direction perpendicular to the said first face; and removing or eliminating the separating wall to expose the desired complex pattern.

Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

Abstract: A method of manufacturing a mask includes: providing a base substrate including light-absorbing layer patterns on a first surface thereof; providing a reflective layer on the light-absorbing layer patterns and the first surface of the base substrate; and providing reflective patterns by partially removing the reflective layer. The providing the reflective patterns includes removing the light-absorbing layer patterns and a portion of the reflective layer, by irradiating the light-absorbing layer patterns with laser light.

Abstract: A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.