Abstract: Provided herein is an apparatus, including a patterned resist overlying a substrate; a number of features of the patterned resist, wherein the number of features respectively includes a number of sidewalls; and a sidewall-protecting material disposed about the number of sidewalls, wherein the sidewall-protecting material is characteristic of a conformal, thin-film deposition, and wherein the sidewall-protecting material facilitates a high-fidelity pattern transfer of the patterned resist to the substrate during etching.

Abstract: A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %.

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

Abstract: A method for fabricating a circuit, by defining a first set of resist features on a substrate and corresponding to a first mask layout, followed by defining a second set of resist features on the substrate corresponding to a second mask layout, wherein the second set adds to the first set for rectifying an error in either mask layout. In another aspect, the method is by defining a first set of resist features on a substrate and corresponding to a first mask layout that has an error, etching the substrate while the first set protects selected regions, defining a second set of resist features on the substrate and corresponding to a second mask layout, followed by etching the substrate to selectively remove portions of the selected regions for rectifying the error.

Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.

Abstract: A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A negative photoresist layer is formed on a positive photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist layer and to form a second exposure region in the negative photoresist layer in response to a first and a second intensity thresholds of the exposure energy. A negative-tone development process is performed to remove portions of the negative photoresist layer to form first opening(s). The positive photoresist layer is then etched along the first opening(s) to form second opening(s) therein. A positive-tone development process is performed to remove the first exposure region therefrom to form a double patterned positive photoresist layer.

Abstract: According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer. Next, the spacer film is etch-backed. Subsequently, an embedded layer is embedded between the core patterns whose peripheral areas are surrounded by the spacer film. Then, the core pattern and the embedded layer are removed simultaneously. Subsequently, using the spacer pattern as a mask, the hard mask layer and the process object are processed.

Abstract: A method for using self aligned multiple patterning with multiple resist layers includes forming a first patterned resist layer onto a substrate, forming a spacer layer on top of the first patterned resist layer such that spacer forms on side walls of features of the first resist layer, and forming a second patterned resist layer over the spacer layer and depositing a masking layer. The method further includes performing a planarizing process to expose the first patterned resist layer, removing the first resist layer, removing the second resist layer, and exposing the substrate.

Abstract: A coating agent for forming a fine pattern and a method for forming a fine pattern using the coating agent, in which the coating agent allows a resist pattern to be favorably fined, and can form a fined pattern having a suppressed deviation of CD. A coating agent for forming a fine pattern including (A) a water-soluble polymer is combined with a compound in which the compound has an alkyl group having 8 or more carbon atoms bound to a nitrogen atom, and is combined with 4 moles or more of ethylene oxide and/or propylene oxide with respect to 1 mole of a nitrogen atom bound with the alkyl group as (B) a nitrogen-containing compound.

Abstract: Methods of multiple exposure in the fields of deep ultraviolet photolithography, next generation lithography, and semiconductor fabrication comprise a spin-castable methodology for enabling multiple patterning by completing a standard lithography process for the first exposure, followed by spin casting an etch selective overcoat layer, applying a second photoresist, and subsequent lithography. Utilizing the etch selectivity of each layer, provides a cost-effective, high resolution patterning technique. The invention comprises a number of double or multiple patterning techniques, some aimed at achieving resolution benefits, as well as others that achieve cost savings, or both resolution and cost savings. These techniques include, but are not limited to, pitch splitting techniques, pattern decomposition techniques, and dual damascene structures.

Abstract: According to one embodiment, the invention relates to a method for the anisotropic etching of patterns in at least one layer to be etched through a hard mask comprising carbon in an inductive-coupling plasma etching reactor (ICP), the method being characterized in that the hard mask is made from boron doped with carbon (B:C), and in that, prior to the anisotropic etching of the patterns in said layer to be etched through the hard mask of carbon-doped boron (B:C), the following steps are performed: realization of an intermediate hard mask situated on a layer of carbon-doped boron intended to form the hard mask made from carbon-doped boron (B:C), etching of the layer of carbon-doped boron (B:C) through the intermediate hard mask in order to form the hard mask made from carbon-doped boron (B:C), the realization of the intermediate hard mask and the etching of the hard mask made from carbon-doped boron (B:C) being done in said inductive coupling plasma etching reactor (ICP).

Abstract: Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops and sidewalls of the features. The first material may be formed by spin-casting a conformal layer of the first material across the features, or by selective deposition along the features relative to the substrate. After the first material is formed, fill material may be provided between the features while leaving regions of the first material exposed. The exposed regions of the first material may then be selectively removed relative to both the fill material and the features to create the pattern of openings.

Abstract: The present invention provides a silicon oxynitride film formation method capable of reducing energy cost, and also provides a substrate equipped with a silicon oxynitride film formed thereby. This method comprises the steps of: casting a film-formable coating composition containing a polysilazane compound on a substrate surface to form a coat; drying the coat to remove excess of the solvent therein; and then irradiating the dried coat with UV light at a temperature lower than 150° C.

Abstract: A conductive pattern is prepared in a polymeric layer that has (a) a reactive polymer comprising pendant tertiary alkyl ester groups, (b) a compound that provides an acid upon exposure to radiation having a ?max of at least 150 nm and up to and including 450 nm, and (c) a crosslinking agent. The polymeric layer is patternwise exposed to provide a polymeric layer comprising non-exposed regions and exposed regions comprising a polymer comprising carboxylic acid groups. The exposed regions are contacted with electroless seed metal ions to form a pattern of electroless seed metal ions. The pattern of electroless seed metal ions is then reduced to provide a pattern of corresponding electroless seed metal nuclei. The corresponding electroless seed metal nuclei are then electrolessly plated with a conductive metal.

Abstract: A neural probe comprising an array of stimulation and/or recording electrodes supported on a tape spring-type carrier is described. The neural probe comprising the tape spring-type carrier is used to insert flexible electrode arrays straight into tissue, or to insert them off-axis from the initial penetration of a guide tube. Importantly, the neural probe is not rigid, but has a degree of stiffness provided by the tape spring-type carrier that maintains a desired trajectory into body tissue, but will subsequently allow the probe to flex and move in unison with movement of the body tissue.

Abstract: The invention provides a patterning process comprises the steps of: (1) forming a positive chemically amplifying type photoresist film on a substrate to be processed followed by photo-exposure and development thereof by using an organic solvent to obtain a negatively developed pattern, (2) forming a silicon-containing film by applying a silicon-containing film composition comprising a solvent and a silicon-containing compound capable of becoming insoluble in a solvent by a heat, an acid, or both, (3) insolubilizing in a solvent the silicon-containing film in the vicinity of surface of the negatively developed pattern, (4) removing the non-insolubilized part of the silicon-containing film to obtain an insolubilized part as a silicon-containing film pattern, (5) etching the upper part of the silicon-containing film pattern thereby exposing the negatively developed pattern, (6) removing the negatively developed pattern, and (7) transferring the silicon-containing film pattern to the substrate to be processed.

Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.

Abstract: A method for patterning a layered structure is provided that includes performing photolithography to provide a developed prepattern layer on a horizontal surface of an underlying substrate, modifying the prepattern layer to form spaced apart inorganic material guides, casting and annealing a layer of a self-assembling block copolymer to form laterally-spaced cylindrical features, forming a pattern by selectively removing at least a portion of one block of the self-assembling block copolymer, and transferring the pattern to the underlying substrate. The method is suitable for making sub-50 nm patterned layered structures.

Abstract: The present application discloses methods, systems and devices for using charged particle beam tools to pattern and inspect a substrate. The inventors have discovered that it is highly advantageous to use write and inspection tools that share the same or substantially the same stage and the same or substantially the same designs for respective arrays of multiple charged particle beam columns, and that access the same design layout database to target and pattern or inspect features. By using design-matched charged particle beam tools, correlation of defectivity is preserved between inspection imaging and the design layout database. As a result, image-based defect identification and maskless design correction, of random and systematic errors, can be performed directly in the design layout database, enabling a fast yield ramp.

Abstract: The present application discloses methods, systems and devices for using charged particle beam tools to pattern and inspect a substrate. The inventors have discovered that it is highly advantageous to use write and inspection tools that share the same or substantially the same stage and the same or substantially the same designs for respective arrays of multiple charged particle beam columns, and that access the same design layout database to target and pattern or inspect features. By using design-matched charged particle beam tools, correlation of defectivity is preserved between inspection imaging and the design layout database. As a result, image-based defect identification and maskless design correction, of random and systematic errors, can be performed directly in the design layout database, enabling a fast yield ramp.

Abstract: One or more techniques or systems for controlling a profile for photo resist (PR) are provided herein. In some embodiments, a first shield layer is formed on a first PR layer and a second PR layer is formed on the first shield layer. A first window is formed within the second PR layer during a first exposure with a mask. A second window is formed within the first shield layer based on the first window. A third window is formed within the first PR layer during a second exposure without a mask. Because, the third window is formed while the first shield layer and the second PR layer are on the first PR layer, a profile associated with the first PR layer is controlled. Contamination during ion bombardment is mitigated due to the controlled profile.

Abstract: A method for forming quarter-pitch patterns is described. Two resist layers are formed. The upper resist layer is defined into first patterns. A coating that contains or generates a reactive material making a resist material dissolvable is formed over the lower resist layer and the first patterns. The reactive material is diffused into a portion of each first pattern and portions of the lower resist layer between the first patterns to react with them. The coating is removed. A development step is performed to remove the portions of the first patterns and the portions of the lower resist layer, so that the lower resist layer is patterned into second patterns. Spacers are formed on the sidewalls of the remaining first patterns and the second patterns. The remaining first patterns are removed, and portions of the second patterns are removed using the spacers on the second patterns as a mask.

Abstract: The present invention relates to a hybrid photoresist composition for improved resolution and a pattern forming method using the photoresist composition. The photoresist composition includes a radiation sensitive acid generator, a crosslinking agent and a polymer having a hydrophobic monomer unit and a hydrophilic monomer unit containing a hydroxyl group. At least some of the hydroxyl groups are protected with an acid labile moiety having a low activation energy. The photoresist is capable of producing a hybrid response to a single exposure. The patterning forming method utilizes the hybrid response to form a patterned structure in the photoresist layer. The photoresist composition and the pattern forming method of the present invention are useful for printing small features with precise image control, particularly spaces of small dimensions.

Abstract: A lithographic material stack including a metal-compound hard mask layer is provided. The lithographic material stack includes a lower organic planarizing layer (OPL), a dielectric hard mask layer, and the metal-compound hard mask layer, an upper OPL, an optional anti-reflective coating (ARC) layer, and a photoresist layer. The metal-compound hard mask layer does not attenuate optical signals from lithographic alignment marks in underlying material layers, and can facilitate alignment between different levels in semiconductor manufacturing.

Abstract: A transparent component comprises a substrate (1) having an interface surface, with a pattern of electrically conductive copper (2) disposed on the interface surface with of the substrate, wherein the copper has a copper sulfide surface coating (3). It is found that copper with a suitably thin coating layer of copper sulfide has reduced visibility compared with uncoated copper, so that the metal pattern is less distracting to a viewer. The component finds application as part of a touch-sensitive display, with the substrate overlying or forming part of the display, with images on the display being visible to a user through the transparent component.

Abstract: In a chemically amplified positive resist composition comprising a base resin and an acid generator in a solvent, the base resin contains both an alkali-insoluble or substantially alkali-insoluble polymer having an acid labile group-protected acidic functional group having a Mw of 1,000-500,000 and an alkyl vinyl ether polymer having a Mw of 10,000-500,000. The composition forms on a substrate a resist film of 5-100 ?m thick which can be briefly developed to form a pattern at a high sensitivity and a high degree of removal or dissolution to bottom.

Abstract: A method of forming a patterned film on both a bottom and a top-surface of a deep trench is disclosed. The method includes the steps of: 1) providing a substrate having a deep trench formed therein; 2) growing a film over a bottom and a top-surface of the deep trench; 3) coating a photoresist in the deep trench and over the substrate and baking the photoresist to fully fill the deep trench; 4) exposing the photoresist to form a latent image that partially covers the deep trench in the photoresist; 5) silylating the photoresist with a silylation agent to transform the latent image into a silylation pattern; 6) etching the photoresist to remove a portion of the photoresist not covered by the silylation pattern; and 7) etching the film to form a patterned film on both the bottom and the top-surface of the deep trench.

Abstract: A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.

Abstract: A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.

Abstract: A target space ratio of a monitor pattern on a substrate for inspection is determined to be different from a ratio of 1:1. A range of space ratios in a library is determined to include the target space ratio and not include a space ratio of 1:1. The monitor pattern is formed on a film to be processed by performing predetermined processes on the substrate for inspection. Sizes of the monitor pattern are measured. The sizes of the monitor pattern are converted into sizes of a pattern of the film to be processed having a space ratio of 1:1, and processing conditions of the predetermined processes are compensated for based on the sizes of the converted pattern of the film to be processed. After that, the predetermined processes are performed on a wafer under the compensated conditions to form a pattern having a space ratio of 1:1 on the film to be processed.

Abstract: A method of fabricating a plurality of features of a semiconductor device includes providing a dielectric layer over a silicon layer, and etching the dielectric layer and the silicon layer to form a plurality of first apertures in the dielectric layer and the silicon layer, wherein adjacent apertures of the plurality of first apertures are set apart by a first pitch. The method further includes etching a plurality of second apertures in the dielectric layer, each aperture of the plurality of second apertures having a greater width than and centered about a respective aperture of the plurality of first apertures, implanting a plurality of dopants into the silicon layer aligned through the plurality of second apertures in the dielectric layer, wherein doped portions of the silicon layer are set apart by a second pitch less than the first pitch, and removing undoped portions of the silicon layer.

Abstract: An orthogonal process for photolithographic patterning organic structures is disclosed. The disclosed process utilizes fluorinated solvents or supercritical CO2 as the solvent so that the performance of the organic conductors and semiconductors would not be adversely affected by other aggressive solvent. One disclosed method may also utilize a fluorinated photoresist together with the HFE solvent, but other fluorinated solvents can be used. In one embodiment, the fluorinated photoresist is a resorcinarene, but various fluorinated polymer photoresists and fluorinated molecular glass photoresists can be used as well. For example, a copolymer perfluorodecyl methacrylate (FDMA) and 2-nitrobenzyl methacrylate (NBMA) is a suitable orthogonal fluorinated photoresist for use with fluorinated solvents and supercritical carbon dioxide in a photolithography process.

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

Abstract: A method for fabricating a circuit, by defining a first set of resist features on a substrate and corresponding to a first mask layout, followed by defining a second set of resist features on the substrate corresponding to a second mask layout, wherein the second set adds to the first set for rectifying an error in either mask layout. In another aspect, the method is by defining a first set of resist features on a substrate and corresponding to a first mask layout that has an error, etching the substrate while the first set protects selected regions, defining a second set of resist features on the substrate and corresponding to a second mask layout, followed by etching the substrate to selectively remove portions of the selected regions for rectifying the error.

Abstract: A method for printing a wafer ID on a wafer, the method comprises identifying a wafer ID on a back side of the wafer. Subsequently, etching a plurality of recesses, consistent in size with chip features of the wafer, into the front side of the wafer, such that the plurality of recesses depicts the wafer ID. The method further comprises filling the recesses with a metal.

Abstract: There is provided a resist underlayer film having both heat resistance and etching selectivity. A composition for forming a resist underlayer film for lithography, comprising a reaction product (C) of an alicyclic epoxy polymer (A) with a condensed-ring aromatic carboxylic acid and monocyclic aromatic carboxylic acid (B). The alicyclic epoxy polymer (A) may include a repeating structural unit of Formula (1): (T is a repeating unit structure containing an alicyclic ring in the polymer main chain; and E is an epoxy group or an organic group containing an epoxy group). The condensed-ring aromatic carboxylic acid and monocyclic aromatic carboxylic acid (B) may include a condensed-ring aromatic carboxylic acid (B1) and a monocyclic aromatic carboxylic acid (B2) in a molar ratio of B1:B2=3:7 to 7:3. The condensed-ring aromatic carboxylic acid (B1) may be 9-anthracenecarboxylic acid and the monocyclic aromatic carboxylic acid (B2) may be benzoic acid.

Abstract: The invention concerns a method for producing a microelectronic device comprising a substrate and a stack comprising at least one electrically conductive layer and at least on dielectric layer, wherein it comprises the following steps: formation, from one face of the substrate, of at least one pattern that is in depression with respect to a plane of the face of the substrate, the wall of the pattern comprising a bottom part and a flank part, the flank part being situated between the bottom part and the face of the substrate, the flank part comprising at least one inclined wall as far as the face of the substrate, formation of the stack, the layers of the stack helping to at least partially fill in the pattern, thinning of the stack at least as far as the plane of the face of the substrate so as to completely expose the edge of said at least one electrically conductive layer flush in one plane, formation of at least one electrical connection member (710, 720) on the substrate in contact with the edge of sai

Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.

Abstract: Some embodiments include methods of forming patterns. A semiconductor substrate is formed to comprise an electrically insulative material over a set of electrically conductive structures. An interconnect region is defined across the electrically conductive structures, and regions on opposing sides of the interconnect region are defined as secondary regions. A two-dimensional array of features is formed over the electrically insulative material. The two-dimensional array extends across the interconnect region and across the secondary regions. A pattern of the two-dimensional array is transferred through the electrically insulative material of the interconnect region to form contact openings that extend through the electrically insulative material and to the electrically conductive structures, and no portions of the two-dimensional array of the secondary regions is transferred into the electrically insulative material.

Abstract: A disclosed mask pattern forming method includes isotropically coating a surface of a resist pattern array having a predetermined line width with a silicon oxide film, embedding a gap in the resist pattern array coated by the silicon oxide film with a carbon film, removing the carbon film from the upper portion and etching back the carbon film while leaving the carbon film within the gap in any order, removing the remaining carbon film and etching back the upper portion of the resist pattern array to have a predetermined film thickness in any order, and forming a first mask pattern array which has a center portion having a predetermined width and film sidewall portions sandwiching the predetermined width, and arranged interposing a space width substantially the same as the predetermined line width with an asking process provided to the resist pattern array exposed from the removed silicon oxide film.

Abstract: A method for forming fine patterns of a semiconductor device employs a double patterning characteristic using a mask for forming a first pattern including a line pattern and a mask for separating the line pattern, and a reflow characteristic of a photoresist pattern.

Abstract: A photoresist composition includes a binder resin, a photo acid generator, an acryl resin having four different types of monomers, and a solvent.

Abstract: In a pattern forming method, a first L & S pattern is formed on a wafer; a first protective layer, a second L & S pattern having a perpendicular periodic direction to that of the first L & S pattern, and a photoresist layer are formed to cover the first L & S pattern; a third pattern having first apertures is formed in the photoresist layer to be overlapped with a part of the second L & S pattern; second apertures are formed in the first protective layer via the first apertures; and a part of the first L & S pattern is removed via the second apertures. Accordingly, a pattern including a non-periodic portion finer than a resolution limit of an exposure apparatus is formed.

Abstract: Disclosed is a method and apparatus for mitigation of photoresist line pattern collapse in a photolithography process by applying a gap-fill material treatment after the post-development line pattern rinse step. The gap-fill material dries into a solid layer filling the inter-line spaces of the line pattern, thereby preventing line pattern collapse due to capillary forces during the post-rinse line pattern drying step. Once dried, the gap-fill material is depolymerized, volatilized, and removed from the line pattern by heating, illumination with ultraviolet light, by application of a catalyst chemistry, or by plasma etching.

Abstract: In a method for imaging a solid state substrate, a vapor is condensed to an amorphous solid water condensate layer on a surface of a solid state substrate. Then an image of at least a portion of the substrate surface is produced by scanning an electron beam along the substrate surface through the water condensate layer. The water condensate layer integrity is maintained during electron beam scanning to prevent electron-beam contamination from reaching the substrate during electron beam scanning. Then one or more regions of the layer can be locally removed by directing an electron beam at the regions. A material layer can be deposited on top of the water condensate layer and any substrate surface exposed at the one or more regions, and the water condensate layer and regions of the material layer on top of the layer can be removed, leaving a patterned material layer on the substrate.

Abstract: A method of forming fine patterns of a semiconductor device according to a double patterning process that uses acid diffusion is provided. In this method, a plurality of first mask patterns are formed on a substrate. A capping film including an acid source is formed on the exposed surface areas of the plurality of first mask patterns. A second mask layer is formed on the capping films. A plurality of acid diffused regions are formed within the second mask layer by diffusing acid obtained from the acid source from the capping films into the second mask layer. A plurality of second mask patterns are formed of residual parts of the second mask layer which remain after removing the acid diffused regions of the second mask layer.

Abstract: A method for patterning a substrate is described. The patterning method may include performing a lithographic process to produce a pattern and a critical dimension (CD) slimming process to reduce a CD in the pattern to a reduced CD. Thereafter, the pattern is doubled to produce a double pattern using a sidewall image transfer technique.

Abstract: A method of forming gate conductor structures. A substrate having thereon a gate electrode layer is provided. A multi-layer hard mask is formed overlying the gate electrode layer. The multi-layer hard mask comprises a first hard mask, a second hard mask, and a third hard mask. A photoresist pattern is formed on the multi-layer hard mask. A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist, thereby forming a patterned third hard mask. A second etching process is performed to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist, thereby forming a patterned first hard mask. A third etching process is performed to etch a layer of the gate electrode layer, using the patterned first hard mask as a third etch resist.

Abstract: To provide a resist pattern improving material, containing: water; and benzalkonium chloride represented by the following general formula (1): where n is an integer of 8 to 18.

Abstract: An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.