Insulative Or Nonmetallic Dielectric Etched Patents (Class 430/317)
  • Patent number: 7320855
    Abstract: A top anti-reflective coating material (TARC) and barrier layer, and the use thereof in lithography processes, is disclosed. The TARC/barrier layer may be especially useful for immersion lithography using water as the imaging medium. The TARC/barrier layer comprises a polymer which comprises at least one silicon-containing moiety and at least one aqueous base soluble moiety. Suitable polymers include polymers having a silsesquioxane (ladder or network) structure, such as polymers containing monomers having the structure: where R1 comprises an aqueous base soluble moiety, and x is from about 1 to about 1.95, more preferably from about 1 to about 1.75.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: January 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Wu-Song S. Huang, Sean D. Burns, Pushkara Rao Varanasi
  • Patent number: 7306742
    Abstract: A template 1 is brought close to or in contact with a surface to be patterned 111 and patterns are formed with liquid 62 on the surface 111. This method comprises the steps of: bringing the template 1 close to or essentially in contact with the surface 111, supplying liquid 62 to a plurality of through holes 12 established in the pattern transfer region 10 of the template 1 for supplying the liquid 62, and separating the template 1 from the surface 111 after the liquid 62 is adhered to the surface 111 via the through holes 12.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: December 11, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Satoshi Nebashi, Takao Nishikawa, Tatsuya Shimoda
  • Patent number: 7303855
    Abstract: An undercoat-forming material comprising a novolak resin having a fluorene or tetrahydrospirobiindene structure, an organic solvent, an acid generator, and a crosslinker, optionally combined with an intermediate layer having an antireflective effect, has an absorptivity coefficient sufficient to provide an antireflective effect at a thickness of at least 200 nm and a high etching resistance as demonstrated by slow etching rates with CF4/CHF3 and Cl2. BCl3 gases for substrate processing.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: December 4, 2007
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Jun Hatakeyama, Satoshi Watanabe
  • Patent number: 7303859
    Abstract: There is provided a positive photoresist for near-field exposure excellent in light utilization efficiency even with small layer thickness of the photoresist layer for image formation, and allowing for reduced pattern edge roughness, and a photolithography method including a step of exposing by the near-field exposure the photoresist layer for image formation made thereof. In a positive photoresist containing an alkali-soluble novolak resin and a quinone diazide compound, the film thickness of the photoresist at the time of exposure is not larger than 100 nm, and the absorption coefficient of the photoresist ? (?m?1) for the exposure light is such that 0.5???7.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: December 4, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takako Yamaguchi, Yasuhisa Inao
  • Patent number: 7297452
    Abstract: A photosensitive resin composition includes an alkali-soluble resin, a quinone diazide, a surfactant, and a solvent. The surfactant includes an organic fluorine compound having the structure a first silicone compound having the structure a second silicone compound having the structure The resin composition may be used in display panels.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: November 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hi-Kuk Lee, Yako Yuko, Kyu-Young Kim
  • Patent number: 7297466
    Abstract: An organic anti-reflective coating (ARC) is formed over a surface of a semiconductor substrate, and a resist layer including a photosensitive polymer is formed on the ARC. The photoresistive polymer contains a hydroxy group. The resist layer is then subjected to exposure and development to form a resist pattern. The resist pattern to then silylated to a given depth by exposing a surface of the resist pattern to a vapor phase organic silane mixture of a first organic silane compound having a functional group capable of reacting with the hydroxy group of the photoresistive polymer, and a second organic silane compound having two functional groups capable of reacting with the hydroxy group of the photoresistive polymer Then, the silylated resist pattern is thermally treated, and the organic ARC is an isotropically etched using the thermally treated resist pattern as an etching mask.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: November 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-ho Lee, Sang-gyun Woo, Yun-sook Chae, Ji-soo Kim
  • Patent number: 7294453
    Abstract: Disclosed are methods of manufacturing electronic devices, particularly integrated circuits. Such methods include the use of low dielectric constant material prepared by using a removable porogen material.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: November 13, 2007
    Assignee: Shipley Company, L.L.C.
    Inventors: Michael K. Gallagher, Yujian You
  • Patent number: 7291446
    Abstract: During pattern transfer to a film stack, the hard mask layer, such as a tunable etch resistant antireflective coating (TERA), is consumed when etching the underling layer(s), leading to reduced etch performance and potential damage to the underlying layer(s), such as lack of profile control. A method of and system for preparing a structure on a substrate is described comprising: preparing a film stack comprising a thin film, a hard mask formed on the thin film, and a layer of light-sensitive material formed on the hardmask; forming a pattern in the layer of light-sensitive material; transferring the pattern to the hard mask; removing the layer of light-sensitive material; treating the surface layer of the hard mask in order to modify the surface; and transferring the pattern to the thin film.
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: November 6, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Aelan Mosden, Dung Phan
  • Patent number: 7285781
    Abstract: A CD-SEM (critical dimension-scanning electron microscope) system may utilize a technique for characterizing and reducing shrinkage carryover due to CD-SEM measurements. The system may identify the affects of CD-SEM measurements on the resist and adjust the operating parameters for a particular resist to avoid or significantly reduce shrinkage carryover. In this manner, the system may obtain more reliable CD measurements and avoid damage to the measured feature.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: October 23, 2007
    Assignee: Intel Corporation
    Inventors: Gary X. Cao, George Chen, Brandon L. Ward, Nancy J. Wheeler, Alan Wong
  • Patent number: 7223526
    Abstract: A method of forming an integrated circuit using an amorphous carbon film. The amorphous carbon film is formed by thermally decomposing a gas mixture comprising a hydrocarbon compound and an inert gas. The amorphous carbon film is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the amorphous carbon film is used as a hardmask. In another integrated circuit fabrication process, the amorphous carbon film is an anti-reflective coating (ARC) for deep ultraviolet (DUV) lithography. In yet another integrated circuit fabrication process, a multi-layer amorphous carbon anti-reflective coating is used for DUV lithography.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: May 29, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Kevin Fairbairn, Michael Rice, Timothy Weidman, Christopher S Ngai, Ian Scot Latchford, Christopher Dennis Bencher, Yuxiang May Wang
  • Patent number: 7211371
    Abstract: A method of manufacturing a TFT array panel for a LCD disclosers that the gate electrode wiring, transparent conducting electrode, and the first electrode of the storage capacity are formed while the first mask is processing. Then, the selective deposition method is used to process the growth of the first metal wiring. This, therefore, can reduce the numbers of the mask processes. Further, the metal deposition with photo-resist lift-off step is used to implement the layout of the second metal wiring for the consequent transmission lines in the manufacturing process. Finally, the process of the passivation layer deposition is used to implement associated circuits of a TFT array panel for a LCD. The TFT array panel for a LCD for manufacturing circuits can simplify the manufacturing process and reduce the cost.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: May 1, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Chi-Shen Lee, Yung-Fu Wu, Chi-Lin Chen, Cheng-Chung Chen
  • Patent number: 7198886
    Abstract: A method of forming a pattern, which comprises forming a masking material layer on a surface of a working film by coating the surface with a solution of a mixture comprising an inorganic compound having a bond between an inorganic element and oxygen atom, and a volatile unit, volatilizing the volatile unit to thereby make the masking material layer porous, forming a resist layer on a surface of the masking material layer, patterning the resist film to form a resist pattern, dry-etching the masking material layer to thereby transfer the resist pattern to the masking material layer, thereby forming a masking material pattern, and dry etching the working film to thereby transfer the masking material pattern to the working film to thereby form a working film pattern.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: April 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Sato, Tsuyoshi Shibata, Junko Ohuchi, Yasunobu Onishi
  • Patent number: 7195716
    Abstract: An etching process is described. A material layer having a bottom anti-reflection coating (BARC) and a patterned photoresist layer thereon is provided. An etching step is performed to the BARC using the patterned photoresist layer as a mask. A cleaning step is performed to remove the polymer formed on the surface of the patterned photoresist layer. Thereafter, another etching step is performed to the material layer using the patterned photoresist layer as a mask.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: March 27, 2007
    Assignee: United Microelectronics Corp.
    Inventor: Pei-Yu Chou
  • Patent number: 7189640
    Abstract: A method of forming damascene structures. A substrate including a dielectric layer thereon is provided. The dielectric layer has a plurality of via holes. A gap filler is formed into each via hole. Subsequently, a first anti-reflective coating (ARC) film and a second ARC film are consecutively formed on the dielectric layer. A photoresist pattern for defining a trench pattern is formed on the second ARC film. Following that, an etching process is performed to remove an upper part of the dielectric layer left uncovered by the photoresist pattern to form a plurality of trenches.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: March 13, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Jen Weng, Yu-Shiang Lin, Chih-Yi Cheng
  • Patent number: 7183036
    Abstract: Acid-catalyzed positive resist compositions which are imageable with 193 nm radiation (and possibly other radiation) at low energy levels are obtained using a polymer having acrylate/methacrylate monomeric units comprising a low activation energy moiety preferably attached to a naphthalene ester group. The resist allows the performance benefit of acrylate/methacrylate polymers with low activation energy for imaging thereby enabling improved resolution and reduced post-exposure bake sensitivity. The resist polymer also preferably contains monomeric units comprising fluoroalcohol moiety and a monomeric units comprising a lactone moiety.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: February 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Mahmoud Khojasteh, Kuang-Jung Chen, Pushkara Rao Varanasi
  • Patent number: 7169536
    Abstract: A manufacturing method for a field emission display includes the steps of (1) forming a conductive film on a substrate that is to be a base plate, the conductive film being for forming a cathode electrode; (2) applying, on the conductive film, a positive resist, which is a photosensitive material; (3) exposing the positive resist to light, so as to form openings that correspond in a shape of emitters, the light being (a) emitted from a light source, (b) paralleled so that rays thereof have even light intensity distribution, and (c) directed into a micro lens array so as to be condensed in interior of the photosensitive material; and (4) forming the emitters respectively in the openings. This arrangement provides a manufacturing method for a field emission display, the method capable of highly accurately and highly productively sharp emitters aligned orderly, without a complicate manufacturing step and a complicate optical system.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: January 30, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yukiko Nagasaka, Kazuya Kitamura, Toshihiro Tamura
  • Patent number: 7163778
    Abstract: There is disclosed an anti-reflection film material used in lithography containing at least a polymer compound having repeating units for copolymerization represented by the following general formula (1), or those containing a polymer compound having repeating units for copolymerization represented by the following general formula (2) and a polymer compound having repeating units for copolymerization represented by the following general formula (3).
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: January 16, 2007
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Jun Hatakeyama, Takafumi Ueda, Tsutomu Ogihara, Motoaki Iwabuchi
  • Patent number: 7160628
    Abstract: A substrate with a patterned opaque coating formable into an opaque aperture in one process is provided. The opaque coating includes at least a bottom layer and a top layer. The bottom and top layers each include a material selected from the group consisting of chrome and chrome oxide. The top layer has a compressive stress, which makes the opaque coating more resistant to pinhole formation during downstream processing.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: January 9, 2007
    Assignee: Corning Incorporated
    Inventors: Robert Bellman, Ljerka Ukrainczyk
  • Patent number: 7150956
    Abstract: The present invention provides a resist composition comprising (A) polyhydroxystyrene in which at least a portion of hydrogen atoms of hydroxyl groups are substituted with an acid-dissociable dissolution inhibiting group, and the solubility in an alkali solution of the polyhydroxystyrene increasing when the acid-dissociable dissolution inhibiting group is eliminated by an action of an acid, and (B) a component capable of generating an acid by irradiation with radiation, wherein a retention rate of the acid-dissociable dissolution inhibiting group of the component (A) after a dissociation test using hydrochloric acid is 40% or less, and also provides a chemical amplification type positive resist composition which contains polyhydroxystyrene in which at least a portion of hydrogen atoms of hydroxyl groups are substituted with a lower alkoxy-alkyl group having a straight-chain or branched alkoxy group, and the solubility in an alkali solution of the polyhydroxystyrene increasing when the lower alkoxy-alkyl group
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: December 19, 2006
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Kazuyuki Nitta, Takeyoshi Mimura, Satoshi Shimatani, Waki Okubo, Tatsuya Matsumi
  • Patent number: 7144686
    Abstract: A method of forming an active matrix organic light emitting display. A first photo mask is used to pattern a first scanning line, a bottom electrode and a second scanning line. A second photo mask is used to pattern a first island structure and a second island structure respectively within two predetermined TFT areas. A third photo mask is used to form a via to expose a part of the second scanning line outside the predetermined TFT area. A fourth photo mask is used to pattern a transparent conductive layer as a pixel electrode. A fifth photo mask is used to pattern a second metal layer as a data line and a top electrode, in which an opening is formed in the island structure to define a source/drain electrode and a source/drain diffusion region. A sixth photo mask is used to remove a protective layer from the pixel electrode.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: December 5, 2006
    Assignee: Au Optronics Corp.
    Inventors: Hsin-Hung Lee, Kuo-Ting Lee
  • Patent number: 7135272
    Abstract: In a method for forming a photoresist pattern, a method for forming a capacitor, and a capacitor manufactured using the same, a light is selectively irradiated onto a selected portion of a photoresist film formed on a substrate. An interfered light generated from the irradiated light is transmitted through other portions of the photoresist film except a ring-shaped portion of the photoresist film having a predetermined width along a boundary of the selected portion. The photoresist film is exposed using the interfered light and the light irradiated onto the selected portion. A cylindrical photoresist pattern having a minute width may be formed through developing the photoresist film. With the cylindrical pattern, the capacitor can be easily formed.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: November 14, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ihn-Gee Baik
  • Patent number: 7129026
    Abstract: This invention provides a lithographic process for multi-etching steps by using single reticle, wherein the develop step is performed next to a bake step after the photoresist layer has been exposed, such that a photoresist residue is formed on the peripheral region around a transformed pattern of the photoresist. Because the photoresist residue has thinner thickness compared to the photoresist layer, this kind of developed photoresist layer can be used as the very mask for multi-etching steps.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: October 31, 2006
    Assignee: Chungwha Picture Tubes, Ltd.
    Inventors: Da-Yo Liu, Chin-Tzu Kao, Jui-Chung Chang, Yi-Tsai Hsu
  • Patent number: 7125645
    Abstract: A composite photoresist structure includes an first organic layer located on a substrate, a sacrificial layer located on the first organic layer, and a second organic layer located on the sacrificial layer. The first organic layer is made of materials that can be easily removed by plasma. Therefore, the surface of the substrate will not be damaged while transferring a predetermined pattern onto the substrate.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: October 24, 2006
    Assignee: United Microelectronics Corp.
    Inventor: Jui-Tsen Huang
  • Patent number: 7107668
    Abstract: A photosensitive material is coated on an insulating material (13) stacked on a substrate (1) (FIG. 16A), and exposed and developed using a mask having a light-shielding film capable of controlling a light transmittance from 100% to 0% annularly and continuously to form a spiral photosensitive material (FIG. 16B). After conducting treatment at a high temperature, the insulating material under the photosensitive material is spirally formed by etching (FIG. 16C). A metal (12) is stacked on the substrate (FIG. 16D), and a photosensitive material is coated (FIG. 16E). The photosensitive material is exposed and developed using a mask having an annular light-shielding film with a light transmittance of 0% to leave the photosensitive material covering only the metal on the base of the spiral structure (FIG. 16F). After treatment at a high temperature is conducted and the metal exposed is etched (FIG. 16G), the photosensitive material is removed (FIG. 16H).
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: September 19, 2006
    Inventor: Takashi Nishi
  • Patent number: 7105279
    Abstract: During the patterning of a semiconductor layer, an N-free SiOx layer is produced under an acid-forming photoresist layer in order to prevent a resist degradation. The Si content of the grown SiOx layer being varied in order to set a desired extinction coefficient k and a desired refractive index n. The SiOx layer formation is effected by a vapor phase deposition, SiH4 and O2 being used as starting gases.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: September 12, 2006
    Assignee: Infineon Technologies AG
    Inventors: Mirko Vogt, Alexander Hausmann
  • Patent number: 7097958
    Abstract: A positive type, photosensitive epoxy resin composition comprising (a) an epoxy resin having two or more epoxy groups in one molecule, (b) a modified phenolic resin having a triazine ring, (c) a latent basic curing agent and (d) a photosensitive acid generator; and a preferably multilayered printed circuit board of buildup mode using said composition as an insulating layer.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: August 29, 2006
    Assignee: Huntsman Advanced Materials Americas Inc.
    Inventors: Yasuaki Sugano, Yasuharu Nojima
  • Patent number: 7096547
    Abstract: A manufacturing method for a ceramic device using a mixture with a photosensitive resin includes: providing a ceramic substrate, forming a lower electrode on the substrate using a mixture of a photosensitive resin and metal, masking and exposing the lower electrode to pattern the lower electrode, forming a piezoelectric/electrostrictive layer on the lower electrode using a mixture of photosensitive resin and piezoelectric/electrostrictive ceramic, masking and exposing the piezoelectric/electrostrictive layer to pattern the piezoelectric/electrostrictive layer, forming an upper electrode on the piezoelectric/electrostrictive layer using the mixture of photosensitive resin and metal, and exposing the upper electrode to pattern the upper electrode.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: August 29, 2006
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Kyeong Yun, Dong Hoon Kim, Sung June Park
  • Patent number: 7087356
    Abstract: Acid-catalyzed positive resist compositions which are imageable with 193 nm radiation and/or possibly other radiation and are developable to form resist structures of improved development characteristics and improved etch resistance are enabled by the use of resist compositions containing imaging polymer component comprising an acid-sensitive polymer having a monomeric unit with a pendant group containing a remote acid labile moiety.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: August 8, 2006
    Assignees: International Business Machines Corporation, JSR Corporation
    Inventors: Mahmoud H. Khojasteh, Kuang-Jung Chen, Pushkara Rao Varanasi, Yukio Nishimura, Eiichi Kobayashi
  • Patent number: 7083903
    Abstract: Methods of etching a carbon-rich layer on organic photoresist overlying an inorganic layer can utilize a process gas including CxHyFz, where y?x and z?0, and one or more optional components to generate a plasma effective to etch the carbon-rich layer with low removal of the inorganic layer. The carbon-rich layer can be removed in the same processing chamber, or alternatively can be removed in a different processing chamber, as used to remove the bulk photoresist.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: August 1, 2006
    Assignee: Lam Research Corporation
    Inventors: Erik A. Edelberg, Robert P. Chebi, Gladys Sowan Lo
  • Patent number: 7083899
    Abstract: Disclosed is a method for manufacturing a semiconductor device by employing a dual damascene process. After a first insulation film including a conductive pattern is formed on a substrate, at least one etch stop film and at least one insulation film are alternatively formed on the first insulation film. A via hole for a contact or a trench for a metal wiring is formed through the insulation film, and then the via hole or the trench is filled with a filling film including a water-soluble polymer. After a photoresist film is coated on the filling film, the photoresist film is patterned to form a photoresist pattern and to remove the filling film. The DOF and processing margin of the photolithography process for forming the photoresist pattern can be improved because the photoresist film can have greatly reduced thickness due to the filling film.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: August 1, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Cheol Kim, Dae-Youp Lee
  • Patent number: 7083901
    Abstract: A layer for use in a modular assemblage for supporting ICES is formed with metal contacts for assembly by making a sandwich of metal interconnect members between two layers of dielectric; drilling holes through the dielectric, stopping on a metal layer bonded to the bottom surface of the module; forming blind holes stopping on the interconnect members; and plating metal through the volume of the via, both full and blind holes, thereby forming vertical and horizontal connections in a layer that be stacked to form complex interconnect assemblies.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Frank D. Egitto, Voya Markovich, Thomas R. Miller, Douglas O. Powell, James R. Wilcox
  • Patent number: 7070907
    Abstract: The present invention provides a substrate-engraving-type chromeless phase-shift mask enabling to adopt a manufacturing method which poses no problem in quality, gives a high operating efficiency, and permits arrangement of characters and symbols, and a manufacturing method thereof. The substrate of the invention has a character/symbol section, on a surface of a transparent substrate, comprising characters and/or symbols engraved in the form of a slit-shaped or lattice-shaped pattern comprising concave grooves only in a prescribed portion corresponding to the characters and/or symbols.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: July 4, 2006
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Shigekazu Fujimoto, Masaaki Kurihara
  • Patent number: 7070911
    Abstract: A structure and method for reducing standing waves in a photoresist during manufacturing of a semiconductor is presented. Embodiments of the present invention include a method for reducing standing wave formation in a photoresist during manufacturing a semiconductor device comprising depositing a first anti-reflective coating having an extinction coefficient above a material, and depositing a second anti-reflective coating having an extinction coefficient above the first anti-reflective coating, such that the first anti-reflective coating and the second anti-reflective coating reduce the formation of standing waves in a photoresist during a lithography process.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: July 4, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dawn Hopper, Kouros Ghandehari, Minh Van Ngo
  • Patent number: 7070910
    Abstract: An adhesive compound for use with a photoresist, the compound represented in accordance with the following chemical formula, A method for forming a photoresist pattern using the adhesive compound is also disclosed.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: July 4, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Mi Kim, Yeu-Young Youn, Jae-Ho Kim, Young-Ho Kim, Shi-Yong Yi
  • Patent number: 7067894
    Abstract: Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic process is provided over the first anti-reflective coating, and a photosensitive material is provided above the transparent layer. The photosensitive material is exposed to a source of radiation including the wavelength of light. Preferably, the first anti-reflective coating extends beneath substantially the entire transparent layer. The complex refractive index of the first anti-reflective coating can be selected to maximize the absorption at the first anti-reflective coating to reduce notching of the photosensitive material.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: June 27, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Zhiping Yin
  • Patent number: 7049052
    Abstract: A method for etching a feature in a layer is provided. An underlayer of a polymer material is formed over the layer. A top image layer is formed over the underlayer. The top image layer is exposed to patterned radiation. A pattern is developed in the top image layer. The pattern is transferred from the top image layer to the underlayer with a reducing dry etch. The layer is etched through the underlayer, where the top image layer is completely removed and the underlayer is used as a pattern mask during the etching the layer to transfer the pattern from the underlayer to the layer.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: May 23, 2006
    Assignee: Lam Research Corporation
    Inventors: Hanzhong Xiao, Helen H. Zhu, Kuo-Lung Tang, S. M. Reza Sadjadi
  • Patent number: 7049051
    Abstract: The present invention describes a processes that builds an acoustic cavity, a chamber, and vent openings for acoustically connecting the chamber with the acoustic cavity. The dry etch processes may include reactive ion etches, which include traditional parallel plate RIE dry etch processes, advanced deep and inductively coupled plasma RIE processes. Three embodiments for connecting the chamber to the cavity from the top side of the substrate, e.g. by using pilot openings formed using at least a portion of the mesh as an etch mask, by forming the vent openings using at least a portion of the mesh as an etch mask, or by having the chamber intersect the vent openings as the chamber is being formed, illustrate how the disclosed process may be modified. By forming the cavity on the back side of the substrate, the depth of the vent holes is decreased. Additionally, using at least a portion of the micro-machined mesh as an etch mask for the vent holes makes the process self-aligning.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: May 23, 2006
    Assignee: Akustica, Inc.
    Inventors: Kaigham J. Gabriel, Xu Zhu
  • Patent number: 7045277
    Abstract: The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first material. An imagable material is formed on the second material, and patterned. A pattern is then transferred from the patterned imagable material to the first and second materials. The invention also includes a structure comprising a first layer of silicon nitride over a substrate, and a second layer on the first layer. The second layer comprises silicon and is free of nitrogen. The structure further comprises a third layer consisting essentially of imagable material on the second layer.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: May 16, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Scott Jeffrey DeBoer, John T. Moore
  • Patent number: 7045268
    Abstract: A photoresist composition having (A) at least two polymers selected from the group consisting of: (a) a fluorine-containing copolymer comprising a repeat unit derived from at least one ethylenically unsaturated compound characterized in that at least one ethylenically unsaturated compound is polycyclic; (b) a branched polymer containing protected acid groups, said polymer comprising one or more branch segment(s) chemically linked along a linear backbone segment; (c) fluoropolymers having at least one fluoroalcohol group having the structure: —C(Rf)(Rf?)OH wherein Rf and Rf? are the same or different fluoroalkyl groups of from 1 to about 10 carbon atoms or taken together are (CF2)n wherein n is 2 to 10;(d) amorphous vinyl homopolymers of perfluoro(2,2-dimethyl-1,3-dioxole or CX2?CY2 where X=F or CF3 and Y=H or amorphous vinyl copolymers of perfluoro(2,2-dimethyl-1,3-dioxole) and CX2?CY2; and (e) nitrile/fluoroalcohol-containing polymers prepared from substituted or unsubstituted vinyl ethers; and (B) at least
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: May 16, 2006
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: Larry L. Berger, Frank L. Schadt, III
  • Patent number: 7033729
    Abstract: Disclosed are a light absorbent agent polymer for organic anti-reflective coating which can prevent diffused reflection of lower film layer or substrate and reduce standing waves caused by variation of thickness of the photoresist itself, thereby, increasing uniformity of the photoresist pattern, in a process for forming ultra-fine patterns of photoresist for photolithography by using 193 nm ArF among processes for manufacturing semiconductor device, and its preparation method. Also, the present invention discloses an organic anti-reflective coating composition comprising the light absorbent agent polymer for the organic anti-reflective coating and a pattern formation process using the coating composition.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: April 25, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-chang Jung, Keun Kyu Kong, Seok-kyun Kim
  • Patent number: 7022463
    Abstract: A near-field photoresist for formation of a fine pattern with by near-field exposure includes an alkali-soluble novalac resin, a diazyde-type photosensitizer which is photoreactive by near-field exposure, a photoacid generator which generates acid by the near-field exposure, and a solvent.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: April 4, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takako Yamaguchi, Ryo Kuroda
  • Patent number: 7018781
    Abstract: Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: March 28, 2006
    Assignee: Infineon Technologies, AG
    Inventors: Hans-Georg Fröhlich, Oliver Genz, Werner Graf, Stefan Gruss, Matthias Handke, Percy Heger, Lars Heineck, Antje Laessig, Alexander Reb, Kristin Schupke, Momtchil Stavrev, Mirko Vogt
  • Patent number: 7018780
    Abstract: A method for controlling a removal of photoresist material from a semiconductor substrate is provided. The method includes providing the semiconductor substrate having a photoresist mask formed thereon. The method also includes forming a conformal layer of polymer over the photoresist mask and a portion of the semiconductor substrate not covered by the photoresist mask while concurrently removing a portion of the conformal layer of polymer. The thickness of the conformal layer of polymer on each region of the semiconductor substrate is set to vary depending on a removal rate of the conformal layer of polymer in each region of the semiconductor substrate.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: March 28, 2006
    Assignee: Lam Research Corporation
    Inventors: Vahid Vahedi, Linda B. Braly
  • Patent number: 7011929
    Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: March 14, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Ta Lei, Yih-Shung Lin, Ai-Sen Liu, Cheng-Chung Lin, Baw-Ching Perng, Chia-Hui Lin
  • Patent number: 7008755
    Abstract: In a method for forming a planarized layer on a semiconductor device having concave and convex structures, a dielectric film is formed on a semiconductor substrate; a photoresist pattern is formed to have a thickness on a portion of the dielectric film other than a convex portion greater than h/n (h and n are real numbers of one or more) to remove the convex portion of the dielectric film by a depth of approximately h. The photoresist pattern is re-flowed to have a thickness below h/n at a portion from an edge of the convex portion to a slant portion of the dielectric film. The dielectric film is etched using an etchant having a selectivity of 1:n between the photoresist pattern and the dielectric film. An edge of the photoresist pattern is made thin by re-flowing thereby minimizing a pillar, hence allowing simple, fast, planarization of the dielectric film.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: March 7, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Jong Park, In-Seak Hwang, Tae-Won Kim
  • Patent number: 7008866
    Abstract: Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: March 7, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co Ltd.
    Inventors: Ming-Jie Huang, Shu-Chih Yang, Huan-Just Lin, Yung-Tin Chen, Hun-Jan Tao
  • Patent number: 7001713
    Abstract: A method of forming a partial reverse active mask. A mask pattern comprising a large active region pattern with an original dimension and a small active region pattern is provided. The large active region pattern and the small active region pattern are shrunk until the small active region pattern disappears. The large active region pattern enlarged to a dimension slightly smaller than the original dimension.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: February 21, 2006
    Assignee: United Microelectronics, Corp.
    Inventors: Coming Chen, Juan-Yuan Wu, Water Lur
  • Patent number: 6998216
    Abstract: In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: February 14, 2006
    Assignee: Intel Corporation
    Inventors: Jun He, Jihperng Leu
  • Patent number: 6994946
    Abstract: Novel silicon-containing polymers are provided comprising recurring units having a POSS pendant and units which improve alkali solubility under the action of an acid. Resist compositions comprising the polymers are sensitive to high-energy radiation and have a high sensitivity and resolution at a wavelength of up to 300 nm and improved resistance to oxygen plasma etching.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: February 7, 2006
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Jun Hatakeyama, Takanobu Takeda
  • Patent number: 6994945
    Abstract: Novel silicon-containing polymers are obtained by copolymerizing a vinylsilane monomer with a compound having a low electron density unsaturated bond such as maleic anhydride, maleimide derivatives or tetrafluoroethylene. Using the polymers, chemical amplification positive resist compositions sensitive to high-energy radiation and having a high sensitivity and resolution at a wavelength of less than 300 nm and improved resistance to oxygen plasma etching are obtained.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: February 7, 2006
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Takanobu Takeda, Jun Hatakeyama, Toshinobu Ishihara, Tohru Kubota, Yasufumi Kubota