Abstract: Method and apparatus for etching a metal layer disposed on a substrate, such as a photolithographic reticle, are provided. In one aspect, a method is provided for processing a photolithographic reticle including positioning the reticle on a support member in a processing chamber, wherein the reticle comprises a metal photomask layer formed on a silicon-based substrate, and a patterned resist material deposited on the silicon-based substrate, etching the substrate with an oxygen-free processing gas, and then etching the substrate with an oxygen containing processing gas.

Abstract: A negative resist composition is disclosed, wherein the resist composition includes a polymer having at least one fluorosulfonamide monomer unit having one of the following two formulae: wherein: M is a polymerizable backbone moiety; Z is a linking moiety selected from the group consisting of —C(O)O—, —C(O)—, —OC(O)—, —O—C(O)—C(O)—O—, or alkyl; P is 0 or 1; R1 is a linear or branched alkyl group of 1 to 20 carbons; R2 is hydrogen, fluorine, a linear or branched alkyl group of 1 to 6 carbons, or a semi- or perfluorinated linear or branched alkyl group of 1 to 6 carbons; and n is an integer from 1 to 6.

Abstract: Compositions suitable for forming planarizing underlayers for multilayer lithographic processes are characterized by the presence of (A) a polymer containing: (i) cyclic ether moieties, (ii) saturated polycyclic moieties, and (iii) aromatic moieties for compositions not requiring a separate crosslinker, or (B) a polymer containing: (i) saturated polycyclic moieties, and (ii) aromatic moieties for compositions requiring a separate crosslinker. The compositions provide outstanding optical, mechanical and etch selectivity properties. The compositions are especially useful in lithographic processes using radiation less than 200 nm in wavelength to configure underlying material layers.

Abstract: A method of etching a noble metal electrode layer disposed on a substrate to produce a semiconductor device including a plurality of electrodes separated by a distance equal to or less than about 0.35 ?m and having a noble metal profile equal to or greater than about 80°. The method comprises heating the substrate to a temperature greater than about 150° C., and etching the noble metal electrode layer by employing a high density inductively coupled plasma of an etchant gas comprising a gas selected from the group consisting of nitrogen, oxygen, a halogen (e.g., chlorine), argon, and a gas selected from the group consisting of BCl3, HBr, and SiCl4 mixtures thereof. Masking methods and etching sequences for patterning high density RAM capacitors are also provided.

Abstract: A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.

Abstract: The invention provides a method for making ink feed vias in semiconductor silicon substrate chips for an ink jet printhead and ink jet printheads containing silicon chips made by the method. The method includes applying a first photoresist material to a first surface side of the chip. The first photoresist material is patterned and developed to define at least one ink via location therein. An etch stop material is applied to a second surface side of the chip. At least one ink via is anisotropically etched with a dry etch process through the thickness of the silicon chip up to the etch stop layer from the first surface side of the chip. As opposed to conventional ink via formation techniques, the method significantly improves the throughput of silicon chip and reduces losses due to chip breakage and cracking. The resulting chips are more reliable for long term printhead use.

Abstract: A method for exposing a semiconductor wafer in an exposer includes applying a first resist layer on a layer covering an alignment mark. A microscope measuring instrument, which has a visible and an ultraviolet light source, uses the visible light source for aligning the wafer and uses the ultraviolet light source for exposing a region in the first resist layer above the alignment mark without using a mask to free expose the alignment marks. The semiconductor wafer is then developed, the alignment mark is etched free and covered again with a second resist, which is exposed in an exposer in order to transfer a mask structure following an alignment with the alignment mark. The capacity of expensive exposers is thus advantageously increased, and microscope measuring instruments can be used multifunctionally, for example for the free exposure and for the detection of defects.

Abstract: A photosensitive composition for sandblasting comprising the components of: (A) a photopolymerizable urethane (meth)acrylate oligomer comprising (meth)acryloyl group; (B) an acrylic copolymer; and (C) a photopolymerization initiator, wherein the component (B) comprises, as a monomer unit, one of copolymerizable monomers comprising one of a benzene ring and a cyclohexyl group.

Abstract: A hybrid photolithography process for printed circuit board patterning combines two types of photoresist applications to achieve superior protection of printed circuit board (PCB) ‘plated through holes’ (PTH). In a first step, electro-deposited (ED) photoresist (also known as “ED resist”) is applied to a fully copper plated PCB including the ‘plated through holes’ to protect the outer layers and the ‘plated through holes’ from copper etchant solution. In a second step, the electro-deposited photoresist is imaged (exposed) and patterned (developed). In a third step, after developing the circuit image, a layer of Dry Film resist is applied to the panel of the PCB on top of the developed electro-deposited (ED) photoresist. This Dry Film resist layer will ‘tent’ the plated through holes by adding an extra layer of protection to the plated through holes. In a fourth step, the dry film resist is then exposed and developed. At this point, the PCB is etched as normal and all subsequent processing remains unchanged.

Abstract: A method of forming a resist pattern film. A positive type actinic ray decomposing and developing dry film is applied onto a surface of a coating substrate so that the surface of the coating substrate may face to the urethane resin layer of the dry film. Then, the dry film may be heat treated. The non-actinic ray-curable substrate of the dry film, then, is optionally stripped, and is heat treated if it has not already been heat treated. Then, an actinic ray is irradiated through a mask or directly onto the surface of the dry film so as to obtain an intended pattern and is optionally heat treated. The non-actinic ray-curable substrate which was not previously stripped is, then, stripped. Then, the positive type actinic ray-curable urethane resin layer is subjected to a developing treatment. Finally, an unnecessary area of the urethane resin layer to form a resist pattern film is removed.

Abstract: A manufacturing method for a metal electrode used for a bus electrode, a data electrode, and the like which make up a display panel including a PDP (Plasma Display Panel) by which, when these electrodes are patterned according to a photolithographic method, the edge curl phenomenon can be substantially controlled to the extent that the phenomenon is negligible. The manufacturing method of the invention therefore includes a dry step for drying the layers making up the metal electrode so that flows (F1, F2, and F3) of the solvent occur from a region having a high absorbency of the solvent to a region having a lower absorbency of the solvent.

Abstract: A full phase shifting mask (FPSM) can be advantageously used in a damascene process for hard-to-etch metal layers. Because the FPSM can be used with a positive photoresist, features on an original layout can be replaced with shifters on a FPSM layout. Adjacent shifters should be of opposite phase, e.g. 0 and 180 degrees. In one embodiment, a dark field trim mask can be used with the FPSM. The trim mask can include cuts that correspond to cuts on the FPSM. Cuts on the FPSM can be made to resolve phase conflicts between proximate shifters. In one case, exposing two proximate shifters on the FPSM and a corresponding cut on the trim mask can form a feature in the metal layer. The FPSM and/or the trim mask can include proximity corrections to further improve printing resolution.

Abstract: A negative pattern is formed to be transparent in the far ultraviolet region including the wavelength 193 nm of an ArF excimer laser and, despite its chemical structure having high dry etching, does not swell and has excellent resolution. An acid-catalyzed reaction is utilized wherein a ?-hydroxy or ?-hydroxy carboxylic acid structure is partially or entirely converted to a ?-lactone or ?-lactone structure. The negative pattern is developed with an aqueous alkali solution without swelling.

Abstract: A method for adjusting and exposing the second level of a phase-shift mask includes the steps of depositing a thin conductive layer over a photoresist layer only on the alignment structures and their surroundings, and covering the chip structures exposed in the first step in a suitable way by a covering for the purpose of depositing the thin conductive layer. Grounding the thin conductive layer means that no charging of the substrate takes place during alignment by an electron-beam writer.

Abstract: A negative resist composition, comprising: (a) silicon-containing polymer with pendant fused moieties selected from the group consisting of fused aliphatic moieties, homocyclic fused aromatic moieties, and heterocyclic fused aromatic and sites for reaction with a crosslinking agent, (b) an acid-sensitive crosslinking agent, and (c) a radiation-sensitive acid generator is provided. The resist composition is used to form a patterned material layer in a substrate.

Abstract: A photolithographic process forms patterns on HgI2 surfaces and defines metal sublimation masks and electrodes to substantially improve device performance by increasing the realizable design space. Techniques for smoothing HgI2 surfaces and for producing trenches in HgI2 are provided. A sublimation process is described which produces etched-trench devices with enhanced electron-transport-only behavior.

Abstract: One aspect of the present invention relates to a system and method for mitigating LER as it may occur on short wavelength photoresists. The method involves forming a short wavelength photoresist over a substrate having at least one dielectric layer formed thereon, exposing the photoresist to a plasma selective to the photoresist to strengthen the photoresist without substantially etching the at least one dielectric layer, the plasma comprising hydrogen, helium and argon, and etching the dielectric layer through openings of the strengthened photoresist with an etchant selective to the at least one dielectric layer, whereby the treated photoresist is substantially resistant to etching effects of the etchant. The system includes a photoresist monitor system for monitoring the plasma treatment to determine whether the photoresist has been strengthened and for adjusting parameters associated with the plasma treatment and for providing feedback to the plasma treatment system.

Abstract: Present invention provides an aqueous emulsion type photosensitive resin composition which forms a cured film significantly superior in water and solvent resistances in comparison with the conventional aqueous emulsion type photosensitive resin compositions. This photosensitive resin composition contains (A) an emulsion of a photosensitive water-insoluble polymer, the emulsion being obtained by reacting (i) an aqueous polymer emulsion whose main ingredient is a water-insoluble polymer and which contains a polymer having a hydroxyl group with (ii) an N-alkylol(meth)acrylamide, (B) a compound having a photoreactive ethylenically unsaturated group, and (C) a photopolymerization initiator.

Abstract: A process for massively producing tape type flexible printed circuits is provided. The steps of pressing, etching and insulating are executed on a flexible insulation tape in reel-to-reel fashion. Thereafter, the flexible insulation tape is punched to form sprocket holes and cut along the parallel lines where the sprocket holes arrange on to become several winds of narrower flexible circuit tapes. Each flexible circuit tape has tape type flexible printed circuits and sprocket holes at two sides.

Abstract: An etching mask is produced for etching a substrate by a photoresist layer being exposed such that areas which are exposed once are not yet completely exposed and, on the basis of a reflective layer which is located under the photoresist layer, additionally exposed areas are exposed completely. In consequence, a first etching mask which is used for etching a substrate can be renewed by a second etching mask in that a photoresist layer which is applied to the first etching mask or instead of the first etching mask is exposed such that areas which have been exposed once are not yet completely exposed, and areas which have been additionally exposed on the basis of a reflective layer which is located under the photoresist layer and corresponds to the first etching mask are exposed completely.

Abstract: A method for forming a conductive trace on a substrate. The conductive trace is patterned with a photoresist mask and etched, thereby forming a polymer layer on a top surface and sidewalls of the photoresist mask and on sidewalls of the conductive trace. The polymer layer contains entrained chlorine gas. The substrate is heated on a chuck in a reaction chamber. A remote plasma is generated from ammonia gas and oxygen gas. The substrate is contacted with the ammonia and oxygen plasma, thereby withdrawing a substantial portion of the entrained chlorine gas from the polymer layer. A radio frequency potential is applied to the chuck on which the substrate resides, thereby creating a reactive ion etchant from the ammonia and oxygen plasma in the reaction chamber and removing the polymer layer from the top surface of the photoresist mask. The photoresist mask is thus exposed, and then removed in an ashing process.

Abstract: A serialization process presents an efficient method of creating serial numbers on a ceramic-like semiconductor wafer by forming a non-rigid photomask that incorporates character specifications for the serial numbers. The non-rigid photomask is retained in a rigid, optically transparent photomask holder that enables the photomask to be handled as a rigid structure. Upon preparation of the wafer, the serial numbers are created onto wafer dies using a combined process involving photolithography, and a reactive ion etching process with a selective etch rate. The serialization process enables a rapid creation of serial numbers, with the selective RIE process substantially increasing the optical contrast of the characters without the need for deep trenches and without generation of excessive debris.

Abstract: A method for manufacturing a polysilicon type thin film transistor comprises the steps of forming a polysilicon layer on a substrate, forming a gate insulating layer on the polysilicon layer, forming a gate layer on the gate insulating layer, forming a gate pattern by patterning, implanting impurities in the substrate over which the gate pattern is formed, forming a cover layer over the substrate in which impurities are implanted, and thermally annealing the substrate over which the cover layer is formed. In the invention, the thermal annealing is carried out instead of a costly laser annealing after the impurity implantation.

Abstract: A method for improving the resolution of optic lithographic is disclosed. The method includes a step of forming an etched layer on the substrate, an inorganic photoresist layer is spun-on the etched layer, and an atomic layer on the inorganic photoresist layer. Then, a deep ultraviolet light is illuminated to the inorganic photoresist layer such that the acid molecular is formed from inorganic photoresist layer. Next, the atomic layer is catalyzed by acid molecular and converted to metallic oxide by active oxygen atom. After oxidation, the oxide pattern can be obtained and it is easy by etching process.

Abstract: The invention provides a microfabrication process which may be used to manufacture a MEMS device. The process comprises depositing one or a stack of layers on a base layer, said one layer or an uppermost layer in said stack of layers being a sacrificial layer; patterning said one or a stack of layers to provide at least one aperture therethrough through which said base layer is exposed; depositing a photosensitive layer over said one or a stack of layers; and passing light through said at least one aperture to expose said photosensitive layer.

Abstract: The invention relates to a TFT-LCD high-performance stripper composition for a photoresist, and more particularly to a stripper composition for a photoresist comprising: 20-60 wt % of monoethanolamine, 15-50 wt % of N,N-dimethylacetamide, 15-50 wt % of carbitol, and 0.1-10 wt % of gallic acid. The invention also provides a stripper composition for a photoresist comprising: 20-60 wt % of monoethanolamine, 15-50 wt % of N,N-dimethylacetamide, and 15-50 wt % of carbitol. The stripper composition for a photoresist of the invention significantly reduces stripping time when applied to the TFT-LCD manufacturing process and leaves no impurity particles. By allowing the hard baking and ashing processes to be omitted, the gate process line can be simplified, which enables cost reduction. In addition, when it is applied to a process wherein silver (Ag) is used as reflective/transflective layer, it offers stripping ability and corrosion resistance of the pure Ag layer.

Abstract: In a disclosed method for manufacturing a semiconductor device, a lower insulating layer, a lower metal line and an upper insulating layer are sequentially stacked. A first photosensitive film is patterned on the upper insulating layer and the upper insulating layer is subsequently etched. The photosensitive film is removed. An etched portion of the upper insulating layer is then filled with a nitride film. The upper insulating layer is then removed. A second photosensitive film is then patterned and the lower metal line is subsequently etched. An IMD layer is deposited over the resultant construct, thereby forming an air gap within the IMD layer. The IMD layer is planarized. The nitride film is then etched away to thereby form a hole in the IMD layer. The hole is filled with a conductive material to form a contact plug. An upper metal line is deposited over the resultant construct.

Abstract: This invention provides a lithographic process for multi-etching steps by using single reticle, wherein the develop step is performed next to a bake step after the photoresist layer has been exposed, such that a photoresist residue is formed on the peripheral region around a transformed pattern of the photoresist. Because the photoresist residue has thinner thickness compared to the photoresist layer, this kind of developed photoresist layer can be used as the very mask for multi-etching steps.

Abstract: The present invention provides polymers which are substantially or completely free of inorganic contaminants and the use of such polymers as a resin component for photoresist compositions, particularly chemically-amplified positive-acting resists. Polymers of the invention also are suitable for use as a resin component for antireflective coating compositions (ARCs). More particularly, the invention provides methods for reducing such contaminants in polymerization initiators, particularly free radical initiators.

Abstract: The silicon-containing resist compositions which have low silicon outgassing and high resolution lithographic performance, especially in bilayer or multilayer lithographic applications using 193 nm or shorter wavelength imaging radiation are enabled by the presence of an imaging polymer having silicon-containing, non-acid-labile pendant groups. The resist compositions of the invention are preferably further characterized by the substantial absence of silicon-containing acid-labile moieties.

Abstract: Acid-catalyzed positive resist compositions suitable for bilayer or multilayer lithographic applications are enabled by the use of a combination of (a) an acid-sensitive imaging polymer, (b) a radiation-sensitive acid generator, and (c) a non-polymeric silicon additive. The imaging polymer is preferably imageable with 193 nm or shorter wavelength imaging radiation. The resist compositions preferably contain at least about 5 wt. % silicon based on the weight of the imaging polymer. The compositions generally provide reduced line edge roughness compared to conventional silicon-containing resists.

Abstract: A method of making an electrical current sensor having an electrical conducting portion (6; 6a, 6b) of rectangular cross-section being surrounded, on three of its lateral faces, by a magnetic circuit portion (7) which has end portions (7′, 7″) having planar surfaces situated substantially in a plane of a fourth lateral face of the conductor portion (6), a magnetic field detector (3; 24; 26) being arranged opposite the fourth lateral face. The conductor portion (6) is made by photo-lithography and etching in a layer of electrically conducting material applied on a first surface of a flat support member (1; 1′; 1″) or on intermediate layers (8, 9, 10, 11) deposited on the support member. The magnetic circuit portion (7) is made by photo-lithography and etching in a layer of magnetically permeable material applied on the conductor portion (6) on the first surface of the support member (1; 1′, 1″) or of an intermediate layer (8).

Abstract: Forming a protective layer such as chromium, chrome alloys, nickel or cobalt as a cap over an aluminum film protects an underlying ITO layer from corrosion during the fabrication of flat panel displays such as field emission devices and the like. The presence of the protective layer during fabrication processes such as photolithography prevents diffusion of solutions through the aluminum into the ITO. This protective layer is especially effective during the development and resist stripping stages of photolithography which use solutions or solvents that would otherwise cause reductive corrosion of ITO in contact with aluminum. The methods and apparatus described herein are particularly advantageous for the fabrication of flat panel displays such as field emission devices and other display devices, because ITO is often used in such devices in contact with aluminum while exposed to corrosion-inducing media.

Abstract: A polymer used for a negative type resist composition having a first repeating unit of a Si-containing monomer unit, a second repeating unit having a hydroxy group or an epoxy ring and copolymerized with the first repeating unit is provided.

Abstract: A process and related structure are disclosed for using photo-definable layers that may be selectively converted to insulative materials in the manufacture of semiconductor devices, including for example dynamic random access memories (DRAMs), synchronous DRAMs (SDRAMs), static RAMs (SRAMs), FLASH memories, and other memory devices. One possible photo-definable material for use with the present invention is plasma polymerized methylsilane (PPMS), which may be selectively converted into photo-oxidized siloxane (PPMSO) through exposure to deep ultra-violet (DUV) radiation using standard photolithography techniques. According to the present invention, structures may be formed by converting exposed portions of a photo-definable layer to an insulative material and by using the non-exposed portions in a negative pattern scheme, or the exposed portions in a positive pattern scheme, to transfer a pattern into to an underlying layer.

Abstract: The invention includes methods of fabricating integrated circuitry and semiconductor processing polymer residue removing solutions. In one implementation, a method of fabricating integrated circuitry includes forming a conductive metal line over a semiconductor substrate. The conductive line is exposed to a solution comprising an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. In one implementation, a method of fabricating integrated circuitry includes forming an insulating layer over a semiconductor substrate. A contact opening is at least partially formed into the insulating layer. The contact opening is exposed to a solution comprising an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. In one implementation, a semiconductor processing polymer residue removing solution comprises an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. Other aspects and implementations are contemplated.

Abstract: A method of forming an electrical feature such as a 3-D circuit on a substrate is described. The method includes the following steps. A catalytic paint is first selectively deposited on the surface of a molded polymer substrate to form a paint coating of the substrate. A conductive metal such as copper or nickel is then deposited onto the coating to form a plating of the substrate. An electrical feature is then obtained by forming a precision conductive pattern in the conductive metal.

Abstract: Through holes are formed at four peripheral edges of a plurality of semiconductor chip placement regions of an insulating substrate, except for coupling portions partially arranged thereat. A substrate sheet for semiconductor module is used in which connecting portions between inner lead portions and outer lead portions arranged on both surfaces of the substrate are formed in pattern on the side wall surface of the through hole. The semiconductor chip is mounted on each region, electrode terminals thereof and the inner lead portions are electrically connected to each other, the chip is sealed, and then the coupling portions are cut.

Abstract: A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.

Abstract: The invention concerns a method for making an multilevel interconnection circuitry comprising conductor tracks and micro-vias. The method for producing at least one of the levels comprises the following steps: a) on a substrate including at its surface metallizable and/or potentially metallizable parts (102), forming a first insulating photosensitive resin layer (103) comprising a compound capable of inducing subsequent metallization; b) exposing and revealing the first layer (103) so as to selectively uncover the metallizable and/or potentially metallizable parts (102) of the substrate; c) forming, by metallization, metal conductor tracks (111) and micro-vias (110) at the surface of the first insulating photosensitive resin layer (113) and of the parts uncovered during step b), by providing a second photosensitive resin layer (105) forming a selective protection, the second photosensitive resin layer (105) being eliminated.

Abstract: It is an object to provide a manufacturing process for a printed wiring board in which a copper foil and resin as a substrate material of a copper clad laminate are irradiated with carbon dioxide gas laser light to drill in both of them simultaneously. In forming a through hole or a hole such as IVH, BVH or the like in the copper clad laminate using carbon dioxide gas laser light, one of a nickel layer of 0.08 to 2 &mgr;m in thickness, a cobalt layer of 0.05 to 3 &mgr;m in thickness and a zinc layer of 0.03 to 2 &mgr;m in thickness is formed as an additional metal layer on a surface of the copper foil residing in an external layer of the copper clad laminate and thereafter, by performing laser drilling, the copper foil layer and the resin layer as a substrate material of the copper clad laminate are enabled to drill simultaneously.

Abstract: A process is described for trimming photoresist patterns during the fabrication of integrated circuits for semiconductor devices and MEMS devices. A combination of a low temperature (<20° C.), high density oxygen and argon plasma and intense UV radiation is used to simultaneously trim and harden a photoresist linewidth in an ICP chamber. As an alternative, a UV hardening step can be performed in a flood exposure tool prior to the ICP plasma etch. Another option is to perform the argon plasma treatment first to harden the resist and then in a second step apply an oxygen plasma to trim the photoresist. Vertical and horizontal etch rates are decreased in a controllable manner which is useful for producing gate lengths in MOS transistors of less than 100 nm. The process can also be used to controllably increase a space width in a photoresist feature.

Abstract: Disclosed herein is a method for inductor An Improved Structure For the Endpiece of Tape Rule of the high frequency integrated passive devices in which a spiral inductor pattern is formed on an insulation substrate, the spiral inductor pattern is spirally coiled outwards from the center. A thick film dielectric layer made of bisbenzocyclobutene (BCB) is formed on the spiral inductor pattern. A metal layer can be formed according to under bump metallization technique (UBM). The metal layer is either formed into a continuous spirally coiled form or a spread discrete configuration. With this structure, laser trimming can be applied to the metal layer pattern so as to acquire an ideal inductance value, thereby achieving wafer level trimming and compensating the process tolerance.

Abstract: A composition for stripping photoresist, methods of preparing and forming the same, a method of manufacturing a semiconductor device using the composition, and a method of removing a photoresist pattern from an underlying layer using the composition, where the composition may include an ethoxy N-hydroxyalkyl alkanamide represented by the formula, CH3CH2—O—R3—CO—N—R1R2OH, an alkanolamine and a polar material. Raw materials of alkyl alkoxy alkanoate, represented by a chemical formula of R4—O—R3—COOR5, and alkanolamine, represented by a chemical formula of NHR1R2OH, may be mixed to form a mixture, which is stirred and cooled to obtain the composition. The composition may balance exfoliation and dissolution of photoresist patterns, and may potentially eliminate thread-type residues from remaining on a surface of an underlying layer after removing the photoresist patterns.

Abstract: Supports (3) are formed to be arrayed on a support base (1), a sacrifice layer (15) is formed of a resin material, and the sacrifice layer (15) is planarized so as to expose the top of the respective supports (3), thereby forming a thin-film substrate (5) on top of the sacrifice layer (15) as planarized, and the supports (3). The sacrifice layer (15) is removed by plasma selective etching thereof through the intermediary of the thin-film substrate, and thereby a large-area thin-film substrate (5) floatingly spaced by a space (7) away from the support base (1) can be fabricated.

Abstract: Resist residues, which is formed in a process of forming Al interconnections, are removed through use of a single chemical. A chemical which contains an organic acid or a salt thereof and water and which has a pH below 8 is used as a treatment for removing resist or resist residues. The chemical may be used in a process in which Al, W, Ti, TiN, and SiO2 are exposed on the surface of a wafer after etching of an Al interconnection; in a process in which Al, W, Ti, TiN, and SiO2 are exposed on the surface of a wafer after etching a hole reaching an Al interconnection in an dielectric layer; in a process in which Cu is exposed on the surface of a semiconductor wafer after dry-etching of a Cu interconnection or etching of an interlayer dielectric film laid on a Cu interconnection; and in a process in which metal material such as W, WN, Ti, or TiN; poly-Si; SiN; and SiO2 are exposed on the surface of a wafer after etching of a metal gate.

Abstract: In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.

Abstract: A negative resist composition, comprising:

Abstract: A method of forming a conductive circuit pattern on a circuit board having a first region, on which a desired conductive circuit pattern is to be formed, and a second region. The method includes the step of applying a coating including a solution with conductive particles to the circuit board. The coating is heated to adhere the conductive particles to the circuit board. The conductive particles are removed in the second region. The second region is shielded and, with the second region shielded, a conductive film is formed on the first region.

Abstract: A technique for etching with a single layered patterned photomask at wavelengths of 193 nanometers or less. Specifically, a method for etching a bottom anti-reflectant coating layer that utilizes a combination of CF4, CH2F2, and O2 to produce a stabilized pattern in the photoresist layer. The etching process results in a structure with a defined pattern having minimal defects and that maintains integrity through the remainder of the etching.