Having Selenium Or Tellurium Elemental Semiconductor Component Patents (Class 438/102)
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Patent number: 8716060Abstract: Confined resistance variable memory cell structures and methods are described herein. One or more methods of forming a confined resistance variable memory cell structure includes forming a via in a memory cell structure and forming a resistance variable material in the via by performing a process that includes providing a germanium amidinate precursor and a first reactant to a process chamber having the memory cell structure therein and providing an antimony ethoxide precursor and a second reactant to the process chamber subsequent to removing excess germanium.Type: GrantFiled: May 14, 2013Date of Patent: May 6, 2014Assignee: Micron Technology, Inc.Inventors: Brenda D. Kraus, Eugene P. Marsh, Timothy A. Quick
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Patent number: 8710478Abstract: Provided is a resistance change type nonvolatile semiconductor storage device including a diode capable of passing therethrough a sufficient current to a resistance changing operation even when the memory cell is miniaturized. A nonvolatile semiconductor storage device has first wires extending in X direction, second wires extending in Y direction, and memory cells disposed at intersection points of the first wires and the second wires. The memory cell includes a diode disposed over the first wire, and coupled to the first wire at one end, and a resistance change part disposed over the diode, and series-coupled to the diode at one end, and coupled to the second wire at the other end, and storing information through changes in resistance value. The diode includes a first conductivity type first semiconductor layer, and a second conductivity type second semiconductor layer extending into the inside of the first semiconductor layer.Type: GrantFiled: May 17, 2012Date of Patent: April 29, 2014Assignee: Renesas Electronics CorporationInventor: Yukihiro Sakotsubo
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Patent number: 8709548Abstract: A method of making a sputtering target includes providing a backing structure, and forming a copper indium gallium sputtering target material on the backing structure by spray forming.Type: GrantFiled: October 19, 2010Date of Patent: April 29, 2014Assignee: Hanergy Holding Group Ltd.Inventors: A. Piers Newbery, Timothy Kueper, Daniel R. Juliano
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Patent number: 8709856Abstract: In particular embodiments, a method is described for forming photovoltaic devices that includes providing a substrate suitable for use in a photovoltaic device, depositing a conductive contact layer over the substrate, depositing a salt solution over the surface of the conductive contact layer, the solution comprising a volatile solvent and an alkali metal salt solute, and depositing a semiconducting absorber layer over the solute residue left by the evaporated solvent.Type: GrantFiled: March 4, 2010Date of Patent: April 29, 2014Assignee: Zetta Research and Development LLC—AQT SeriesInventors: Brian Josef Bartholomeusz, Michael Bartholomeusz
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Patent number: 8709834Abstract: A method of manufacturing a semiconductor device includes providing a wafer, forming a memory device which includes phase change material layer on the wafer, completing a wafer level process of manufacturing the semiconductor device, and performing a thermal treatment process on the wafer to densify the phase change material. To this end, the process temperature of the thermal treatment is higher than the crystallization temperature of the phase change material and lower than the melting point of the phase change material.Type: GrantFiled: March 5, 2012Date of Patent: April 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hyun Hong, Jung-Hyuk Lee, Su-Jin Ahn, Dae-Won Ha
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Patent number: 8709863Abstract: Antimony, germanium and tellurium precursors useful for CVD/ALD of corresponding metal-containing thin films are described, along with compositions including such precursors, methods of making such precursors, and films and microelectronic device products manufactured using such precursors, as well as corresponding manufacturing methods. The precursors of the invention are useful for forming germanium-antimony-tellurium (GST) films and microelectronic device products, such as phase change memory devices, including such films.Type: GrantFiled: September 18, 2012Date of Patent: April 29, 2014Assignee: Advanced Technology Materials, Inc.Inventors: William Hunks, Tianniu Chen, Chongying Xu, Jeffrey F. Roeder, Thomas H. Baum, Matthias Stender, Philip S. H. Chen, Gregory T. Stauf, Bryan C. Hendrix
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Patent number: 8703588Abstract: A phase change material including a high adhesion phase change material formed on a dielectric material and a low adhesion phase change material formed on the high adhesion phase change material. The high adhesion phase change material includes a greater amount of at least one of nitrogen and oxygen than the low adhesion phase change material. The phase change material is produced by forming a first chalcogenide compound material including an amount of at least one of nitrogen and oxygen on the dielectric material and forming a second chalcogenide compound including a lower percentage of at least one of nitrogen and oxygen on the first chalcogenide compound material. A phase change random access memory device, and a semiconductor structure are also disclosed.Type: GrantFiled: January 11, 2012Date of Patent: April 22, 2014Assignee: Micron Technology, Inc.Inventor: Keith R. Hampton
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Patent number: 8704203Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 ? and about 100 ?, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.Type: GrantFiled: August 20, 2013Date of Patent: April 22, 2014Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, Sandisk 3D LLCInventors: Hieu Pham, Vidyut Gopal, Imran Hashim, Tim Minvielle, Yun Wang, Takeshi Yamaguchi, Hong Sheng Yang
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Patent number: 8703524Abstract: A solar cell includes an absorber layer formed of a CIGAS, copper, indium, gallium, aluminum, and selenium. A method for forming the absorber layer provides for using an indium-aluminum target and depositing an aluminum-indium film as a metal precursor layer using sputter deposition. Additional metal precursor layers such as a CuGa layer are also provided and a thermal processing operation causes the selenization of the metal precursor layers. The thermal processing operation/selenization operation converts the metal precursor layers to an absorber layer. In some embodiments, the absorber layer includes a double graded chalcopyrite-based bandgap.Type: GrantFiled: November 29, 2012Date of Patent: April 22, 2014Assignee: TSMC Solar Ltd.Inventors: Wen-Tsai Yen, Chung-Hsien Wu, Shih-Wei Chen, Wen-Chin Lee
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Patent number: 8697480Abstract: Methods for treating a semiconductor material, and for making devices containing a semiconducting material, are presented. One embodiment is a method for treating a semiconductor material that includes a chalcogenide. The method comprises contacting at least a portion of the semiconductor material with a chemical agent. The chemical agent comprises a solvent, and an iodophor dissolved in the solvent.Type: GrantFiled: November 21, 2012Date of Patent: April 15, 2014Assignee: First Solar, Inc.Inventor: Donald Franklin Foust
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Patent number: 8697486Abstract: A method of forming a phase change material which having germanium and tellurium therein includes depositing a germanium-containing material over a substrate. Such material includes elemental-form germanium. A gaseous tellurium-comprising precursor is flowed to the germanium-comprising material and tellurium is removed from the gaseous precursor to react with the elemental-form germanium in the germanium-comprising material to form a germanium and tellurium-comprising compound of a phase change material over the substrate. Other implementations are disclosed.Type: GrantFiled: April 15, 2009Date of Patent: April 15, 2014Assignee: Micro Technology, Inc.Inventors: Eugene P. Marsh, Timothy A. Quick, Stefan Uhlenbrock
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Patent number: 8691612Abstract: Provided is a method of enhancing thermoelectric performance by surrounding crystalline semiconductors with nanoparticles by contacting a bismuth telluride material with a silver salt under a substantially inert atmosphere and a temperature approximately near the silver salt decomposition temperature; and recovering a metallic bismuth decorated material comprising silver telluride crystal grains.Type: GrantFiled: March 5, 2012Date of Patent: April 8, 2014Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Hyun-Jung Kim, Sang Hyouk Choi, Glen C. King, Yeonjoon Park, Kunik Lee
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Patent number: 8692222Abstract: A nonvolatile memory element according to the present disclosure includes: a variable resistance element including a first electrode layer, a second electrode layer, and a variable resistance layer which is located between the first electrode layer and the second electrode layer and has a resistance value that reversibly changes based on an electrical signal applied between the first electrode layer and the second electrode layer; and a fixed resistance layer having a predetermined resistance value and stacked together with the variable resistance element. The variable resistance layer includes (i) a first transition metal oxide layer which is oxygen deficient and (ii) a second transition metal oxide layer which has a higher oxygen content atomic percentage than the first transition metal oxide layer. The predetermined resistance value ranges from 70? to 1000? inclusive.Type: GrantFiled: December 12, 2011Date of Patent: April 8, 2014Assignee: Panasonic CorporationInventors: Shinichi Yoneda, Takumi Mikawa
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Patent number: 8691619Abstract: This invention aims to provide a laminated structure and an integrated structure of a high production efficiency for a CIS based thin-film solar cell, which can produce a high-resistance buffer layer of the CIS based thin-film solar cell efficiently on a series of production lines and which needs no treatment of wastes or the like, and a manufacturing method for the structures. The CIS based thin-film solar cell includes a back electrode, a p-type CIS based light absorbing layer, a high-resistance buffer layer and an n-type transparent conductive film laminated in this order. The high-resistance buffer layer and the n-type transparent conductive film are formed of thin films of a zinc oxide group. The buffer layer contacts the p-type CIS based light absorbing layer directly, and has a resistivity of 500?·cm or higher.Type: GrantFiled: November 25, 2008Date of Patent: April 8, 2014Assignee: Showa Shell Sekiyu, K.K.Inventors: Hideki Hakuma, Katsuya Tabuchi, Yosuke Fujiwara, Katsumi Kushiya
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Patent number: 8691622Abstract: A method of forming a memory cell includes forming programmable material within an opening in dielectric material over an elevationally inner conductive electrode of the memory cell. Conductive electrode material is formed over the dielectric material and within the opening. The programmable material within the opening has an elevationally outer edge surface angling elevationally and laterally inward relative to a sidewall of the opening. The conductive electrode material is formed to cover over the angling surface of the programmable material within the opening. The conductive electrode material is removed back at least to an elevationally outermost surface of the dielectric material and to leave the conductive electrode material covering over the angling surface of the programmable material within the opening. The conductive electrode material constitutes at least part of an elevationally outer conductive electrode of the memory cell. Memory cells independent of method of manufacture are also disclosed.Type: GrantFiled: May 25, 2012Date of Patent: April 8, 2014Assignee: Micron Technology, Inc.Inventors: John Smythe, Gurtej S. Sandhu
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Patent number: 8686389Abstract: Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.Type: GrantFiled: October 16, 2012Date of Patent: April 1, 2014Assignee: Intermolecular, Inc.Inventors: Yun Wang, Imran Hashim
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Patent number: 8685785Abstract: A method of manufacturing a phase change memory cell on a substrate. The method includes: etching a first trench in the substrate; depositing a first conductor layer in the first trench; depositing a first insulator layer over the first conductor layer in the first trench; etching a second trench in the substrate at an angle to the first trench; depositing a second insulator layer in the second trench; depositing a second conductor layer over the second insulator layer in the second trench; and depositing phase change material. The deposited phase change material is in contact with the first conductor layer and the second conductor layer.Type: GrantFiled: September 14, 2012Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Michele M. Franceschini, John P. Karidis
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Patent number: 8686391Abstract: A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.Type: GrantFiled: September 12, 2012Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Alejandro G. Schrott, Chung H. Lam, Eric A. Joseph, Matthew J. Breitwisch, Roger W. Cheek
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Patent number: 8685786Abstract: Disclosed herein is a semiconductor memory device, including: a first electrode formed on a substrate; an ion source layer formed on an upper layer of the first electrode; and a second electrode formed on an upper layer of the ion source layer. Resistance change type memory cells in each of which either a surface of the first electrode or a surface of the ion source layer is oxidized to form a resistance change type memory layer in an interface between the first electrode and the ion source interface are arranged in a array.Type: GrantFiled: May 24, 2013Date of Patent: April 1, 2014Assignee: Sony CorporationInventors: Yoshihisa Kagawa, Tetsuya Mizuguchi, Ichiro Fujiwara, Akira Kouchiyama, Satoshi Sasaki, Naomi Yamada
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Patent number: 8685783Abstract: On a first structure having a first dielectric layer, a second dielectric layer, and a third dielectric layer a crown is formed through the third dielectric layer and the second dielectric layer. A fourth dielectric layer is deposited over the first structure and thereby is over the crown. A portion of the fourth dielectric layer is removed to form a first spacer having a remaining portion of the fourth dielectric layer. A portion of the third electric layer is also removed during the removal of the portion the fourth dielectric layer, resulting in a second spacer having a remaining portion of the third dielectric layer. A second structure is thereby formed. A phase change material layer is deposited over the second structure. An electrode layer is deposited over the phase change layer.Type: GrantFiled: October 27, 2010Date of Patent: April 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Huei Shen, Tsun Kai Tsao, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 8674127Abstract: Precursors for use in depositing antimony-containing films on substrates such as wafers or other microelectronic device substrates, as well as associated processes of making and using such precursors, and source packages of such precursors. The precursors are useful for deposition of A Ge2Sb2Te5 chalcogenide thin films in the manufacture of nonvolatile Phase Change Memory (PCM) or for the manufacturing of thermoelectric devices, by deposition techniques such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).Type: GrantFiled: April 30, 2009Date of Patent: March 18, 2014Assignee: Advanced Technology Materials, Inc.Inventors: Tianniu Chen, William Hunks, Philip S. H. Chen, Chongying Xu, Leah Maylott
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Patent number: 8673401Abstract: A method for depositing gallium using a gallium ink, comprising, as initial components: a gallium component comprising gallium; a stabilizing component; an additive; and, a liquid carrier; is provided comprising applying the gallium ink on the substrate; heating the applied gallium ink to eliminate the additive and the liquid carrier, depositing gallium on the substrate; and, optionally, annealing the deposited gallium.Type: GrantFiled: January 7, 2013Date of Patent: March 18, 2014Assignee: Rohm and Haas Electronic Materials LLCInventors: David Mosley, David Thorsen
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Patent number: 8673717Abstract: A method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes forming pillars with a doped silicon region on the substrate. An electrically conductive gate material is deposited between and over the pillars. The gate material is etched such that the gate material partially fills a space between the pillars. The pillars are then etched such that a pair of pillars from the pillars include an insulating material over the doped silicon region. A gate contact is deposited between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level, and the insulating material extends below the contact interface level.Type: GrantFiled: July 18, 2012Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Matthew J. BrightSky, Chung H. Lam, Gen P. Lauer
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Publication number: 20140073084Abstract: A method of forming a phase change material which having germanium and tellurium therein includes depositing a germanium-containing material over a substrate. Such material includes elemental-form germanium. A gaseous tellurium-comprising precursor is flowed to the germanium-comprising material and tellurium is removed from the gaseous precursor to react with the elemental-form germanium in the germanium-comprising material to form a germanium and tellurium-comprising compound of a phase change material over the substrate. Other implementations are disclosed.Type: ApplicationFiled: November 18, 2013Publication date: March 13, 2014Applicant: Micron Technology, Inc.Inventors: Eugene P. Marsh, Timothy A. Quick, Stefan Uhlenbrock
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Patent number: 8664033Abstract: A gallium-containing alloy is formed on the light-receiving surface of a CIGS absorber layer, and, in conjunction with a subsequent selenization or anneal process, is converted to a gallium-rich region at the light-receiving surface of the CIGS absorber layer. A second gallium-rich region is formed at the back contact surface of the CIGS absorber layer during selenization, so that the CIGS absorber layer has a double-graded gallium concentration that increases toward the light-receiving surface and toward the back contact surface of the CIGS absorber layer. The double-graded gallium concentration advantageously produces a double-graded bandgap profile for the CIGS absorber layer.Type: GrantFiled: December 20, 2011Date of Patent: March 4, 2014Assignee: Intermolecular, Inc.Inventor: Haifan Liang
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Publication number: 20140054536Abstract: A resistive memory device capable of implementing a multi-level cell, a method of fabricating the same, and a memory apparatus and data processing system including the same are provided. The resistive memory device includes a lower electrode, a first phase-change material layer formed over the lower electrode, a second phase-change material layer formed to surround an outer sidewall of the first phase-change material layer, and an upper electrode formed over the first phase-change material layer and the second phase-change material layer.Type: ApplicationFiled: December 19, 2012Publication date: February 27, 2014Applicant: SK HYNIX INC.Inventor: Sung Min LEE
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Patent number: 8658999Abstract: According to an embodiment, a semiconductor device includes first and second memristors. The first memristor includes a first electrode made of a first material, a second electrode made of a second material, and a first resistive switching film arranged between the first and second electrodes. The first resistive switching film is connected to both the first and second electrodes. The second memristor includes a third electrode made of a third material, a fourth electrode made of the second material, and a second resistive switching film arranged between the third and fourth electrodes. The second resistive switching film is connected to both the third and fourth electrodes. The work function of the first material is smaller than that of the second material. The work function of the third material is larger than that of the second material.Type: GrantFiled: December 27, 2012Date of Patent: February 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshifumi Nishi, Takao Marukame, Takayuki Ishikawa, Masato Koyama
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Patent number: 8653493Abstract: According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane.Type: GrantFiled: February 9, 2012Date of Patent: February 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Jin Kang, Youngnam Hwang
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Patent number: 8653495Abstract: A phase change memory may be formed of two vertically spaced layers of phase change material. An intervening dielectric may space the layers from one another along a substantial portion of their lateral extent. An opening may be provided in the intervening dielectric to allow the phase change layers to approach one another more closely.Type: GrantFiled: April 11, 2005Date of Patent: February 18, 2014Assignee: Micron Technology, Inc.Inventors: Guy C. Wicker, Fabio Pellizzer, Enrico Varesi, Agostino Pirovano
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Patent number: 8652876Abstract: A method of manufacturing a phase-change random access memory includes: sequentially depositing an insulating layer, a first electrode layer, a phase change material layer, and a transfer material layer on a substrate; forming an array pattern in the transfer material layer using a laser interference lithography process; forming a metal layer on the transfer material layer having the array pattern formed; forming a second electrode layer by removing the transfer material layer; and forming a phase change layer by etching the phase change material layer using the second electrode layer as a mask. Accordingly, the manufacturing process of the phase-change random access memory may achieve an increase in speed and may be simplified.Type: GrantFiled: November 9, 2012Date of Patent: February 18, 2014Assignee: Korea Institute of Science and TechnologyInventors: Young Hwan Kim, Yong Tae Kim, Jinn Il Choi
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Patent number: 8642988Abstract: A non-volatile memory device includes: a first line extending along a main surface of a substrate; a stack provided above the first line; a second line formed above the stack; a select element provided where the first and second lines intersect, the select element adapted to pass current in a direction perpendicular to the main surface; a second insulator film provided along a side surface of the stack; a channel layer provided along the second insulator film; an adhesion layer provided along the channel layer; and a variable resistance material layer provided along the adhesion layer, wherein the first and second lines are electrically connected via the select element and channel layer, a contact resistance via the adhesion layer between the channel layer and variable resistance material layer is low, and a resistance of the adhesion layer is high with respect to an extending direction of the channel layer.Type: GrantFiled: August 17, 2012Date of Patent: February 4, 2014Assignee: Hitachi, Ltd.Inventors: Masaharu Kinoshita, Yoshitaka Sasago, Takashi Kobayashi, Hiroyuki Minemura
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Patent number: 8643080Abstract: Provided are three-dimensional semiconductor devices. The devices may include gap-fill insulating patterns configured to upwardly extend from a substrate and an electrode structure defined by sidewalls of the gap-fill insulating patterns. Vertical structures may be provided between adjacent ones of the gap-fill insulating patterns to penetrate the electrode structure, and the vertical structures may include first and second rows of the vertical structures. A separation pattern may be provided between the first and second rows of vertical structures and include a separation semiconductor layer. The separation pattern extends along a direction parallel to the first and second rows of vertical structures.Type: GrantFiled: August 25, 2011Date of Patent: February 4, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Changhyun Lee, Byoungkeun Son, Youngwoo Park
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Patent number: 8637844Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.Type: GrantFiled: April 29, 2011Date of Patent: January 28, 2014Assignees: International Business Machines Corporation, Macronix International Co., Ltd., Qimonda AGInventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung, Min Yang
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Publication number: 20140024173Abstract: Described herein is a method and liquid-based precursor composition for depositing a multicomponent film. In one embodiment, the method and compositions described herein are used to deposit Germanium Tellurium (GeTe), Antimony Tellurium (SbTe), Antimony Germanium (SbGe), Germanium Antimony Tellurium (GST), Indium Antimony Tellurium (IST), Silver Indium Antimony Tellurium (AIST), Cadmium Telluride (CdTe), Cadmium Selenide (CdSe), Zinc Telluride (ZnTe), Zinc Selenide (ZnSe), Copper indium gallium selenide (CIGS) films or other tellurium and selenium based metal compounds for phase change memory and photovoltaic devices.Type: ApplicationFiled: September 20, 2013Publication date: January 23, 2014Inventors: Manchao Xiao, Liu Yang, Xinjian Lei, Iain Buchanan
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Publication number: 20140024172Abstract: Apparatus and method for vapor deposition of a sublimated source material are generally provided. The apparatus includes a deposition head with a first sublimation compartment and a second sublimation compartment, each configured for receipt and sublimation of a source material. A first distribution plate can be positioned at a first defined distance above a horizontal conveyance plane of an upper surface of substrates conveyed through a first deposition area of the apparatus, and a second distribution plate can be positioned at a second defined distance above a horizontal conveyance plane of an upper surface of substrates conveyed through a second deposition area of said apparatus. The first sublimation compartment and the second sublimation compartment can be isolated from each other such that the sublimated first source material is substantially prevented from mixing with the sublimated second source material, at least during sublimation.Type: ApplicationFiled: July 20, 2012Publication date: January 23, 2014Applicant: PRIMESTAR SOLAR, INC.Inventors: Christopher Rathweg, Scott Daniel Feldman-Peabody
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Patent number: 8634236Abstract: Provided are a phase change memory device and a fabricating method thereof. The phase change memory device includes a substrate, an interlayer dielectric layer formed on the substrate, first and second contact holes formed in the interlayer dielectric layer, and a memory cell formed in the first and second contact holes and including a diode, a first electrode on the diode, a phase change material layer on the first electrode, and a second electrode on the phase change material layer, wherein the first contact hole and the second contact hole are spaced apart from and separated from each other.Type: GrantFiled: September 16, 2011Date of Patent: January 21, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hye-Young Park, Jeong-Hee Park, Hyun-Suk Kwon
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Patent number: 8632851Abstract: A method of forming an compound semiconductor thin film of chalcopyrite structure includes the steps of heating up elemental VI powder in a first chamber to produce VI vapor flux. The VI vapor flow is introduced into a second chamber and an Argon plasma is utilized to crack large molecular VI fractions to generate small VI species. The small molecule VI species are homogeneously deposited on the metallic I-III precursor layers and the precursor film is sealed into a graphite box and transferred to an annealing chamber to create an absorber layer with a large grain size and good crystalline structure.Type: GrantFiled: April 26, 2013Date of Patent: January 21, 2014Assignee: Sun Harmonics LtdInventors: Yuhang Ren, Zhi Huang, Paifeng Luo, Kai Shum
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Patent number: 8629421Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.Type: GrantFiled: October 15, 2012Date of Patent: January 14, 2014Assignee: Micron Technology, Inc.Inventors: D.V. Nirmal Ramaswamy, Murali Balakrishnan, Alessandro Torsi, Noel Rocklein
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Patent number: 8623697Abstract: A storage element structure for phase change memory (PCM) cell and a method for forming such a structure are disclosed. The method of forming a storage element structure, comprises providing a multilayer stack comprising a chalcogenide layer (206), a metal cap layer (208), and a dielectric hard mask layer (210), depositing and patterning a photo resist layer (212) on top of the multilayer stack, etching the dielectric hard mask layer using the photo resist layer as etch mask, after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide, etching the chalcogenide layer using the dielectric hard mask layer as etch mask, depositing a spacer dielectric (214) over the multilayer stack and anisotropically etching the spacer dielectric to form sidewall spacers (216) for the multilayer stack.Type: GrantFiled: December 31, 2008Date of Patent: January 7, 2014Assignee: Micron Technology, Inc.Inventors: Michele Magistretti, Pietro Petruzza, Samuele Sciarrillo, Cristina Casellato
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Patent number: 8618603Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.Type: GrantFiled: July 11, 2012Date of Patent: December 31, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Fumiki Aiso
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Patent number: 8614117Abstract: A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line and placed on both sides of the gate contact over a layer of insulating material. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars over an insulating material on the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material.Type: GrantFiled: February 8, 2012Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventors: Matthew J. BrightSky, Chung H. Lam, Gen P. Lauer
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Patent number: 8613899Abstract: An apparatus includes a manifold with a chamber for mixing multiple reactants. Gases are jetted into the manifold by a plurality of inlet injectors. The inlet injectors are arranged such that the gases passing into the manifold impinge on each other at a common point to form a mixture. The mixture passes through a plurality of holes in one side of the manifold into a deposition chamber where the mixture of gases impinges on additional gases at a common point to provide a reaction resulting in deposition of solid materials in the deposition chamber. The solid materials are free-standing.Type: GrantFiled: April 17, 2012Date of Patent: December 24, 2013Assignees: Rohm and Haas Electronic Materials LLC, Dow Global Technologies LLCInventors: Heather A. G. Stern, Vincent DiFilippo, Jitendra S. Goela, Michael A. Pickering, Hua Bai, Debashis Chakraborty, Hangyao Wang
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Patent number: 8614135Abstract: A phase change memory is manufactured by providing a substrate including a layer of phase-change material, forming a damascene pattern on the layer of phase-change material, and forming both a top electrode and a bit line in the damascene pattern.Type: GrantFiled: February 9, 2010Date of Patent: December 24, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-ho Eun, JaeHee Oh
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Patent number: 8610101Abstract: According to one embodiment, there are provided a first electrode, a second electrode containing a 1B group element having an Al element added thereto, and a variable resistive layer disposed between the first electrode and the second electrode and having a silicon element.Type: GrantFiled: January 27, 2012Date of Patent: December 17, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yamauchi, Shosuke Fujii, Reika Ichihara
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Patent number: 8609459Abstract: A nanostructure quick-switch memristor includes an upper electrode, a lower electrode and three layers of nanomembrane provided between the upper electrode and the lower electrode. The three layers of nanomembrane consist of an N-type semiconductor layer, a neutral semiconductor layer on the N-type semiconductor layer, and a P-type semiconductor layer on the neutral semiconductor layer. The nanostructure quick-switch memristor of the present invention has the quick switching speed, simple manufacturing method, and low manufacturing cost.Type: GrantFiled: June 13, 2013Date of Patent: December 17, 2013Assignee: Heilongjiang UniversityInventors: Dianzhong Wen, Xiaohui Bai
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Patent number: 8609506Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.Type: GrantFiled: November 19, 2012Date of Patent: December 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Patent number: 8598010Abstract: Methods of forming a variable-resistance memory device include patterning an interlayer dielectric layer to define an opening therein that exposes a bottom electrode of a variable-resistance memory cell, on a memory cell region of a substrate (e.g., semiconductor substrate). These methods further include depositing a layer of variable-resistance material (e.g., phase-changeable material) onto the exposed bottom electrode in the opening and onto a first portion of the interlayer dielectric layer extending opposite a peripheral circuit region of the substrate. The layer of variable-resistance material and the first portion of the interlayer dielectric layer are then selectively etched in sequence to define a recess in the interlayer dielectric layer. The layer of variable-resistance material and the interlayer dielectric layer are then planarized to define a variable-resistance pattern within the opening.Type: GrantFiled: April 20, 2011Date of Patent: December 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Heung Jin Joo, JaeHee Oh, Byoungjae Bae, Myung Jin Kang
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Patent number: 8597975Abstract: A method is provided for fabricating a microelectronic device with programmable memory that includes: i) depositing an intermediate layer of a material having a chalcogenide on a first electrode; ii) irradiating the intermediate layer of step i with ultraviolet radiation; iii) depositing an ionizable metallic layer on the intermediate layer obtained in step ii; iv) diffusing the metal ions originating from the ionizable metallic layer of step iii into the intermediate layer to form a chalcogenide material containing metal ions; and v) depositing a second electrode on the layer of chalcogenide material containing metal ions obtained in step iv to form the microelectronic device.Type: GrantFiled: July 2, 2012Date of Patent: December 3, 2013Assignee: Altis SemiconductorInventor: Faiz Dahmani
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Publication number: 20130314983Abstract: A method of storing a bit at a memory device is disclosed. A memory cell the memory device is formed of a germanium-deficient chalcogenide glass configured to alternate between an amorphous phase and a crystalline phase upon application of a selected voltage, wherein a drift coefficient of the germanium-deficient chalcogenide glass is less than a drift coefficient of an undoped chalcogenide glass. A voltage is applied to the formed memory cell to select one of the amorphous phase and the crystalline phase to store the bit.Type: ApplicationFiled: May 23, 2012Publication date: November 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chung H. Lam, Jing Li, Binquan Luan, Glenn J. Martyna, Dennis M. Newns
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Patent number: 8592979Abstract: A conductive pattern structure includes a first insulating interlayer on a substrate, metal wiring on the first insulating interlayer, a second insulating interlayer on the metal wiring, and first and second metal contacts extending through the second insulating interlayer. The first metal contacts contact the metal wiring in a cell region and the second metal contact contacts the metal wiring in a peripheral region. A third insulating interlayer is disposed on the second insulating interlayer. Conductive segments extend through the third insulating interlayer in the cell region and contact the first metal contacts. Another conductive segment extends through the third insulating interlayer in the peripheral region and contacts the second metal contact. The structure facilitates the forming of uniformly thick wiring in the cell region using an electroplating process.Type: GrantFiled: April 5, 2012Date of Patent: November 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hei-Seung Kim, Gil-Heyun Choi, Ji-Soon Park, Jong-Myeong Lee