Abstract: A method of depositing an antimony-comprising phase change material onto a substrate includes providing a reducing agent and vaporized Sb(OR)3 to a substrate, where R is alkyl, and forming there-from antimony-comprising phase change material on the substrate. The phase change material has no greater than 10 atomic percent oxygen, and includes another metal in addition to antimony.

Abstract: According to one embodiment, a semiconductor memory device includes a word line interconnect layer, a bit line interconnect layer and a pillar. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction intersecting with the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The pillar has a selector stacked film containing silicon, and a variable resistance film disposed on a side of the word lines or the bit lines. The selector stacked film has a different component-containing layer. The different component-containing layer is formed at one position in a region excluding ends on the sides of the word and bit lines, and contains a 14 group element having a larger atomic radius than an atomic radius of silicon.

Abstract: The present invention relates to the use of a shaped bottom electrode in a resistance variable memory device. The shaped bottom electrode ensures that the thickness of the insulating material at the tip of the bottom electrode is thinnest, creating the largest electric field at the tip of the bottom electrode. The arrangement of electrodes and the structure of the memory element makes it possible to create conduction paths with stable, consistent and reproducible switching and memory properties in the memory device.

Abstract: A nonvolatile memory element includes a substrate; a lower electrode layer and a resistive layer sequentially formed on the substrate; a resistance variable layer formed on the resistive layer; a wire layer formed above the lower electrode layer; an interlayer insulating layer disposed between the substrate and the wire layer and covering at least the lower electrode layer and the resistive layer, the interlayer insulating layer being provided with a contact hole extending from the wire layer to the resistance variable layer; and an upper electrode layer formed inside the contact hole such that the upper electrode layer is connected to the resistance variable layer and to the wire layer; resistance values of the resistance variable layer changing reversibly in response to electric pulses applied between the lower electrode layer and the upper electrode layer.

Abstract: Various embodiments of the present invention are direct to nanoscale, reconfigurable memristor devices. In one aspect, a memristor device (500,600) comprises an active region (508,610) sandwiched between a first electrode (301) and a second electrode (302). The active region including a non-volatile dopant region (506,608) selectively formed and positioned within the active region.

Abstract: A method for forming a non-volatile memory device includes forming a dielectric material overlying a semiconductor substrate, forming a first wiring structure overlying the first dielectric material, depositing an undoped amorphous silicon layer, depositing an aluminum layer over the amorphous silicon layer at a temperature of about 450 Degrees Celsius or lower, annealing the amorphous silicon and aluminum at a temperature of about 450 Degrees Celsius or lower to form a p+ polycrystalline layer, depositing a resistive switching material comprising an amorphous silicon material overlying the polycrystalline silicon material, forming a second wiring structure comprising a metal material overlying the resistive switching material.

Abstract: A phase change RAM device includes a semiconductor substrate having a phase change cell area and a voltage application area; a first oxide layer, a nitride layer and a second oxide layer sequentially formed on the semiconductor substrate; a first plug formed in the first oxide layer, the nitride layer and the second oxide layer of the phase change cell area; a second plug formed in the first oxide layer and the nitride layer of the voltage application area; a conductive line formed in the second oxide layer; a third oxide layer formed on the second oxide layer; a lower electrode shaped like a plug, the lower electrode being formed so as to directly make contact with the first plug; and a phase change layer and an upper electrode sequentially formed on the lower electrode in a pattern form.

Abstract: A memristor having an active region includes a first electrode. The first electrode comprises a nanostructure formed of at least one metallic single walled nanotube. The memristor also includes a second electrode formed of at least one metallic single walled nanotube. The second electrode is positioned in a crossed relationship with respect to the first electrode. The memristor further includes a switching material positioned between the first electrode and the second electrode, in which the active region is configured to form in the switching material at a cross point of the first electrode and the second electrode.

Abstract: A nonvolatile memory element comprises a first electrode (103); a second electrode (105); and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (105), resistance values of the resistance variable layer reversibly changing in response to electric signals applied between the electrodes (103, 105); the resistance variable layer (104) including a first tantalum oxide layer (107) comprising a first tantalum oxide and a second tantalum oxide layer (108) comprising a second tantalum oxide which is different in oxygen content from the first tantalum oxide, the first tantalum oxide layer and the second tantalum oxide layer being stacked together, and being configured such that 0<x<2.5 is satisfied when the first tantalum oxide is expressed as TaOx and x<y?2.5 is satisfied when the second tantalum oxide is expressed as TaOy; and the second electrode (105) being in contact with the second tantalum oxide layer (108) and comprising platinum and tantalum.

Abstract: A nonvolatile memory element includes first and second electrodes, and a resistance variable layer disposed therebetween. At least one of the first and second electrodes includes a platinum-containing layer. The resistance variable layer includes a first oxygen-deficient transition metal oxide layer which is not physically in contact with the platinum-containing layer and a second oxygen-deficient transition metal oxide layer which is disposed between the first oxygen-deficient transition metal oxide layer and the platinum-containing layer and is physically in contact with the platinum-containing layer. When oxygen-deficient transition metal oxides included in the first and second oxygen-deficient transition metal oxide layers are expressed as MOx, and MOy, respectively, x<y is satisfied. The platinum-containing layer has a thickness which is not less than 1 nm and not more than 23 nm.

Abstract: Example embodiments, relate to a non-volatile memory element and a memory device including the same. The non-volatile memory element may include a memory layer having a multi-layered structure between two electrodes. The memory layer may include first and second material layers and may show a resistance change characteristic due to movement of ionic species therebetween. The first material layer may be an oxygen-supplying layer. The second material layer may be an oxide layer having a multi-trap level.

Abstract: A large-capacity and inexpensive nonvolatile semiconductor memory device that prevents a leak current and is operated at high speed is implemented with a nonvolatile variable resistive element. A memory cell array includes the nonvolatile variable resistive elements each including a variable resistor composed of a metal oxide film to cause a resistance change according to an oxygen concentration in the film, an insulation film formed on the variable resistor, first and second electrodes to sandwich the variable resistor, and a third electrode opposite to the variable resistor across the insulation film. A writing operation is performed by applying a voltage to the third electrode to induce an electric field having a threshold value or more, in a direction perpendicular to an interface between the variable resistor and the insulation film, and a resistance state of the variable resistor is read by applying a voltage between the first and second electrodes.

Abstract: A nonvolatile semiconductor memory device which can achieve miniaturization and a larger capacity in a cross-point structure in which memory cells are formed inside contact holes at cross points of word lines and bit lines, respectively, and a manufacturing method thereof are provided.

Abstract: A memory or switching device includes a mesa and a first electrode conforming to said mesa. The device also includes a second electrode and a phase-change or switching material disposed between said first and second electrodes. The phase-change or switching material is in electrical communication with the first and second electrodes at a first contact region and a second contact region respectively. Also described is a method for making a memory or switching device. The method includes providing a first insulator and configuring the first insulator to provide a mesa. A first conductive layer is provided conforming to the mesa. A phase-change or switching material is provided over a portion of the first conductive layer, and a second conductive layer is provided over the phase-change or switching material.

Abstract: A nonvolatile memory element which can be initialized at low voltage includes a variable resistance layer (116) located between a lower electrode (105) and an upper electrode (107) and having a resistance value that reversibly changes based on electrical signals applied between these electrodes. The variable resistance layer (116) includes at least two layers: a first variable resistance layer (1161) including a first transition metal oxide (116b); and a second variable resistance layer (1162) including a second transition metal oxide (116a) and a third transition metal oxide (116c). The second transition metal oxide (116a) has an oxygen deficiency higher than either oxygen deficiency of the first transition metal oxide (116b) or the third transition metal oxide (116c), and the second transition metal oxide (116a) and the third transition metal oxide (116c) are in contact with the first variable resistance layer (1161).

Abstract: A memristor includes a first electrode having a triangular cross section, in which the first electrode has a tip and a base, a switching material positioned upon the first electrode, and a second electrode positioned upon the switching material. The tip of the first electrode faces the second electrode and an active region in the switching material is formed between the tip of the first electrode and the second electrode.

Abstract: The present invention relates to a transparent memory for a transparent electronic device. The transparent memory includes: a lower transparent electrode layer that is sequentially formed on a transparent substrate, and a data storage region and an upper transparent layer which are made of at least one transparent resistance-variable material layer. The transparent resistance-variable material layer has switching characteristics as a result of the resistance variance caused by the application of a certain voltage between the lower and upper transparent electrode layers. An optical band gap of the transparent resistance-variable material layer is 3 eV or more, and transmittivity of the material layer for visible rays is 80% or more. The invention provides transparent and resistance-variable memory that: has very high transparency and switching characteristics depending on resistance variation at a low switching voltage, and can maintain the switching characteristics thereof after a long time elapses.

Abstract: There are provided a resistance variable nonvolatile memory device which changes its resistance stably at low voltages and is suitable for a miniaturized configuration, and a manufacturing method thereof. The nonvolatile memory device comprises: a substrate (100); a first electrode (101); an interlayer insulating layer (102); a memory cell hole (103) formed in the interlayer insulating layer; a first resistance variable layer (104a) formed in at least a bottom portion of the memory cell hole and connected to the first electrode; a second resistance variable layer (104b) formed inside the memory cell hole (103) and located on the first resistance variable layer (104a); and a second electrode (105); the first resistance variable layer (104a) and the second resistance variable layer (104b) respectively comprising metal oxides of the same kind; and the first resistance variable layer (104a) having a higher oxygen content than the second resistance variable layer (104b).

Abstract: A memristor with a switching layer that includes a composite of multiple phases is disclosed. The memristor comprises: a first electrode; a second electrode spaced from the first electrode; and a switching layer positioned between the first electrode and the second electrode, the switching layer comprising the multi-phase composite system that comprises a first majority phase comprising a relatively insulating matrix of a switching material and a second minority phase comprising a relatively conducting material for forming at least one conducting channel in the switching layer during a fabrication process of the memristor. A method of making the memristor and a crossbar employing the memristor are also disclosed.

Abstract: A memory cell structure, including a substrate having a via therein bound at first and second ends thereof by electrodes. The via is coated on side surfaces thereof with GST material defining a core that is hollow or at least partially filled with material, e.g., germanium or dielectric material. One or more of such memory cell structures may be integrated in a phase change memory device. The memory cell structure can be fabricated in a substrate containing a via closed at one end thereof with a bottom electrode, by conformally coating GST material on sidewall surface of the via and surface of the bottom electrode enclosing the via, to form an open core volume bounded by the GST material, optionally at least partially filling the open core volume with germanium or dielectric material, annealing the GST material film, and forming a top electrode at an upper portion of the via.

Abstract: According to one embodiment, a nonvolatile memory device includes a first wire, a second wire and a nonvolatile memory cell. The first wire is formed to extend in a first direction, and the second wire is formed at height different from height of the first wire and to extend in a second direction. The nonvolatile memory cell is arranged to be held between the first wire and the second wire in a poison where the first wire and the second wire cross. The nonvolatile memory cell includes a nonvolatile storage layer and a current limiting resistance layer connected in series to the nonvolatile storage layer and having resistance of 1 kilo-ohm to 1 mega-ohm.

Abstract: To realize miniaturization and increased capacity of memories by lowering break voltage for causing resistance change and suppressing variation in break voltage. The nonvolatile memory device (10) in the present invention includes: a lower electrode (105) formed above a substrate (100); a first variable resistance layer (106a) formed above the lower electrode (105) and comprising a transitional metal oxide; a second variable resistance layer (106b) formed above the first variable resistance layer (106a) and comprising a transitional metal oxide having higher oxygen content than the transitional metal oxide of the first variable resistance layer (106a); and an upper electrode (107) formed above the second variable resistance layer (106b), wherein a step (106ax) is formed in an interface between the first variable is resistance layer (106a) and the second variable resistance layer (106b).

Abstract: According to one embodiment, a nonvolatile memory device comprises a plurality of first lines, a plurality of second lines, and memory cells. Each of the memory cells comprise a variable resistor, and a diode. The variable resistor includes a first metal oxide film and is configured to reversibly change resistance value by energy application. The diode includes a second metal oxide film and is connected in series to the variable resistor. The first metal oxide film has at least one of dielectric constant lower than that of the second metal oxide film and physical film thickness greater than that of the second metal oxide film.

Abstract: A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.

Abstract: Graphene magnet multilayers (GMMs) are employed to facilitate development of spintronic devices. The GMMs can include a sheet of monolayer (ML) or few-layer (FL) graphene in contact with a magnetic material, such as a ferromagnetic (FM) or an antiferromagnetic material. Electrode terminals can be disposed on the GMMs to be in electrical contact with the graphene. A magnetic field effect is induced in the graphene sheet based on an exchange magnetic field resulting from a magnetization of the magnetic material which is in contact with graphene. Electrical characteristics of the graphene can be manipulated based on the magnetization of the magnetic material in the GMM.

Abstract: A method for manufacturing a phase change memory includes forming a phase change memory cell by forming a phase change layer between two switching layers. The phase change layer is separated from thermal heat sinks, such as the bitline or wordline, by the switching layers.

Abstract: In some aspects, a memory cell is provided that includes (1) a steering element above a substrate; and (2) a reversible resistance-switching element coupled to the steering element, wherein the reversible resistance-switching element is selectively formed by: (a) forming a material layer on the substrate; (b) etching the material layer; and (c) oxidizing the etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.

Abstract: Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.

Abstract: To provide a variable resistance element capable of preventing the interface resistance, in a side of the variable resistance element in which resistance change is not allowed, from changing to high resistance due to applied voltage. The variable resistance element is configured by providing a variable resistance film (265) between a first electrode (280) and a second electrode (250), the oxygen concentration within the film of the variable resistance film (265) is high at the side of an interface with the second electrode (250) (high-concentration variable resistance layer (260)) and low at the side of an interface with the first electrode (280) (low-concentration variable resistance layer (270)), and the junction surface area between the low-concentration variable resistance layer (270) and the first electrode (280) is larger than the interface surface area between the high-concentration variable resistance layer (260) and the second electrode (250).

Abstract: A variable resistance device includes a first electrode including a transition metal nitride film, a second electrode including a precious metal or a precious metal oxide, and a transition metal oxide film interposed between the first and second electrodes.

Abstract: A first wire layer (19) including first memory wires (12) is connected to a second wire layer (20) including second memory wires (17) via first contacts (21) penetrating a first interlayer insulating layer (13). The first wire layer (13) is connected to and led out to upper wires (22) via second contacts (26) connected to the second wire layer (20) and penetrating the second interlayer insulating layer (18). The first contacts (21) penetrate semiconductor layer (17b) or insulator layer (17c) of the second wire layer (20).

Abstract: A resistive random access memory includes a lower electrode; a metal oxide film formed on the lower electrode and having a variable resistance, the metal oxide film having a first portion containing a metal element forming the metal oxide film and a second portion richer in oxygen than the first portion; and an upper electrode formed on the metal oxide film.

Abstract: A stacked-chip device includes a first inductive chip having a first function, a second inductive chip having a second function different from the first function, which is stacked on the first inductive chip, and a third inductive chip having the second function, which is stacked on the second inductive chip. Each of the first, second and third inductive chips has transmitting inductors which transmit data and receiving inductors which receive data. The transmitting inductors and the receiving inductors are disposed in line symmetry to an axis of symmetry. The axes of symmetry of the first, second and third inductive chips are overlapped. Each of the second and third inductive chips is disposed in upside-down or back to front to the first inductive chip.

Abstract: According to one embodiment, a variable resistance layer includes a mixture of a first compound and a second compound. The first compound includes carbon (C) as well as at least one element selected from a group of elements G1. The group of elements G1 consists of hydrogen (H), boron (B), nitrogen (N), silicon (Si), and titanium (Ti). The second compound includes at least one compound selected from a group of compounds G2. The group of compounds G2 consists of silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (Si3N4), carbon nitride (C3N4), boron nitride (BN), aluminum nitride (AlN), aluminum oxide (Al2O3), and silicon carbide (SiC). Concentration of the first compound in the variable resistance layer is not less than 30 volume percent, and not more than 70 volume percent.

Abstract: An electronic device (100), the electronic device (100) comprises a substrate (101), a first electrode (102) formed at least partially on the substrate (101), a second electrode (103) formed at least partially on the substrate (101), a convertible structure (104) connected between the first electrode (102) and the second electrode (103), and a spacer element (105) connected between the first electrode (102) and the second electrode (103) and adapted for spacing the convertible structure (104) with regard to a surface of the substrate (101).

Abstract: A non-volatile memory device includes a lower electrode, a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, and an upper electrode formed on the phase-change material layer so as to be electrically connected to the phase-change material layer. The phase-change material layer includes a phase-change material including a composition represented by the formula (I)A(IIXIIIYIVZ)(1-A), where I is at least one of As and Se, II is at least one of Ge, Si and Sn, III is at least one of Sb and Bi, and IV is at least one of Te and Se, and where 0.001?A?0.3, 0.001?X?0.3, 0.001?Y?0.8, 0.1?Z?0.8, and X+Y+Z=1.

Abstract: An integrated circuit device includes a device isolation pattern on a semiconductor substrate to define an active area therein. The active area includes a doped region therein. A conductive pattern extends on the active area and electrically contacts the doped region. The conductive pattern has a lower resistivity than the doped region. The conductive pattern may be disposed in a recessed region having a bottom surface lower than a top surface of the active area. A channel pillar electrically contacts to the doped region and extends therefrom in a direction away from the substrate. A conductive gate electrode is disposed on a sidewall of the channel pillar, and a gate dielectric layer is disposed between the gate electrode and the sidewall of the channel pillar.

Abstract: A resistive random access memory (RRAM) devices and resistive random access memory (RRAM) arrays are provided, the RRAM devices include a first electrode layer, a variable resistance material layer formed of an oxide of a metallic material having a plurality of oxidation states, an intermediate electrode layer on the variable resistance material layer and formed of a conductive material having a lower reactivity with oxygen than the metallic material, and a second electrode layer on the intermediate electrode layer. The RRAM arrays include at least one of the aforementioned RRAM devices.

Abstract: A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.

Abstract: A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.

Abstract: A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.

Abstract: Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.

Abstract: A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.

Abstract: A semiconductor memory device includes first lines and second lines and a memory cell array. The first lines and second lines are formed to intersect each other. The memory cell array includes memory cells arranged at intersections of the first lines and the second lines and each formed by connecting a rectification element and a variable-resistance element in series. The rectification element includes a first semiconductor region having an n-type and a second semiconductor region having a p-type. At least a portion of the first semiconductor region is made of a silicon-carbide mixture (Si1-xCx (0<x<1)), and the second semiconductor region is made of silicon (Si).

Abstract: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.

Abstract: A phase-change memory is provided. The phase-change memory comprises a substrate. A first electrode is formed on the substrate. A circular or linear phase-change layer is electrically connected to the first electrode. A second electrode formed on the phase-change layer and electrically connected to the phase-change layer, wherein at least one of the first electrode and the second electrode comprises phase-change material.

Abstract: During the manufacture of a set of non-volatile resistance-switching memory elements, a forming process is performed in which a voltage is applied over forming period until a conductive filament is formed in a resistance-switching layer. A heat source at a temperature of 50° C. to 150° C. is applied to expedite the forming process while reducing the required magnitude of the applied voltage. Manufacturing time and reliability are improved. After the forming process, an expedited training process can be performed in which a fixed number of cycles of voltage pulses are applied without verifying the memory elements. Subsequently, the memory elements are verified by determining their read current in an evaluation. Another fixed number of cycles of voltage pulses is applied without verifying the memory elements, if the memory elements do not pass the evaluation.

Abstract: A resistance switching memory is introduced herein. The resistance switching memory includes a highly-insulating or resistance-switching material formed to cover the sidewall of a patterned metal line, and extended alongside a dielectric layer sidewall to further contact a portion of the top surface of the lower electrode. The other part of the top surface of the lower electrode is covered by an insulating layer between the top electrode and the lower electrode. An oxygen gettering metal layer in the lower electrode occupies a substantial central part of the top surface of the lower electrode and is partially covered by the highly-insulating or resistance-switching material. A switching area is naturally very well confined to the substantial central part of the oxygen gettering metal layer of the lower electrode.

Abstract: A method of depositing an antimony-comprising phase change material onto a substrate includes providing a reducing agent and vaporized Sb(OR)3 to a substrate, where R is alkyl, and forming there-from antimony-comprising phase change material on the substrate. The phase change material has no greater than 10 atomic percent oxygen, and includes another metal in addition to antimony.

Abstract: A nonvolatile memory device of the present invention comprises a substrate (1), first wires (3), first filling constituents (5) filled into first through-holes (4), respectively, second wires (11) which cross the first wires (3) perpendicularly to the first wires (3), respectively, each of the second wires (11) including a plurality of layers including a resistance variable layer (6) of each of first resistance variable elements, a conductive layer (7) and a resistance variable layer (8) of each of second resistance variable elements which are stacked together in this order, second filling constituents (14) filled into second through-holes (13), respectively, and third wires (15), and the conductive layer (7) of the second wires (11) serves as the electrodes of the first resistance variable elements (9) and the electrodes of the second resistance variable elements (10).