Making Plural Separate Devices Patents (Class 438/110)
  • Patent number: 9029195
    Abstract: A method of manufacturing a semiconductor device includes mounting at least one of a first semiconductor chip and a second semiconductor chip over a die pad of a leadframe, and inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, wherein the leadframe includes first mark formed to the die pad, for indicating a first mounting region for the first semiconductor chip, and second mark formed to the die pad, for indicating a second mounting region for the second semiconductor chip, the first mark is different from the second mark, in at least either one of size and geometry, wherein, in the inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, a mounting position of the first semiconductor chip is inspected when the first semiconductor chip is mounted.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Kenji Nishikawa
  • Publication number: 20150115456
    Abstract: A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer.
    Type: Application
    Filed: December 29, 2014
    Publication date: April 30, 2015
    Inventor: Christopher M. Scanlan
  • Patent number: 9012267
    Abstract: Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: April 21, 2015
    Assignee: Intersil Americas LLC
    Inventors: Jian Yin, Nikhil Vishwanath Kelkar, Loyde Milton Carpenter, Jr.
  • Patent number: 9006031
    Abstract: A semiconductor device has a carrier with a die attach area. Recesses are formed partially through the carrier outside the die attach area. A first conductive layer is conformally applied over a surface of the carrier and into the recesses. A semiconductor die is mounted to the die attach area of the carrier. An encapsulant is deposited over the carrier and semiconductor die. The encapsulant extends into the recesses over the first conductive layer to form encapsulant bumps. The carrier is removed to expose the first conductive layer over the encapsulant bumps. A first insulating layer is formed over the semiconductor die with openings to expose contact pads of the semiconductor die. A second conductive layer is formed between the first conductive layer and the contact pads on the semiconductor die. A second insulating layer is formed over the second conductive layer and semiconductor die.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: April 14, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Henry D. Bathan, Emmanuel A. Espiritu
  • Patent number: 8999756
    Abstract: Method and apparatus for semiconductor device fabrication using a reconstituted wafer is described. In one embodiment, diced semiconductor chips are placed within openings on a frame. A reconstituted wafer is formed by filling a mold compound into the openings. The mold compound is formed around the chips. Finished dies are formed within the reconstituted wafer. The finished dies are separated from the frame.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Matthias Hierlemann
  • Patent number: 8999810
    Abstract: A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: April 7, 2015
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Vage Oganesian
  • Patent number: 8987054
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Darrell Truhitte
  • Patent number: 8980676
    Abstract: A method of forming a window cap wafer (WCW) structure for semiconductor devices includes machining a plurality of cavities into a front side of a first substrate; bonding the first substrate to a second substrate, at the front side of the first substrate; removing a back side of the first substrate so as to expose the plurality of cavities, thereby defining the WCW structure comprising the second substrate and a plurality of vertical supports comprised of material of the first substrate.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: March 17, 2015
    Assignee: Raytheon Company
    Inventors: Buu Diep, Stephen H. Black
  • Patent number: 8980696
    Abstract: A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: March 17, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dominic Koey Poh Meng, Zhiwei Gong, Kesvakumar V. C. Muniandy, Weng Foong Yap
  • Patent number: 8969136
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle pad and a peripheral lead pad with an inner lead pad between the die attach paddle pad and the peripheral lead pad; forming a component side of the lead frame for exposing an upper portion of a peripheral lead under the peripheral lead pad; forming an encapsulation on the lead frame and the upper portion of the peripheral lead; exposing the peripheral lead pad; depositing a conductive shielding layer on the encapsulation connected to the peripheral lead pad; and forming a mounting side of the lead frame for forming a lower portion of the peripheral lead over a peripheral lead contact pad.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: March 3, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventor: Reza Argenty Pagaila
  • Patent number: 8970009
    Abstract: To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a second outer ring is provided outside the first outer ring. This can prevent a crack from reaching even the seal ring that exists in the ring region, for example, when a scribe region located outside the ring region is cut off by a dicing blade.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yasushi Ishii
  • Patent number: 8959756
    Abstract: A method of manufacturing a core substrate having an electronic component, including providing a core substrate having a first surface and a second surface on an opposite side of the first surface, forming a through hole extending from the first surface to the second surface in the core substrate, attaching an adhesive tape to the second surface of the core substrate such that the through hole formed in the core substrate is closed on the second surface, attaching an electronic component to the adhesive tape inside the through hole, filling the through hole with a filler, and removing the adhesive tape from the second surface of the core substrate.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: February 24, 2015
    Assignee: IBIDEN Co., Ltd.
    Inventors: Hajime Sakamoto, Dongdong Wang
  • Patent number: 8964369
    Abstract: In an example, a solid-state data storage system comprises a housing forming an enclosure; a plurality of trays within the enclosure of the housing; a plurality of non-volatile, rewriteable solid-state memory chips mounted to flexible circuit substrates within each of the trays; and a controller configured to apply a power-sequencing scheme that supplies power to active flexible memory strands.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: February 24, 2015
    Assignee: Imation Corp.
    Inventor: Todd W. Abrahamson
  • Patent number: 8956917
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: (a) forming cutting grooves in an element formation surface of a semiconductor wafer on which semiconductor elements are formed; (b) applying a protection tape on the element formation surface of the semiconductor wafer; (c) grinding a rear surface of the semiconductor wafer to thin the semiconductor wafer and to divide the semiconductor wafer into a plurality of semiconductor chips on which the semiconductor elements are formed; (d) forming an adhesive layer on the rear surface of the semiconductor wafer; (e) separating and cutting the adhesive layer for each of the semiconductor chips; and (f) removing the protection tape. The (e) is performed by spraying a high-pressure air to the adhesive layer formed on the rear surface of the semiconductor wafer while melting or softening the adhesive layer by heating.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Kurosawa, Shinya Takyu, Akira Tomono
  • Patent number: 8956916
    Abstract: A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component. Signal contacts of each logic chip can be directly electrically connected to signal contacts of the other logic chips through the conductive structure of the substrate for transfer of signals between the logic chips. The logic chips can be adapted to simultaneously execute a set of instructions of a given thread of a process. The contacts of the memory chip can be directly electrically connected to the signal contacts of at least one of the logic chips through the conductive structure of the substrate.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: February 17, 2015
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Ilyas Mohammed, Piyush Savalia
  • Patent number: 8956904
    Abstract: A method of forming a MEMS device provides first and second wafers, where at least one of the first and second wafers has a two-dimensional array of MEMS devices. The method deposits a layer of first germanium onto the first wafer, and a layer of aluminum-germanium alloy onto the second wafer. To deposit the alloy, the method deposits a layer of aluminum onto the second wafer and then a layer of second germanium to the second wafer. Specifically, the layer of second germanium is deposited on the layer of aluminum. Next, the method brings the first wafer into contact with the second wafer so that the first germanium in the aluminum-germanium alloy contacts the second germanium. The wafers then are heated when the first and second germanium are in contact, and cooled to form a plurality of conductive hermetic seal rings about the plurality of the MEMS devices.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: February 17, 2015
    Assignee: Analog Devices, Inc.
    Inventors: John R. Martin, Timothy J. Frey, Christine H. Tsau, Michael W. Judy
  • Patent number: 8951841
    Abstract: In one embodiment, a semiconductor package includes a clip frame with a first clip having a first support structure, a first lever, and a first contact portion, which is disposed on a front side of the semiconductor package. The first support structure is adjacent an opposite back side of the semiconductor package. The first lever joins the first contact portion and the first support structure. A first die is disposed over the first support structure of the first clip. The first die has a first contact pad on the front side of the semiconductor package. An encapsulant material surrounds the first die and the first clip.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Melissa Mei Ching Ng, Mei Chin Ng, Peng Soon Lim
  • Patent number: 8952527
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: February 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Patent number: 8951840
    Abstract: A manufacturing method for Flip Chip on Chip (FCoC) package based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating first IC chip, second IC chip, solder bumps, underfill material, and metal wire to form an array of FCoC package based on the type of multi-row QFN package. Sawing and separating the FCoC package array, and forming FCoC package unit.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: February 10, 2015
    Assignee: Beijing University of Technology
    Inventors: Fei Qin, Guofeng Xia, Tong An, Chengyan Liu, Wei Wu, Wenhui Zhu
  • Patent number: 8945998
    Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Shun Hsu, Clinton Chao, Mark Shane Peng
  • Patent number: 8945988
    Abstract: There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: February 3, 2015
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Hiroyuki Numaguchi
  • Patent number: 8940557
    Abstract: A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: January 27, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-won Kim, Jong-youn Kim, Eun-kyoung Choi, Sang-uk Han, Ji-seok Hong
  • Patent number: 8941208
    Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: January 27, 2015
    Assignee: General Electric Company
    Inventors: Shakti Singh Chauhan, Arun Virupaksha Gowda, Paul Alan McConnelee
  • Patent number: 8937372
    Abstract: An integrated circuit package system includes an in-line strip, attaching an integrated circuit die over the in-line strip, and applying a molding material with a molded segment having a molded strip protrusion formed therefrom over the in-line strip.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jae Hak Yee, Junwoo Myung
  • Patent number: 8936966
    Abstract: Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: January 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 8936969
    Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die separated by a non-active region. The semiconductor die can be circular or polygonal with three or more sides. A plurality of bumps is formed over the semiconductor die. A portion of semiconductor wafer is removed to thin the semiconductor wafer. A wafer ring is mounted to mounting tape. The semiconductor wafer is mounted to the mounting tape within the wafer ring. The mounting tape includes translucent or transparent material. A penetrable layer is applied over the bumps formed over the semiconductor wafer. An irradiated energy from a laser is applied through the mounting tape to the non-active region to form a modified region within the non-active region. The semiconductor wafer is singulated along the modified region to separate the semiconductor die.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Hunteak Lee, Daewook Yang, Yeongbeom Ko
  • Patent number: 8927335
    Abstract: Method for bonding of a plurality of chips onto a base wafer which contains chips on the front, the chips being stacked in at least one layer on the back of the base wafer and electrically conductive connections are established between the vertically adjacent chips, with the following steps: a) fixing of the front of the base wafer on a carrier, b) placing at least one layer of chips in defined positions on the back of the base wafer, and c) heat treatment of the chips on the base wafer fixed on the carrier, characterized in that prior to step c) at least partial separation of the chips of the base wafer into separated chip stack sections of the base after takes place.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: January 6, 2015
    Assignee: EV Group E. Thallner GmbH
    Inventor: Markus Wimplinger
  • Patent number: 8927417
    Abstract: A mechanism is provided by which signal travel distance within and between semiconductor device packages is reduced and substrate size and complexity can be reduced. This capacity is provided by virtue of a conductive via that intersects a wire bond molded within a package substrate. The via provides a direct electrical connection between an external signal transmitter or receiver and the points connected by the wire bond, and thereby avoiding the need for the signal to transit built up interconnects in the semiconductor device package. Conductive vias can provide connectivity through or to a package substrate, and can be through vias or blind vias. The conductive via is formed by either mechanical or laser drilling, and is filled using standard fill techniques, and is therefore readily incorporated into a package production flow.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 6, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Weng Foong Yap
  • Patent number: 8927337
    Abstract: A plurality of microelectronic assemblies (60) are made by severing an in-process unit including an upper substrate (40) and lower substrate (20) with microelectronic elements (36) disposed between the substrates. In a further embodiment, a lead frame (452) is joined to a substrate (440) so that the leads project from this substrate. Lead frame (452) is joined to a further substrate (470) with one or more microelectronic elements (436, 404, 406) disposed between the substrates.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: January 6, 2015
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Craig S. Mitchell, Masud Beroz
  • Patent number: 8921158
    Abstract: Semiconductor devices are described that are configured to have a state of operation defined by a connection between at least one inner bump assembly and a selected outer bump assembly. In an implementation, the semiconductor device, which may be a wafer-level (chip-scale) package semiconductor device, includes an integrated circuit chip, a plurality of outer bump assemblies disposed on the chip, and one or more inner bump assemblies disposed on the chip so that the inner bump assemblies are at least partially surrounded by the outer bump assemblies. At least one of the inner bump assemblies is configured to be connected to a selected outer bump assembly to cause the integrated circuit chip to have a desired state of operation.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: December 30, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Kymberly T. Christman, Roderick B. Hogan, Anand Chamakura
  • Patent number: 8916453
    Abstract: A semiconductor wafer includes a first main face and a second main face opposite to the first main face and a number of semiconductor chip regions. The wafer is diced along dicing streets to separate the semiconductor chip regions from each other. At least one metal layer is formed on the first main face of each one of the semiconductor chip regions.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: December 23, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gopalakrishnan Trichy Rengarajan, Armin Tilke
  • Patent number: 8916419
    Abstract: A semiconductor package assembly process that includes attaching one or more dies to a substrate; applying an adhesive material on a periphery of the substrate by an adhesive dispenser having a stamp-type dispensing head; applying a thermal interface material (TIM) on a top surface of the die by a TIM dispenser having a stamp-type dispensing head; and positioning a lid over the one or more dies and placing the lid on top of the adhesive material and the TIM by a lid carrier to encapsulate the one or more dies.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Kuan-Lin Ho, Jason Shen
  • Patent number: 8912045
    Abstract: Solder is simultaneously transferred from a mold to a plurality of 3D assembled modules to provide solder bumps on the modules. The mold includes cavities containing injected molten solder or preformed solder balls. A fixture including resilient pressure pads and vacuum lines extending through the pads applies pressure to the modules when they are positioned on the mold. Following reflow and solder transfer to the modules, the fixture is displaced with respect to the mold. The modules, being attached to the fixture by vacuum pressure through the pads, are displaced from the mold with the fixture.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, Jae-Woong Nah
  • Patent number: 8906743
    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: December 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Chan Yoo, Todd O. Bolken
  • Patent number: 8906744
    Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: December 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Meow Koon Eng, Yong Poo Chia, Suan Jeung Boon
  • Patent number: 8907471
    Abstract: A semiconductor device is described advantageously making use of the interposer principle. The semiconductor device comprises at least one semiconductor die, a window substrate being an inorganic substrate comprising at least one window-shaped cavity for mounting the at least one semiconductor die, the window substrate having interconnect structures. Furthermore, the at least one semiconductor die is positioned inside the at least one cavity and is connected to the interconnect structures, providing connections to another level of assembly or packaging of the semiconductor device. The invention also relates to a method of manufacturing such a semiconductor device.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: December 9, 2014
    Assignee: IMEC
    Inventors: Eric Beyne, Paresh Limaye
  • Patent number: 8900921
    Abstract: A semiconductor device has a core semiconductor device with a through silicon via (TSV). The core semiconductor device includes a plurality of stacked semiconductor die and semiconductor component. An insulating layer is formed around the core semiconductor device. A conductive via is formed through the insulating layer. A first interconnect structure is formed over a first side of the core semiconductor device. The first interconnect structure is electrically connected to the TSV. A second interconnect structure is formed over a second side of the core semiconductor device. The second interconnect structure is electrically connected to the TSV. The first and second interconnect structures include a plurality of conductive layers separated by insulating layers. A semiconductor die is mounted to the first interconnect structure. The semiconductor die is electrically connected to the core semiconductor device through the first and second interconnect structures and TSV.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: December 2, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Sun Mi Kim, OhHan Kim, KyungHoon Lee
  • Patent number: 8900924
    Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: December 2, 2014
    Inventors: Shu-Ming Chang, Tsang-Yu Liu, Yen-Shih Ho
  • Patent number: 8900925
    Abstract: In a method for manufacturing a diode, a semiconductor crystal wafer is used to produce a p-n or n-p junction, which extends in planar fashion across the top side of a semiconductor crystal wafer. Separation edges form perpendicularly to the top side of the semiconductor crystal wafer, which edges extend across the p-n or n-p junction. The separation of the semiconductor crystal wafer is achieved in that, starting from a disturbance, a fissure is propagated by local heating and local cooling of the semiconductor crystal wafer. The separation fissure thus formed extends along crystal planes of the semiconductor crystal, which avoids the formation of defects in the area of the p-n or n-p junction.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: December 2, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Alfred Goerlach, Robert Kolb
  • Patent number: 8889442
    Abstract: Provided is a method of transferring semiconductor elements formed on a non-flexible substrate to a flexible substrate. Also, provided is a method of manufacturing a flexible semiconductor device based on the method of transferring semiconductor elements. A semiconductor element grown or formed on the substrate may be efficiently transferred to the resin layer while maintaining an arrangement of the semiconductor elements. Furthermore, the resin layer acts as a flexible substrate supporting the vertical semiconductor elements.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-hyoung Cho, Jun-hee Choi, Jin-seung Sohn
  • Patent number: 8890296
    Abstract: A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: November 18, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yueh-Se Ho, Yan Xun Xue
  • Patent number: 8890292
    Abstract: A method for manufacturing a semiconductor device includes forming at least one stripe-shaped protection film over a multilayer film in a scribe region of a semiconductor substrate having a plurality of semiconductor element regions formed therein, the protection film having a thickness larger in a center portion thereof than at an end surface thereof and being made of a member which transmits a laser beam, and removing the multilayer film in the scribe region by irradiating the protection film with a laser beam.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: November 18, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyuki Watanabe
  • Patent number: 8883562
    Abstract: A stacked microelectronic unit is provided which can include a plurality of vertically stacked microelectronic elements each having a front surface, contacts exposed at the front surface, a rear surface and edges extending between the front and rear surfaces. Traces connected with the contacts may extend along the front surfaces towards edges of the microelectronic elements with the rear surface of at least one of the stacked microelectronic elements being adjacent to a top face of the microelectronic unit. A plurality of conductors may extend along edges of the microelectronic elements from the traces to the top face. The conductors may be conductively connected with unit contacts such that the unit contacts overlie the rear surface of the at least one microelectronic element adjacent to the top face.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: November 11, 2014
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Giles Humpston, David Ovrutsky, Laura Wills Mirkarimi
  • Patent number: 8877567
    Abstract: A semiconductor device has an interposer frame having a die attach area. A uniform height insulating layer is formed over the interposer frame at corners of the die attach area. The insulating layer can be formed as rectangular or circular pillars at the corners of the die attach area. The insulating layer can also be formed in a central region of the die attach area. A semiconductor die has a plurality of bumps formed over an active surface of the semiconductor die. The bumps can have a non-fusible portion and fusible portion. The semiconductor die is mounted over the insulating layer which provides a uniform standoff distance between the semiconductor die and interposer frame. The bumps of the semiconductor die are bonded to the interposer frame. An encapsulant is deposited over the semiconductor die and interposer frame and between the semiconductor die and interposer frame.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: November 4, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: KyungHoon Lee, Soo Moon Park, SeungWon Kim
  • Patent number: 8877523
    Abstract: A method for making a packaged integrated circuit is provided. The method includes making a first panel of encapsulated die. In some embodiments, if a threshold number of die are not positioned in proper positions in the first panel, the die are separated from the first panel. The separated die are subsequently encapsulated in other panels of encapsulated die. Conductive interconnects can be formed over the other panels. The other panels are then separated into integrated circuit packages.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: November 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: George R. Leal
  • Patent number: 8872334
    Abstract: In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: October 28, 2014
    Assignee: NEC Corporation
    Inventors: Shintaro Yamamichi, Katsumi Kikuchi, Yoshiki Nakashima, Kentaro Mori
  • Patent number: 8871569
    Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 28, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Doo Hwan Lee, Tae Sung Jeong, Yul Kyo Chung
  • Publication number: 20140312476
    Abstract: A no-exposed-pad ball grid array (BGA) packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of outer leads formed on the metal substrate and extending to the proximity of the die. A metal layer that contains a plurality of inner leads corresponding to the plurality of outer leads and extending to the proximity of the die is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Furthermore, the die and the plurality of inner leads are connected by metal wires, and a plurality of solder balls is attached to a back surface of the plurality of outer leads and a die pad. The die, the plurality of inner leads, and the metal wires are sealed with a molding compound.
    Type: Application
    Filed: April 22, 2014
    Publication date: October 23, 2014
    Applicant: Jiangsu Changjiang Electronics Technology Co., Ltd.
    Inventors: Xinchao WANG, Zhizhong LIANG
  • Publication number: 20140315350
    Abstract: A wafer process for MCSP comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer covering metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer and a thick metal layer at bottom surface of wafer in recessed space in a sequence; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and the metal seed and metal layers along the scribe line.
    Type: Application
    Filed: June 27, 2014
    Publication date: October 23, 2014
    Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Zhiqiang Niu, Guo Feng Lian, Hong Xia Fu, Yu Ping Gong
  • Patent number: 8865522
    Abstract: A method for connecting a semiconductor chip to a metal layer of a carrier substrate is disclosed. A semiconductor chip is provided which has a first side, a second side opposite the first side, a glass substrate bonded to the second side of the semiconductor chip and including at least one opening leaving an area of the second side of the semiconductor chip uncovered by the glass substrate, and a metallization region arranged in the opening of the glass substrate and electrically contacting the second side of the semiconductor chip. The semiconductor chip with the bonded glass substrate is brought onto a metal layer of a carrier substrate. A firm mechanical and electrical connection is formed between the metal layer of the carrier substrate and the metallization region.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Carsten von Koblinski, Gerald Lackner, Karin Schrettlinger, Markus Ottowitz