Making Plural Separate Devices Patents (Class 438/110)
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Patent number: 8669646Abstract: Methods and apparatus for improved electromagnetic interference (EMI) shielding and thermal performance in integrated circuit (IC) packages are described. A die-up or die-down package includes a protective lid, a plurality of ground posts, an IC die, and a substrate. The substrate includes a plurality of ground planes. The IC die is mounted to the substrate. Plurality of ground posts is coupled to plurality of ground planes that surround IC die. Protective lid is coupled to plurality of ground posts. The plurality of ground posts and the protective lid from an enclosure structure that substantially encloses the IC die, and shields EMI from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.Type: GrantFiled: May 31, 2011Date of Patent: March 11, 2014Assignee: Broadcom CorporationInventors: Mohammad Tabatabai, Abbas Amirichimeh, Lorenzo Longo
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Patent number: 8664043Abstract: A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern.Type: GrantFiled: December 1, 2009Date of Patent: March 4, 2014Assignee: Infineon Technologies AGInventors: Henrik Ewe, Joachim Mahler, Anton Prueckl, Stefan Landau
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Patent number: 8664044Abstract: A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.Type: GrantFiled: November 2, 2011Date of Patent: March 4, 2014Assignees: STMicroelectronics Pte Ltd., STMicroelectronics Grenoble 2 SASInventors: Yonggang Jin, Romain Coffy, Jerome Teysseyre
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Patent number: 8664041Abstract: A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components.Type: GrantFiled: April 12, 2012Date of Patent: March 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Jen Tseng, Guan-Yu Chen, Sheng-Yu Wu, Chen-Hua Yu, Mirng-Ji Lii, Chen-Shien Chen, Tin-Hao Kuo
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Patent number: 8664752Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: GrantFiled: March 26, 2012Date of Patent: March 4, 2014Assignee: Fairchild Semiconductor CorporationInventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
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Patent number: 8658468Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.Type: GrantFiled: August 9, 2012Date of Patent: February 25, 2014Assignee: Intel Mobile Communications GmbHInventors: Gottfried Beer, Irmgard Escher-Poeppel
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Patent number: 8653655Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: GrantFiled: August 6, 2013Date of Patent: February 18, 2014Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Patent number: 8653654Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base assembly having a cavity and a through conductor adjacent to the cavity; connecting a first device to the base assembly with the first device within the cavity; connecting a second device to the base assembly with the second device within the cavity; and connecting an interposer substrate having an exposed external side over the through conductor with the exposed external side facing away from the through conductor and exposed to ambient.Type: GrantFiled: December 16, 2009Date of Patent: February 18, 2014Assignee: Stats Chippac Ltd.Inventors: Harry Chandra, Robert J. Martin, III
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Patent number: 8654537Abstract: Electrical components such as integrated circuits may be mounted on a printed circuit board. To prevent the electrical components from being subjected to electromagnetic interference, radio-frequency shielding structures may be formed over the components. The radio-frequency shielding structures may be formed from a layer of metallic paint. Components may be covered by a layer of dielectric. Channels may be formed in the dielectric between blocks of circuitry. The metallic paint may be used to coat the surfaces of the dielectric and to fill the channels. Openings may be formed in the surface of the metallic paint to separate radio-frequency shields from each other. Conductive traces on the surface of the printed circuit board may be used in connecting the metallic paint layer to internal printed circuit board traces.Type: GrantFiled: December 1, 2010Date of Patent: February 18, 2014Assignee: Apple Inc.Inventors: Joseph Fisher, Jr., Sean Mayo, Dennis R. Pyper, Paul Nangeroni, Jose Mantovani
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Patent number: 8648444Abstract: A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation.Type: GrantFiled: March 24, 2008Date of Patent: February 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Shin-Puu Jeng, Yu-Wen Liu
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Patent number: 8647924Abstract: A method of forming a device stack is presented. The method includes providing a temporary substrate having a temporary mounting surface. A first chip is temporarily mounted to the temporary mounting surface. A first bottom surface of the first chip is temporarily mounted to the temporary mounting surface and a first top surface of the first chip comprises first interconnects. A second chip is stacked on the first chip. The second chip includes second conductive contacts on the second bottom surface. The method also includes bonding the first and second chips together to form the device stack. The second conductive contacts are coupled to the first interconnects. The first bottom surface of the first chip is separated from the substrate to separate the chip stack from the substrate.Type: GrantFiled: April 13, 2010Date of Patent: February 11, 2014Assignee: United Test and Assembly Center Ltd.Inventors: Chin Hock Toh, Keng Yuen Au, Reynaldo Vincent Hernandez Sta Agueda, Bee Liang Catherine Ng, Librado Amurao Gatbonton, Xue Ren Zhang, Yi-Sheng Anthony Sun
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Patent number: 8642384Abstract: A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate.Type: GrantFiled: March 9, 2012Date of Patent: February 4, 2014Assignee: STATS ChipPAC, Ltd.Inventors: JaeHyun Lee, KiYoun Jang, KyungHoon Lee, TaeWoo Lee
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Patent number: 8642388Abstract: A method for manufacturing LEDs includes following steps: forming circuit structures on a substrate, each circuit structure having a first metal layer and a second metal layer formed on opposite surfaces of the substrate and a connecting section interconnecting the first and second metal layers; cutting through each circuit structure along a middle of the connecting section to form first and second electrical connecting portions insulated from each other via a gap therebetween; arranging LED chips on the substrate and electrically connecting the LED chips to the first and second electrical connecting portions; forming an encapsulation on the substrate to cover the LED chips; and cutting through the substrate and the encapsulation between the first and second electrical connecting portions of neighboring circuit structures to obtain the LEDs.Type: GrantFiled: December 21, 2011Date of Patent: February 4, 2014Assignee: Advanced Optoelectronics Technology, Inc.Inventor: Chao-Hsiung Chang
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Patent number: 8637977Abstract: A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip.Type: GrantFiled: June 27, 2013Date of Patent: January 28, 2014Assignee: Infineon Technologies AGInventors: Boon Huat Lim, Chee Chian Lim, Yoke Chin Goh
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Patent number: 8637876Abstract: Disclosed are a light emitting device and a light emitting device package having the same. The light emitting device includes a plurality of light emitting cells including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; a first electrode layer connected to the first conductive semiconductor layer of a first light emitting cell of the plural light emitting cells; a plurality of second electrode layers under the light emitting cells, a portion of the second electrode layers being connected to the first conductive semiconductor layer of an adjacent light emitting cells; a third electrode layer disposed under a last light emitting cell of the plural light emitting cells; a first electrode connected to the first electrode layer; a second electrode connected to the third electrode layer; an insulating layer around the first to third electrode layers; and a support member under the insulating layer.Type: GrantFiled: August 30, 2010Date of Patent: January 28, 2014Assignee: LG Innotek Co., Ltd.Inventors: Sang Youl Lee, Jung Hyeok Bae, Ji Hyung Moon, Juno Song
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Patent number: 8637897Abstract: A semiconductor light emitting device includes a substrate and a plurality of light emitting cells arranged on the substrate. Each of the light emitting cells includes a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer disposed therebetween to emit blue light. An interconnection structure electrically connects the first-conductivity-type and the second-conductivity-type semiconductor layers of one light emitting cell to the first-conductivity-type and the second-conductivity-type semiconductor layers of another light emitting cell. A light conversion part is formed in a light emitting region defined by the light emitting cells and includes a red and/or a green light conversion part respectively having a red and/or a green light conversion material.Type: GrantFiled: February 25, 2011Date of Patent: January 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Je Won Kim, Tae Sung Jang, Jong Gun Woo, Jong Ho Lee
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Patent number: 8633058Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; connecting an integrated circuit die to the substrate, with the integrated circuit die having peripheral sides; molding a step mold covering one of the peripheral sides; attaching an intermediate die directly over the integrated circuit die, offset to one of the peripheral sides adjacent to the step mold; and directly connecting the intermediate die to the substrate.Type: GrantFiled: March 21, 2011Date of Patent: January 21, 2014Assignee: Stats Chippac Ltd.Inventors: DaeSik Choi, Jong-Woo Ha, Seung Won Kim
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Patent number: 8633089Abstract: An array of semiconductor components, comprising a first plurality of semiconductor components and a second plurality of semiconductor components held on a carrier, is bonded onto one or more substrates. The first plurality of semiconductor components is first located for pick-up by a transfer device, and each semiconductor component comprised in the first plurality of semiconductor components is picked up with the transfer device and is bonded onto a respective bonding position on the one or more substrates. After the first plurality of semiconductor components have been picked up and bonded, the carrier is rotated and the second plurality of semiconductor components is located for pick-up by the transfer device. Thereafter, each semiconductor component comprised in the second plurality of semiconductor components is picked up with the transfer device and is bonded onto a respective bonding position on the one or more substrates.Type: GrantFiled: March 28, 2011Date of Patent: January 21, 2014Assignee: ASM Assembly Automation LtdInventors: Man Chung Ng, Keung Chau
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Patent number: 8629043Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.Type: GrantFiled: November 16, 2011Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Jui-Pin Hung, Chih-Hao Chen, Chun-Hsing Su, Yi-Chao Mao, Kung-Chen Yeh, Yi-Lin Tsai, Ying-Tz Hung, Chin-Fu Kao, Shih-Yi Syu, Chin-Chuan Chang, Hsien-Wen Liu, Long Hua Lee
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Publication number: 20140008809Abstract: A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer.Type: ApplicationFiled: September 12, 2013Publication date: January 9, 2014Applicant: Deca Technologies, Inc.Inventor: Christopher M. Scanlan
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Patent number: 8623700Abstract: The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.Type: GrantFiled: November 15, 2006Date of Patent: January 7, 2014Assignee: University of Notre Dame du LacInventors: Gary H. Bernstein, Patrick Fay, Wolfgang Porod, Qing Liu
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Patent number: 8617926Abstract: A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.Type: GrantFiled: September 9, 2010Date of Patent: December 31, 2013Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Z. Su, Gamal Refai-Ahmed, Bryan Black
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Publication number: 20130337608Abstract: According to the present invention, a structure of a semiconductor device in which adhesive deposits are reduced and yield is excellent; and a process for manufacturing the same can be provided. A process for manufacturing a semiconductor device according to the present invention includes: a step of arranging plural semiconductor elements (106) on a main surface of a thermal release adhesive layer (mount film); a step of forming an encapsulant layer (108), which encapsulates the plural semiconductor elements (106) on the main surface of the mount film, using a semiconductor-encapsulating resin composition; and a step of peeling off the mount film to expose a lower surface (30) of the encapsulant layer (108) and lower surfaces (20) of the semiconductor elements (106). A contact angle of the lower surface (30) of the encapsulant layer (108) is less than or equal to 70° when measured using formamide after the step of peeling off the mount film.Type: ApplicationFiled: March 9, 2012Publication date: December 19, 2013Applicant: SUMITOMO BAKELITE CO., LTD.Inventors: Takahiro Kotani, Masakatsu Maeda
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Patent number: 8609470Abstract: A substrate-free semiconducting sheet has an array of semiconducting elements dispersed in a matrix material. The matrix material is bonded to the edge surfaces of the semiconducting elements and the substrate-free semiconducting sheet is substantially the same thickness as the semiconducting elements.Type: GrantFiled: April 16, 2012Date of Patent: December 17, 2013Assignee: Goldeneye, Inc.Inventors: Karl W. Beeson, Scott M. Zimmerman, William R. Livesay, Richard L. Ross
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Patent number: 8609464Abstract: To provide a simple method for manufacturing a semiconductor device in which deterioration in characteristics due to electrostatic discharge is reduced, a plurality of element layers each having a semiconductor integrated circuit and an antenna are sealed between a first insulator and a second insulator; a layered structure having a first conductive layer formed on a surface of the first insulator, the first insulator, the element layers, the second insulator, and a second conductive layer formed on a surface of the second insulator is formed; and the first insulator and the second insulator are melted, whereby the layered structure is divided so as to include at least one of the semiconductor integrated circuits and one of the antennas.Type: GrantFiled: June 2, 2009Date of Patent: December 17, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiaki Oikawa, Hironobu Shoji, Shingo Eguchi
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Patent number: 8609446Abstract: A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating.Type: GrantFiled: October 6, 2011Date of Patent: December 17, 2013Assignee: TSMC Solid State Lighting Ltd.Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chih-Kuang Yu, Hung-Yi Kuo
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MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads
Patent number: 8597985Abstract: In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predetermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.Type: GrantFiled: February 1, 2012Date of Patent: December 3, 2013Assignee: Sandia CorporationInventors: Rajen Chanchani, Christopher Nordquist, Roy H. Olsson, Tracy C. Peterson, Randy J. Shul, Catalina Ahlers, Thomas A. Plut, Gary A. Patrizi -
Patent number: 8598690Abstract: A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate.Type: GrantFiled: January 27, 2012Date of Patent: December 3, 2013Assignee: STATS ChipPAC, Ltd.Inventors: Harry Chandra, Flynn Carson
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Patent number: 8597981Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a microelectronic device includes a microelectronic die, a plurality of electrical couplers projecting from the die, and a flowable material disposed on the die. The die includes an integrated circuit and a plurality of terminals operably coupled to the integrated circuit. The electrical couplers are attached to corresponding terminals on the die. The flowable material includes a plurality of spacer elements sized to space the die apart from another component. The flowable material may be a no-flow underfill, a flux compound, or other suitable material.Type: GrantFiled: December 30, 2010Date of Patent: December 3, 2013Assignee: Micron Technology, Inc.Inventor: Rick C. Lake
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Patent number: 8598619Abstract: A semiconductor light emitting device includes a substrate and a plurality of light emitting cells arranged on the substrate. Each of the light emitting cells includes a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer disposed therebetween to emit blue light. An interconnection structure electrically connects the first-conductivity-type and the second-conductivity-type semiconductor layers of one light emitting cell to the first-conductivity-type and the second-conductivity-type semiconductor layers of another light emitting cell. A light conversion part is formed in a light emitting region defined by the light emitting cells and includes a red and/or a green light conversion part respectively having a red and/or a green light conversion material.Type: GrantFiled: February 24, 2011Date of Patent: December 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Je Won Kim, Tae Sung Jang, Jong Gun Woo, Jong Ho Lee
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Patent number: 8598631Abstract: A semiconductor integrated circuit chip mounted on a substrate by flip chip bonding includes: a plurality of electrode pads; a corner portion of a flat periphery of an inner layer; a first linear region adjoining one side of the corner portion; a second linear region adjoining another side of the corner portion; and a third linear region adjoining a side of the first linear region opposite to the side adjoining the corner portion. A circuit core placeable region is provided in at least part of the corner portion and the first linear region. A plurality of IO cells connected to the electrode pads are arranged in the second and third linear regions. The IO cells in the second linear region are connected to the electrode pads arranged inwardly in n rows×n columns from a corner of the chip above the corner portion.Type: GrantFiled: May 7, 2013Date of Patent: December 3, 2013Assignee: Panasonic CorporationInventor: Shiro Usami
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Patent number: 8592993Abstract: A monolithic integrated electronic device includes a substrate having a surface region and one or more integrated micro electro-mechanical systems and electronic devices provided on a first region overlying the surface region. Each of the integrated micro electro-mechanical systems and electronic devices has one or more contact regions. The first region has a first surface region. One or more trench structures are disposed within one or more portions of the first region. A passivation material overlies the first region and the one or more trench structures. A conduction material overlies the passivation material, the one or more trench structures, and one or more of the contact regions. The device also has one or more edge bond pad structures within a vicinity of the one or more bond pad structures, which are formed by a singulation process within a vicinity of the one or more bond pad structures.Type: GrantFiled: January 25, 2013Date of Patent: November 26, 2013Assignee: mCube Inc.Inventor: Xiao (Charles) Yang
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Patent number: 8593914Abstract: A method and system for providing an energy assisted magnetic recording (EAMR) head are described. The EAMR head includes a laser, a slider, and an EAMR transducer. The laser has a main emitter and at least one alignment emitter. The slider includes at least one alignment waveguide, at least one output device, and an air-bearing surface (ABS). The alignment waveguide(s) are aligned with the alignment emitter(s). The EAMR transducer is coupled with the slider and includes a waveguide aligned with main emitter. The waveguide is for directing energy from the main emitter toward the ABS.Type: GrantFiled: December 22, 2010Date of Patent: November 26, 2013Assignee: Western Digital (Fremont), LLCInventors: Lei Wang, Shing Lee, Sergei Sochava, Hyojune Lee, Arkadi B. Goulakov
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Patent number: 8586413Abstract: A multi-chip module and a method for manufacturing the multi-chip module that mitigates wire breakage. A first semiconductor chip is mounted and wirebonded to a support substrate. A spacer is coupled to the first semiconductor chip. A support material is disposed on the spacer and a second semiconductor chip is positioned on the support material. The second semiconductor chip is pressed into the support material squeezing it into a region adjacent the spacer and between the first and second semiconductor chips. Alternatively, the support material is disposed on the first semiconductor chip and a die attach material is disposed on the spacer. The second semiconductor chip is pressed into the die attach material and the support material, squeezing a portion of the support material over the spacer edges. Wirebonds are formed between the support substrate and the first and second semiconductor chips.Type: GrantFiled: May 4, 2005Date of Patent: November 19, 2013Assignee: Spansion LLCInventors: Yin Lye Foong, Cheng Sim Kee, Lay Hong Lee, Mohamed Suhaizal Bin Abu-Hassan
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Publication number: 20130299973Abstract: A semiconductor device has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semiconductor die and TSV wafer. Conductive TMV are formed through the encapsulant over the conductive TSV and contact pads of the semiconductor die. The conductive TMV can be formed through the channel. A conductive layer is formed over the encapsulant and electrically connected to the conductive TMV. The conductive TMV are formed during the same manufacturing process. An insulating layer is formed over the encapsulant and conductive layer. A plurality of semiconductor die of the same size or different sizes can be stacked over the TSV wafer. The plurality of semiconductor die can be stacked over opposite sides of the TSV wafer. An internal stacking module can be stacked over the semiconductor die and electrically connected through the conductive TMV.Type: ApplicationFiled: July 16, 2013Publication date: November 14, 2013Inventors: DaeSik Choi, Young Jin Woo, TaeWoo Lee
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Patent number: 8580614Abstract: A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer.Type: GrantFiled: January 4, 2013Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Jing-Cheng Lin
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Publication number: 20130288433Abstract: Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.Type: ApplicationFiled: June 24, 2013Publication date: October 31, 2013Inventor: Paul A. Farrar
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Patent number: 8569882Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a central integrated circuit over the base substrate; mounting a side package having a side package substrate along a peripheral region of the base substrate and laterally peripheral to the central integrated circuit with the side package substrate coplanar with the central integrated circuit; and encapsulating the central integrated circuit and the side package above the base substrate with a base encapsulation to form a planar surface over the central integrated circuit and the side package facing away from the base substrate.Type: GrantFiled: March 24, 2011Date of Patent: October 29, 2013Assignee: Stats Chippac Ltd.Inventors: WonJun Ko, Sungmin Song, Jong Wook Ju, JaEun Yun, Hye Ran Lee
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Patent number: 8569881Abstract: A semiconductor device includes a baseplate and a first and a second insulated gate bipolar transistor (IGBT) substrate coupled to the baseplate. The semiconductor device includes a first and a second diode substrate coupled to the baseplate and a first, a second, and a third control substrate coupled to the baseplate. Bond wires couple the first and second IGBT substrates to the first control substrate. Bond wires couple the first and second IGBT substrates to the second control substrate via the first and second diode substrates, and bond wires couple the first and second IGBT substrates to the third control substrate via the second diode substrate.Type: GrantFiled: September 8, 2010Date of Patent: October 29, 2013Assignee: Infineon Technologies AGInventors: Reinhold Spanke, Waleri Brekel, Ivonne Benzler
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Patent number: 8563359Abstract: A method for manufacturing a semiconductor device includes forming at least one stripe-shaped protection film over a multilayer film in a scribe region of a semiconductor substrate having a plurality of semiconductor element regions formed therein, the protection film having a thickness larger in a center portion thereof than at an end surface thereof and being made of a member which transmits a laser beam, and removing the multilayer film in the scribe region by irradiating the protection film with a laser beam.Type: GrantFiled: March 18, 2011Date of Patent: October 22, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Naoyuki Watanabe
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Patent number: 8564012Abstract: A method for manufacturing an optoelectronic apparatus includes attaching bottom surfaces of first and second packaged optoelectronic semiconductor devices (POSDs) to a carrier substrate (e.g., a tape) so that there is a space between the first and second POSDs. An opaque molding compound is molded around portions of the first and second POSDs attached to the carrier substrate, so that peripheral surfaces of the first POSD and the second POSD are surrounded by the opaque molding compound, the space between the first and second POSDs is filled with the opaque molding compound, and the first and second POSDs are attached to one another by the opaque molding compound. The carrier substrate is thereafter removed so that electrical contacts on the bottom surfaces of the first and second POSDs are exposed. A window for each of the POSDs is formed during the molding process or thereafter.Type: GrantFiled: March 27, 2012Date of Patent: October 22, 2013Assignee: Intersil Americas LLCInventors: Seshasayee S. Ankireddi, Lynn K. Wiese
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Patent number: 8563357Abstract: A method of attaching a die to a substrate is disclosed. A major surface of the die has an array of electrical contacts, and is covered with a tape segment having an array of apertures in register with the contacts. Solder balls are inserted into the apertures. The die is positioned against a substrate with the solder balls in register with the die pads on the surface of the substrate, and a heat treatment process is performed to bond the conductive elements to the corresponding bond pads.Type: GrantFiled: June 26, 2008Date of Patent: October 22, 2013Assignee: Infineon Technologies AGInventor: Chee Chian Lim
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Patent number: 8563405Abstract: A method for manufacturing semiconductor device includes the following steps. First, a carrier substrate and a plurality of pieced segments of wafer are provided. Each of the pieced segments of wafer has an active surface and a back surface on opposite sides thereof. Further, there is at least a bonding pad disposed on the active surface. Next, an adhering layer is formed between the carrier substrate and the active surfaces of the pieced segments of wafer, so as to make the pieced segments of wafer adhere to the carrier substrate. Next, a through silicon via is formed in each of the pieced segments of wafer to electrically connect to the bonding pad correspondingly. Then, the pieced segments of wafer are separated from the carrier substrate.Type: GrantFiled: May 6, 2010Date of Patent: October 22, 2013Assignee: Ineffable Cellular Limited Liability CompanyInventor: Wen-Hsiung Chang
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Patent number: 8557636Abstract: A semiconductor system in a package in which at least first and second semiconductor substrates are mounted one above the other on a package substrate. The first substrate is mounted on the package substrate with its active (or front) side facing the package substrate. A plurality of through-silicon-vias (TSVs) extend through one or more peripheral regions of the first substrate; and a redistribution layer is located on the back side of the first substrate and connected to the TSVs. The second substrate is mounted on the first substrate and electrically connected to circuits in the active side of the first substrate through the redistribution layer and the TSVs. Illustratively, one of the substrates is an FPGA and one or more of the other substrates stores the configuration memory and/or other functional memory for the FPGA.Type: GrantFiled: September 13, 2012Date of Patent: October 15, 2013Assignee: Altera CorporationInventor: Rakesh H. Patel
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Patent number: 8551815Abstract: A stacked microelectronic unit is provided which has a top surface and a bottom surface remote from the top surface and a plurality of vertically stacked microelectronic elements therein, including at least one microelectronic element having a front face adjacent to the top surface and a rear face oriented towards the bottom surface. Each of the microelectronic elements has traces extending from contacts at the front face beyond edges of the microelectronic element. A dielectric layer contacts edges of the microelectronic elements and underlies the rear face of the at least one microelectronic element. Leads are connected to the traces extending along the dielectric layer. Unit contacts, exposed at the top surface, are connected to the leads.Type: GrantFiled: August 1, 2008Date of Patent: October 8, 2013Assignee: Tessera, Inc.Inventors: Osher Avsian, Andrey Grinman, Giles Humpston, Moti Margalit
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Patent number: 8551814Abstract: A wafer structure (88) includes a device wafer (20) and a cap wafer (60). Semiconductor dies (22) on the device wafer (20) each include a microelectronic device (26) and terminal elements (28, 30). Barriers (36, 52) are positioned in inactive regions (32, 50) of the device wafer (20). The cap wafer (60) is coupled to the device wafer (20) and covers the semiconductor dies (22). Portions (72) of the cap wafer (60) are removed to expose the terminal elements (28, 30). The barriers (36, 52) may be taller than the elements (28, 30) and function to prevent the portions (72) from contacting the terminal elements (28, 30) when the portions (72) are removed. The wafer structure (88) is singulated to form multiple semiconductor devices (89), each device (89) including the microelectronic device (26) covered by a section of the cap wafer (60) and terminal elements (28, 30) exposed from the cap wafer (60).Type: GrantFiled: March 11, 2010Date of Patent: October 8, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Lisa H. Karlin, Lianjun Liu, Alex P. Pamatat, Paul M Winebarger
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Patent number: 8552498Abstract: A semiconductor device in which defects in characteristics due to electrostatic discharge is reduced and a method for manufacturing the semiconductor device are provided. The semiconductor device has at least one of these structures: (1) a structure in which a first and second insulating films are in direct contact with each other in a peripheral region of a circuit portion, (2) a structure in which a first and second insulators are closely attached to each other, and (3) a structure in which a first conductive layer and a second conductive layer are provided on outer surfaces of the first insulator and the second insulator, respectively, and electrical conduction between the first and second conductive layers is achieved at a side surface of the peripheral region. Note that the conduction at the side surface can be achieved by cutting a plurality of semiconductor devices into separate semiconductor devices.Type: GrantFiled: September 16, 2009Date of Patent: October 8, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shingo Eguchi, Yoshiaki Oikawa
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Patent number: 8551817Abstract: A wafer having a front face formed with a functional device is irradiated with laser light while positioning a light-converging point within the wafer with the rear face of the wafer acting as a laser light incident face, so as to generate multiphoton absorption, thereby forming a starting point region for cutting due to a molten processed region within the wafer along a line. Consequently, a fracture can be generated from the starting point region for cutting naturally or with a relatively small force, so as to reach the front face and rear face. Therefore, when an expansion film is attached to the rear face of the wafer by way of a die bonding resin layer after forming the starting point region for cutting and then expanded, the wafer and die bonding resin layer can be cut along the line.Type: GrantFiled: October 7, 2011Date of Patent: October 8, 2013Assignee: Hamamatsu Photonics K.K.Inventors: Kenshi Fukumitsu, Fumitsugu Fukuyo, Naoki Uchiyama, Ryuji Sugiura, Kazuhiro Atsumi
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Patent number: 8551812Abstract: In a manufacturing method of a printed circuit board, a rigid substrate having a rigid-board metal layer is provided, an open slot is formed on the rigid substrate, and a flexible substrate is installed in the open slot, and the flexible substrate and the rigid substrate are securely bonded, and an increased-layer circuit layer is formed after electric circuits are manufactured on the rigid-board and flexible-board metal layers, and stacked on the rigid substrate and on an adjacent block where the flexible substrate is coupled to the rigid substrate, and an electric circuit is manufactured, and the increased-layer circuit layer is provided for electrically connecting and conducting the rigid and flexible substrates to overcome the issue of alignment errors.Type: GrantFiled: January 18, 2012Date of Patent: October 8, 2013Assignee: Unitech Printed Circuit Board Corp.Inventors: Ming Yi Yeh, Jia Lin Liu, Chung Shih Wu
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Patent number: 8546193Abstract: A semiconductor device has a plurality of bumps formed over a carrier. A semiconductor die is mounted to the carrier between the bumps. A penetrable film encapsulant layer having a base layer, first adhesive layer, and second adhesive layer is placed over the semiconductor die and bumps. The penetrable film encapsulant layer is pressed over the semiconductor die and bumps to embed the semiconductor die and bumps within the first and second adhesive layers. The first adhesive layer and second adhesive layer are separated to remove the base layer and first adhesive layer and leave the second adhesive layer around the semiconductor die and bumps. The bumps are exposed from the second adhesive layer. The carrier is removed. An interconnect structure is formed over the semiconductor die and second adhesive layer. A conductive layer is formed over the second adhesive layer electrically connected to the bumps.Type: GrantFiled: November 2, 2010Date of Patent: October 1, 2013Assignee: STATS ChipPAC, Ltd.Inventors: Byung Tai Do, Reza A. Pagaila, Linda Pei Ee Chua