Substrate Dicing Patents (Class 438/113)
  • Patent number: 11361878
    Abstract: The present invention relates to a method for manufacturing an insulating layer which can minimize the degree of warpage caused by polymer shrinkage at the time of curing and secure the stability of a semiconductor chip located therein, and a method for manufacturing a semiconductor package using an insulating layer obtained from the manufacturing method of the insulating layer.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: June 14, 2022
    Assignee: LG CHEM, LTD.
    Inventors: Woo Jae Jeong, You Jin Kyung, Byung Ju Choi, Bo Yun Choi, Kwang Joo Lee, Min Su Jeong
  • Patent number: 11355365
    Abstract: Introduced is a micro-chip gripper comprising: a pin plate of which one surface is coupled to another apparatus; a hole plate of which one surface faces the other surface of the pin plate while being disposed to be spaced apart therefrom by a fixed distance, and which is driven together with the drive of the pin plate, and in which a plurality of holes making a fixed pattern are formed; pins which are inserted into the holes of the hole plate and of which one end part is supported by the pin plate; and an adhesion layer which covers the other surface of the hole plate. Other embodiments are possible.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: June 7, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changjoon Lee, Byunghoon Lee, Min Park, Kyungwoon Jang, Jeonggen Yoon, Hyuntae Jang
  • Patent number: 11342426
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes. The semiconductor part is provided between the first and second electrodes. A method of manufacturing the device includes forming the first electrode covering a back surface of a wafer after the second electrode is formed on a front surface of the wafer; forming a first groove by selectively removing the first electrode; and dividing the wafer by forming a second groove at the front surface side. The wafer includes a region to be the semiconductor part; and the first and second grooves are provided along a periphery of the region. The first groove is in communication with the first groove. The second groove has a width in a direction along the front surface of the wafer, the width of the first groove being narrower than a width of the first groove in the same direction.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: May 24, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Shinji Nunotani, Shinji Onzuka
  • Patent number: 11329021
    Abstract: A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Fabian Craes, Barbara Eichinger, Martin Mischitz, Frederik Otto, Fabien Thion
  • Patent number: 11315804
    Abstract: A manufacturing method of a mounting structure, the method including a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member; a disposing step of disposing a thermosetting sheet and a thermoplastic sheet on the mounting member, with the thermosetting sheet interposed between the thermoplastic sheet and the first circuit member; a first sealing step of pressing a stack of the thermosetting sheet and the thermoplastic sheet against the first circuit member, and heating the stack, to seal the second circuit members and to cure the thermosetting sheet into a first cured layer; a removal step of removing the thermoplastic sheet from the first cured layer; and a coating film formation step of forming a coating film on the first cured layer, after the removal step.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 26, 2022
    Assignee: NAGASE CHEMTEX CORPORATION
    Inventors: Eiichi Nomura, Yutaka Miyamoto, Takayuki Hashimoto
  • Patent number: 11276737
    Abstract: A method of forming a pattern part includes forming a first film on a target object, the first film having a first cure shrinkage ratio, forming a second film on the first film, the second film having a second cure shrinkage ratio greater than the first cure shrinkage ratio, and patterning the first film and the second film to form a pattern.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: March 15, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seungcheol Ko, Junho Sim, Seyoon Oh
  • Patent number: 11270897
    Abstract: An apparatus and associated method for high speed and/or mass transfer of electronic components onto a substrate comprises transferring, using an ejector assembly, electronics components (e.g., light emitting devices) from a die sheet onto an adhesive receiving structure to form a predefined pattern including electronic components thereon, and then transferring the electronic components defining the predefined pattern onto a substrate (e.g., a translucent superstrate) for light emission therethrough to create a high-density (e.g., high resolution) display device utilizing, for example, mini- or micro-LED display technologies.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: March 8, 2022
    Assignee: CREELED, INC.
    Inventors: Christopher P. Hussell, Peter Scott Andrews
  • Patent number: 11260646
    Abstract: A method of processing a substrate, with a first major surface of the substrate removably bonded to a first major surface of a first carrier and a second major surface of the substrate removably bonded to a first major surface of a second carrier, includes initiating debonding at a first location of an outer peripheral bonded interface between the substrate and the first carrier to separate a portion of the first carrier from the substrate. The method further includes propagating a first debond front from the first debonded location along a first direction extending away from the first debonded location by sequentially applying a plurality of lifting forces to the first carrier at a corresponding plurality of sequential lifting locations of the first carrier.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: March 1, 2022
    Assignee: CORNING INCORPORATED
    Inventors: Christina Sue Bennett, Raymond Charles Cady, Hyun-Soo Choi, Claire Renata Coble, Byungchul Kim, Timothy Michael Miller, Joseph William Soper, Gary Carl Weber
  • Patent number: 11244923
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. For example, various aspects of this disclosure provide a semiconductor device having an ultra-thin substrate, and a method of manufacturing a semiconductor device having an ultra-thin substrate. As a non-limiting example, a substrate structure comprising a carrier, an adhesive layer formed on the carrier, and an ultra-thin substrate formed on the adhesive layer may be received and/or formed, components may then be mounted to the ultra-thin substrate and encapsulated, and the carrier and adhesive layer may then be removed.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: February 8, 2022
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventor: Ronald Huemoeller
  • Patent number: 11244862
    Abstract: A method for manufacturing semiconductor devices includes: forming a plurality of semiconductor devices in a first region of a primary surface of a wafer; forming a plurality of cleave initiation portions in a second region of a primary surface different from the first region; and cleaving the wafer sequentially, using the plurality of cleave initiation portions as initiation points, starting from a cleave initiation portion that is relatively difficult to cleave among the plurality of cleave initiation portions. Forming the plurality of cleave initiation portions includes forming the plurality of first grooves by etching portions of the second region. Due to this, the yield and the manufacturing efficiency for semiconductor devices can be enhanced.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 8, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kenji Yoshikawa, Masato Negishi, Masato Suzuki, Tatsuro Yoshino
  • Patent number: 11195769
    Abstract: A thermosetting composition for use as an underfill material contains: a mono- or bifunctional acrylic compound; a thermo-radical polymerization initiator; silica; and an elastomer including a 1,2-vinyl group. The thermosetting composition is liquid and has a property of turning, when cured thermally, into a cured product having a relative dielectric constant of 3.2 or less at 25° C. and a dielectric loss tangent of 0.013 or less at 25° C.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: December 7, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shigeru Yamatsu, Naoki Kanagawa
  • Patent number: 11189609
    Abstract: Methods for reducing heat transfer in semiconductor devices, and associated systems and devices, are described herein. In some embodiments, a method of manufacturing a semiconductor device includes forming a channel in a region of a substrate between a first die stack and a second die stack. The first die stack includes a plurality of first dies attached to each other by first film layers and the second die stack includes a plurality of second dies attached to each other by second film layers. The channel extends entirely through a thickness of the substrate. The method also includes applying heat to the first die stack to cure the first film layers. The channel reduces heat transfer from the first die stack to the second die stack.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: November 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, Andrew M. Bayless
  • Patent number: 11152322
    Abstract: In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D1 according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D2 according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D1 is shallower than a height H of the metal strip, and the depth D2 is also shallower than the height H. Other embodiments are presented.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: October 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K. Koduri
  • Patent number: 11137559
    Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: October 5, 2021
    Assignee: XINTEC INC.
    Inventors: Jiun-Yen Lai, Yu-Ting Huang, Hsing-Lung Shen, Tsang-Yu Liu, Hui-Hsien Wu
  • Patent number: 11136479
    Abstract: The electrically conductive adhesive film comprises a metal particle (P), a resin (M) and a prescribed sulfide compound (A), the resin (M) comprises a thermosetting resin (M1), and the metal particle (P) has an average particle size (d50) of 20 ?m or less and comprises 10% by mass or more of a first metal particle (P1) having a fractal dimension of 1.1 or more when viewed in a projection drawing in a primary particle state.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: October 5, 2021
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Naoaki Mihara, Noriyuki Kirikae, Jirou Sugiyama
  • Patent number: 11114408
    Abstract: Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: September 7, 2021
    Assignee: Invensas Corporation
    Inventors: Hong Shen, Liang Wang, Guilian Gao
  • Patent number: 11114630
    Abstract: A display panel is provided, including a substrate on a base, a transistor stack on the substrate, and a fluorescent layer between the base and the transistor stack. The fluorescent layer is configured to prevent light from damaging an active layer in the transistor stack in a laser lift-off process, and an orthographic projection of the fluorescent layer on the base overlaps an orthographic projection of the active layer on the base. A display device comprising the display panel, and a manufacturing method of the display panel are further provided.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: September 7, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Shipei Li, Qi Yao, Wusheng Li, Jiangnan Lu, Huili Wu, Fang He, Renquan Gu, Dongsheng Yin, Sheng Xu, Wei He
  • Patent number: 11098226
    Abstract: The electrically conductive adhesive film comprises a metal particle (P), a resin (M) and a prescribed sulfide compound (A), the resin (M) comprises a thermosetting resin (M1), and the metal particle (P) has an average particle size (d50) of 20 ?m or less and comprises 10% by mass or more of a first metal particle (P1) having a fractal dimension of 1.1 or more when viewed in a projection drawing in a primary particle state.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: August 24, 2021
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Naoaki Mihara, Noriyuki Kirikae, Jirou Sugiyama
  • Patent number: 11088041
    Abstract: Semiconductor packages are disclosed. A semiconductor package includes an integrated circuit, a first die and a second die. The first die includes a first bonding structure and a first seal ring. The first bonding structure is bonded to the integrated circuit and disposed at a first side of the first die. The second die includes a second bonding structure. The second bonding structure is bonded to the integrated circuit and disposed at a first side of the second die. The first side of the first die faces the first side of the second die. A first portion of the first seal ring is disposed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Chih-Chia Hu
  • Patent number: 11075071
    Abstract: To provide a wafer processing method which can simplify the wafer processing process and efficiently obtain chips of stable quality. A wafer processing method includes: a tape attaching step of attaching a back grinding tape to the front surface of a wafer; a modified region forming step of applying a laser beam from the back surface of the wafer along a cut line to form modified regions inside the wafer; a back surface processing step of processing the back surface of the wafer having the modified regions to reduce a thickness of the wafer; and a dividing step of, in a state in which the back grinding tape is attached to the front surface of the wafer, applying a load to the cut line from the back surface of the wafer to divide the wafer along the cut line and obtain individual chips.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: July 27, 2021
    Assignee: TOKYO SEIMITSU CO., LTD.
    Inventors: Ryosuke Kataoka, Takashi Tamogami, Syuhei Oshida
  • Patent number: 11037883
    Abstract: Techniques are provided for containing magnetic fields generated by an integrated switching package and for reducing electromagnetic interference generated from an integrated switching package.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 15, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Leonard Shtargot, Zafer Kutlu, John Underhill Gardner
  • Patent number: 11031276
    Abstract: A wafer expanding method for expanding a wafer having a plurality of rectangular devices respectively formed in a plurality of separate regions defined by a plurality of division lines, thereby increasing spacing between any adjacent ones of the devices, each rectangular device having a pair of shorter sides and a pair of longer sides. The wafer expanding method includes a jig preparing step of preparing an annular jig having an elliptical opening, the elliptical opening having a shorter portion for restricting a width of the annular exposed portion in a first direction where the shorter sides of the devices extend to a first width and a longer portion for restricting the width of the annular exposed portion in a second direction where the longer sides of the devices extend to a second width larger than the first width.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: June 8, 2021
    Assignee: DISCO CORPORATION
    Inventors: Yoshihiro Kawaguchi, Masaru Nakamura
  • Patent number: 11024220
    Abstract: Apparatus and method relating generally to an LED display is disclosed. In such an apparatus, a driver die has a plurality of driver circuits. A plurality of light-emitting diodes, each having a thickness of 10 microns or less and discrete with respect to one another, are respectively interconnected to the plurality of driver circuits. The plurality of light-emitting diodes includes a first portion for a first color, a second portion for a second color, and a third portion for a third color respectively obtained from a first, a second, and a third optical wafer. The first, the second, and the third color are different from one another.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: June 1, 2021
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Rajesh Katkar, Javier A. Delacruz, Ilyas Mohammed, Belgacem Haba
  • Patent number: 11018044
    Abstract: A wafer expanding method increases spacing between adjacent devices formed on a wafer. The method includes preparing an annular jig having a first restricting portion, a second restricting portion, and a curved restricting portion connecting the first restricting portion and the second restricting portion, mounting a ring frame supporting the wafer through an adhesive tape on a cylindrical frame fixing member, next mounting the annular jig on the ring frame, and next fixing the ring frame and the annular jig to the cylindrical frame fixing member, and operating a cylindrical pushing member having an outer circumference corresponding to an outer circumference of the wafer to push up an annular exposed portion of the adhesive tape defined between the wafer and the ring frame and thereby lift the wafer away from the ring frame, thereby expanding the annular exposed portion and increasing the spacing between the adjacent devices.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: May 25, 2021
    Assignee: DISCO CORPORATION
    Inventors: Masaru Nakamura, Saki Kozuma
  • Patent number: 11004759
    Abstract: An electronic component includes a resin structure including first and second surfaces facing each other, an electronic component element contained in the resin structure, including first and second main surfaces facing each other, and side surfaces connecting the first and second main surfaces, and being exposed to the first surface of the resin structure, and a through-electrode penetrating the resin structure to connect the first and second surfaces of the resin structure, in which the through-electrode are in contact with at least one of the side surfaces of the electronic component element.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: May 11, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hiroshi Somada
  • Patent number: 10978607
    Abstract: A device includes a substrate and an optoelectronic chip buried in the substrate. The substrate may include an opening above a first optical transduction region of the first optoelectronic chip and above a second optical transduction region of a second optoelectronic chip.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: April 13, 2021
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Alexandre Coullomb, Romain Coffy, Jean-Michel Riviere
  • Patent number: 10971400
    Abstract: A semiconductor device includes a device layer having a semiconductor element and a wiring layer, a first structure, a second structure at an outer periphery of the first structure and having a thickness smaller than that of the first structure, and a conductive layer that covers the first structure and the second structure. The first structure comprises a first substrate having the device layer formed on a first surface thereof and a through hole formed through a second surface thereof that is opposite to the first surface to reach the device layer, and an inner portion of a second substrate facing the first surface and bonded to the first surface by a first adhesive layer.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: April 6, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masahiko Murano, Fumito Shoji, Tatsuo Migita, Ippei Kume
  • Patent number: 10943794
    Abstract: A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: March 9, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Owen R. Fay, Akshay N. Singh, Kyle K. Kirby
  • Patent number: 10937680
    Abstract: Among other things a method including releasing a discrete component from an interim handle and depositing a discrete component on a handle substrate, attaching the handle substrate to the discrete component, and removing the handle substrate from the discrete component.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: March 2, 2021
    Assignee: Uniqarta, Inc.
    Inventor: Val Marinov
  • Patent number: 10903121
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a uniform rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: January 26, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, Karthik Balakrishnan, James S. Papanu
  • Patent number: 10888040
    Abstract: The present disclosure relates to a shielded double-sided module, which includes a module substrate with a ground plane, at least one top electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a number of first module contacts attached to a bottom surface of the module substrate, a second mold compound, and a shielding structure. The second mold compound resides over the bottom surface of the module substrate, and each first module contact is exposed through the second mold compound. The shielding structure completely covers a top surface and a side surface of the module, and is electrically coupled to the ground plane within the module substrate.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: January 5, 2021
    Assignee: Qorvo US, Inc.
    Inventors: David Jandzinski, Thomas Scott Morris, Brian Howard Calhoun
  • Patent number: 10856456
    Abstract: The present disclosure relates to a shielded double-sided module, which includes a module substrate with a ground plane, at least one top electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a number of first module contacts attached to a bottom surface of the module substrate, a second mold compound, and a shielding structure. The second mold compound resides over the bottom surface of the module substrate, and each first module contact is exposed through the second mold compound. The shielding structure completely covers a top surface and a side surface of the module, and is electrically coupled to the ground plane within the module substrate.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: December 1, 2020
    Assignee: Qorvo US, Inc.
    Inventors: David Jandzinski, Thomas Scott Morris, Brian Howard Calhoun
  • Patent number: 10847497
    Abstract: A mounting apparatus of a chip including a mechanism configured to arrange a front surface of a chip and a front surface of a substrate to face each other such that a back surface of the chip is attached to a sheet, the sheet having a first portion corresponding to the selected chip and a the second portion arranged at a periphery of the first portion corresponding to the selected chip in the sheet when seen in a direction perpendicular to the front surface of the substrate; a holding mechanism moving in a direction that is not perpendicular to the front surface of the substrate and arranged to hold the second portion of the sheet; and a pushing mechanism for pushing the back surface of the chip through the first portion of the sheet so that the front surface of the chip is brought close to the front surface of the substrate with the first portion deformed in a state where the second portion is held by the holding mechanism, and configured to release the pushing mechanism from the first portion of the sheet t
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: November 24, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoichiro Kurita
  • Patent number: 10825731
    Abstract: Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: November 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Takashi Noma
  • Patent number: 10825704
    Abstract: A chip transferring machine includes a chip carrier, a chip transferring module, and a chip carrier substrate. The chip carrier carries a plurality of chips. The chip transferring module includes at least one conveyor belt having an adhesive surface. The chip carrier substrate carries the plurality of chips. The chip carrier, the chip transferring module, and the chip carrier substrate are disposed on a same production line, and the chip carrier and the chip carrier substrate are disposed under or above the adhesive surface of the conveyor belt.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: November 3, 2020
    Assignee: ASTI GLOBAL INC., TAIWAN
    Inventor: Chien-Shou Liao
  • Patent number: 10784164
    Abstract: A wafer having a device area on one side with a plurality of devices partitioned by division lines is divided into dies. An adhesive tape for protecting devices is attached to the one side of the wafer, the adhesive tape adhering to at least some, optionally all, of the devices. A carrier for supporting the tape is attached to the side of the tape opposite to the one side by an attachment means provided over an entire surface area of the adhesive tape which is in contact with the carrier. The wafer is cut along the division lines. The side of the wafer opposite to the one side is mechanically partially cut, and a remaining part of the cuts in the wafer is mechanically cut and/or cut by laser and/or cut by plasma from the side of the wafer opposite to the one side.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 22, 2020
    Assignee: DISCO CORPORATION
    Inventor: Karl Heinz Priewasser
  • Patent number: 10784161
    Abstract: A method for manufacturing a semiconductor device includes: partially dicing a substrate wafer arrangement having a plurality of semiconductor chips, wherein the partial dicing forms trenches around the semiconductor chips on a front-side of the substrate wafer arrangement, the depth being greater than a target thickness of a semiconductor chip; filling the trenches with a polymer material to form a polymer structure; first thinning of the back-side to expose portions of the polymer structure; forming a conductive layer on the back-side of the substrate wafer arrangement so that the exposed portions of the polymer structure are covered; second thinning of the back-side to form insular islands of conductive material, the insular islands separated from each other by the polymer structure, each insular island corresponding to a respective one of the semiconductor chips; and dicing the substrate wafer arrangement along the polymer structure.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 22, 2020
    Assignee: Infineon Technologies AG
    Inventors: Ingo Muri, Bernhard Goller
  • Patent number: 10748850
    Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 18, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Takashi Noma, Francis J. Carney
  • Patent number: 10748800
    Abstract: A chip bonding device is disclosed, including a first motion stage (110), a second motion stage (200), a chip pickup element (160), a transfer carrier (170), a chip adjustment system (1000), a bonding stage (420) and a control system (500). A chip bonding method is also disclosed, in which a set of chips are temporarily retained on the transfer carrier (170) and their positions on the transfer carrier (170) are accurately adjusted by using the chip adjustment system (1000), followed by bonding the chips on the transfer carrier (170) simultaneously onto the substrate (430). With this batch bonding approach, flip-chips can be bonded with greatly enhanced efficiency. Moreover, picking up and bonding chips in batches can balance times for chip picking up, fine chip position tuning and chip bonding, thereby ensuring high bonding accuracy while increasing the throughput.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 18, 2020
    Assignee: SHANGHAI MICRO ELECTRONICS EQUIPMENT (GROUP) CO., LTD.
    Inventors: Yuebin Zhu, Feibiao Chen, Hai Xia, Bin Yu, Song Guo, Yaping Ge
  • Patent number: 10741504
    Abstract: A semiconductor wafer provided with a pseudo chip between a product chip and a pattern prohibiting region is prepared. With the edge portion of the semiconductor wafer left, the bottom surface of the inner semiconductor substrate is ground, and then, the semiconductor wafer is cut in a ring shape to remove the edge portion. Here, in the pseudo chip, a protective film covering the conductive pattern is formed on the top surface of the semiconductor substrate and the end surface of the protective film facing the pattern prohibiting region is positioned on the conductive pattern. Further, in plan view, the inner peripheral end of the edge portion is positioned in the pattern prohibiting region, and the pattern prohibiting region between the inner peripheral end of the edge portion and the pseudo chip is cut in a ring shape.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: August 11, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takuji Yoshida
  • Patent number: 10675791
    Abstract: A plurality of molded cover members are manufactured by first singulating a single sheet of cover material, such as glass, into a plurality of separate, discrete cover members, placing the cover members in spaced-apart positions on a releaseable carrier, and applying a molded material to the perimeter of each cover member. The molded material can be applied by a blanket molding technique whereby gaps between adjacent cover members are filled, and then the cover members are singulated, leaving a portion of the cover material on the perimeter of each cover member, and then the singulated, molded cover members are released from the releasable carrier. Alternatively, the molded material is applied by a patterned molding technique whereby molding material is applied to the perimeter of each cover member without fully filling the gaps between adjacent cover members, and then the molded cover members are released from the releasable carrier.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: June 9, 2020
    Assignee: IDEX Biometrics ASA
    Inventors: David N. Light, Anne L. McAleer
  • Patent number: 10644190
    Abstract: A fluidic assembly method is provided that uses a counterbore pocket structure. The method is based upon the use of a substrate with a plurality of counterbore pocket structures formed in the top surface, with each counterbore pocket structure having a through-hole to the substrate bottom surface. The method flows an ink with a plurality of objects over the substrate top surface. As noted above, the objects may be micro-objects in the shape of a disk. For example, the substrate may be a transparent substrate and the disks may be light emitting diode (LED) disks. Simultaneously, a suction pressure is created at the substrate bottom surface. In response to the suction pressure from the through-holes, the objects are drawn into the counterbore pocket structures. Also provided is a related fluidic substrate assembly.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: May 5, 2020
    Assignee: eLux Inc.
    Inventors: Changqing Zhan, Paul John Schuele, Mark Albert Crowder, Sean Mathew Garner, Timothy James Kiczenski
  • Patent number: 10615106
    Abstract: The present disclosure relates to a chip package structure and a method for forming a chip package. A package unit is formed from the chip and an encapsulant surrounding the chip to have an increased area. A redistribution layer is formed on the package unit to draw out to and redistribute input/output terminals on a surface of the chip. The redistribution layer is then electrically coupled to a leadframe or a printed circuit board by external and electrical connectors. The method and the package structure are suitable for providing a chip package having input/output terminals with high density, reducing package cost, and improving package reliability.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: April 7, 2020
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventor: Jiaming Ye
  • Patent number: 10600670
    Abstract: An apparatus which comprises an expansion unit configured for expanding a foil, and a mounting unit configured for subsequently mounting the expanded foil on a frame and a workpiece, in particular a wafer, on the expanded foil.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies AG
    Inventor: Thomas Fischer
  • Patent number: 10566257
    Abstract: A method for manufacturing a wiring board includes forming on a first support plate a first laminated wiring portion including conductor and insulating layers such that the first portion has a first surface on first support plate side and a second surface, separating the first portion from the first plate, forming a conductor layer exposed on the first surface and including pads, laminating the first portion on a second support plate such that the second surface of the first portion faces second support plate side, forming on the first surface of the first portion a second laminated wiring portion including conductor and insulating layers such that the second portion has a third surface on second support plate side and a fourth surface, forming cavity in the second portion on the second plate such that the cavity exposes the pads, and separating the first and second portions from the second plate.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 18, 2020
    Assignee: IBIDEN CO., LTD.
    Inventor: Naoki Kurahashi
  • Patent number: 10566268
    Abstract: A package to die connection system and method are provided. The system includes a semiconductor device having a substrate with a top surface. A gasket is affixed to the top surface of the substrate and has at least one cavity with a portion of the cavity open to a sidewall of the gasket. A semiconductor die is attached to the top surface of the substrate. A sidewall of the semiconductor die is abutted with the sidewall of the gasket. A portion of a metal layer is exposed to the open portion of the cavity. A pillar located in the cavity is electrically connected to the exposed portion of the metal layer.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: February 18, 2020
    Assignee: NXP USA, INC.
    Inventors: Mark Douglas Hall, Walter J. Ciosek, David Russell Tipple
  • Patent number: 10559546
    Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin
  • Patent number: 10468255
    Abstract: A processing method for performing laser processing on a wafer includes: a reflected light detecting step of irradiating the wafer with light for state detection along a plurality of planned dividing lines, and detecting reflected light of the light from an upper surface of the wafer; a region setting step of setting a first region and a second region to the planned dividing lines based on the reflected light; a first laser processing step of performing laser processing on the first region under a first laser processing condition; and a second laser processing step of performing laser processing on the second region under a second laser processing condition.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: November 5, 2019
    Assignee: DISCO CORPORATION
    Inventor: Jinyan Zhao
  • Patent number: 10461016
    Abstract: A ceramic module for power semiconductor integrated packaging and a preparation method thereof are disclosed. The ceramic module includes a ceramic substrate and an integrated metal dam layer. By providing the integral metal dam layer on the upper surface of the ceramic substrate and forming cavities around die bonding regions, the semiconductor chip can be hermetically sealed. By providing a heat dissipation layer on the lower surface of the ceramic substrate, the heat generated by the semiconductor chip can be quickly conducted to the outside. The product has a simple production process and high product consistency.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: October 29, 2019
    Assignee: DONGGUAN CHINA ADVANCED CERAMIC TECHNOLOGY CO., LTD.
    Inventors: Zhaohui Wu, Wei Kang, Xiaoquan Guo, Jun Zhang
  • Patent number: 10453795
    Abstract: A ground isolation webbing structure package includes a top level with an upper interconnect layer having upper ground contacts, upper data signal contacts, and a conductive material upper ground webbing structure that is connected to the upper ground contacts and surrounds the upper data signal contacts. The upper contacts may be formed over and connected to via contacts or traces of a lower layer of the same interconnect level. The via contacts of the lower layer may be connected to upper contacts of a second interconnect level which may also have such webbing. There may also be at least a third interconnect level having such webbing. The webbing structure electrically isolates and reduces cross talk between the signal contacts, thus providing higher frequency and more accurate data signal transfer between devices such as integrated circuit (IC) chips attached to a package.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Yu Amos Zhang, Mathew J. Manusharow, Kemal Aygun, Mohiuddin Mazumder