Substrate Dicing Patents (Class 438/113)
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Patent number: 12103200Abstract: An acoustic cleaving system are described for initiating and controlling crack propagation. In an embodiment, the system includes an acoustic generator that includes a piezoelectric device; a high-voltage power supply; and an acoustic cleaving circuit. The acoustic cleaving circuit includes a push-pull circuit coupled to the piezoelectric device and coupled to the high-voltage power supply, and a capacitor bank that includes one or more capacitors coupled in parallel to the push-pull circuit. In one embodiment, the push-pull circuit is for receiving at least one input signal and for producing an amplified output signal to drive the piezoelectric device.Type: GrantFiled: March 19, 2024Date of Patent: October 1, 2024Assignee: Crystal Sonic, Inc.Inventors: Mariana Bertoni, Pablo Guimerá Coll, Arno Merkle, Jon Williams
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Patent number: 12062643Abstract: A method for manufacturing an electronic device including the following steps: a) forming a wafer of electronic chips; b) fixing the wafer of electronic chips to a first support made of a stretchable material; c) removing and/or etching the wafer; and d) stretching the first support so as to move the chips away from one another.Type: GrantFiled: October 8, 2019Date of Patent: August 13, 2024Assignee: AlediaInventors: Ivan-Christophe Robin, Zine Bouhamri, Philippe Gilet
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Patent number: 11867754Abstract: A system, comprising: (i) an interposer layer; (ii) a circuit layer positioned on the interposer layer and comprising a plurality of sonically-enabled pads; and (iii) an interrogator layer positioned on the circuit layer and comprising a plurality of ultrasonic transducers configured to sonically interrogate the circuit layer; wherein the sonically-enabled pads are configured to generate an electrical signal in response to sonic interrogation from the interrogator layer, if the sonically-enabled pad is functional.Type: GrantFiled: July 17, 2018Date of Patent: January 9, 2024Assignee: Cornell UniversityInventors: Amit Lal, Christopher Batten
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Patent number: 11807712Abstract: Disclosed is a hydrogenated norbornene ring-opened polymer, wherein a proportion of a norbornene-derived repeating unit is 90% by mass or more, a meso diad fraction of the norbornene-derived repeating unit is 80% or more, and in an X-ray diffraction pattern measured at 25° C. using a CuK? radiation source, an X-ray diffraction peak is observed which has a peak top positioned in a diffraction angle (2?) range of 17° or more and 18° or less.Type: GrantFiled: March 20, 2019Date of Patent: November 7, 2023Assignee: ZEON CORPORATIONInventors: Yuki Nakama, Shigetaka Hayano
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Patent number: 11707804Abstract: A mask-integrated surface protective tape, containing: a substrate film; a temporary-adhesive layer provided on the substrate film; and a mask material layer provided on the temporary-adhesive layer; wherein the mask material layer and the temporary-adhesive layer each contain a (meth)acrylic copolymer; and wherein the mask-integrated surface protective tape is used for a method of producing a semiconductor chip utilizing a plasma-dicing.Type: GrantFiled: January 11, 2018Date of Patent: July 25, 2023Assignee: FURUKAWA ELECTRIC CO., LTD.Inventors: Hirotoki Yokoi, Tomoaki Uchiyama, Yoshifumi Oka
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Patent number: 11631647Abstract: In one embodiment, an integrated device package is disclosed. The integrated device package can comprise a carrier an a molding compound over a portion of an upper surface of the carrier. The integrated device package can comprise an integrated device die mounted to the carrier and at least partially embedded in the molding compound, the integrated device die comprising active circuitry. The integrated device package can comprise a stress compensation element mounted to the carrier and at least partially embedded in the molding compound, the stress compensation element spaced apart from the integrated device die, the stress compensation element comprising a dummy stress compensation element devoid of active circuitry. At least one of the stress compensation element and the integrated device die can be directly bonded to the carrier without an adhesive.Type: GrantFiled: June 30, 2020Date of Patent: April 18, 2023Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventor: Belgacem Haba
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Patent number: 11557548Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame.Type: GrantFiled: December 29, 2020Date of Patent: January 17, 2023Assignee: STMicroelectronics, Inc.Inventors: Aaron Cadag, Lester Joseph Belalo, Ela Mia Cadag
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Patent number: 11502228Abstract: A method of producing an optoelectronic semiconductor device includes providing a frame part including a plurality of openings, providing an auxiliary carrier, connecting the auxiliary carrier to the frame part such that the auxiliary carrier covers at least some of the openings at an underside of the frame part, placing conversion elements onto the auxiliary carrier in at least some of the openings, placing optoelectronic semiconductor chips onto the conversion elements in at least some of the openings, applying a housing onto the conversion elements and around the semiconductor chips in at least some of the openings, and removing the frame part and the auxiliary carrier wherein a bottom surface of at least some of the optoelectronic semiconductor chips remains free of the housing.Type: GrantFiled: August 4, 2017Date of Patent: November 15, 2022Assignee: OSRAM Opto Semiconductors GmbHInventors: Seng-Teong Chang, Choon Keat Or, Lee-Ying Jacqueline Ng, Chai-Yun Jade Looi
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Patent number: 11456188Abstract: A flexible semiconductor device includes a first tape having bonding pads and conductive traces formed. A semiconductor die having a bottom surface is attached to the first tape and electrically connected to the bond pads by way of electrical contacts. A second tape is attached to a top surface of the semiconductor die. The first and second tapes encapsulate the semiconductor die, the electrical contacts, and at least a part of the conductive traces.Type: GrantFiled: May 14, 2020Date of Patent: September 27, 2022Assignee: NXP USA, INC.Inventors: You Ge, Meng Kong Lye, Zhijie Wang
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Patent number: 11456215Abstract: A manufacturing method includes the step of laminating a sheet assembly onto chips arranged on a processing tape, where the sheet assembly has a multilayer structure including a base and a sinter-bonding sheet and is laminated so that the sinter-bonding sheet faces the chips, and subsequently removing the base B from the sinter-bonding sheet. The chips on the processing tape are picked up each with a portion of the sinter-bonding sheet adhering to the chip, to give sinter-bonding material layer-associated chips. The sinter-bonding material layer-associated chips are temporarily secured through the sinter-bonding material layer to a substrate. The sinter-bonding material layers lying between the temporarily secured chips and the substrate are converted through a heating process into sintered layers, to bond the chips to the substrate.Type: GrantFiled: March 27, 2019Date of Patent: September 27, 2022Assignee: NITTO DENKO CORPORATIONInventors: Ryota Mita, Tomoaki Ichikawa
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Patent number: 11361878Abstract: The present invention relates to a method for manufacturing an insulating layer which can minimize the degree of warpage caused by polymer shrinkage at the time of curing and secure the stability of a semiconductor chip located therein, and a method for manufacturing a semiconductor package using an insulating layer obtained from the manufacturing method of the insulating layer.Type: GrantFiled: July 2, 2018Date of Patent: June 14, 2022Assignee: LG CHEM, LTD.Inventors: Woo Jae Jeong, You Jin Kyung, Byung Ju Choi, Bo Yun Choi, Kwang Joo Lee, Min Su Jeong
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Patent number: 11355365Abstract: Introduced is a micro-chip gripper comprising: a pin plate of which one surface is coupled to another apparatus; a hole plate of which one surface faces the other surface of the pin plate while being disposed to be spaced apart therefrom by a fixed distance, and which is driven together with the drive of the pin plate, and in which a plurality of holes making a fixed pattern are formed; pins which are inserted into the holes of the hole plate and of which one end part is supported by the pin plate; and an adhesion layer which covers the other surface of the hole plate. Other embodiments are possible.Type: GrantFiled: December 3, 2018Date of Patent: June 7, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Changjoon Lee, Byunghoon Lee, Min Park, Kyungwoon Jang, Jeonggen Yoon, Hyuntae Jang
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Patent number: 11342426Abstract: A semiconductor device includes a semiconductor part, first and second electrodes. The semiconductor part is provided between the first and second electrodes. A method of manufacturing the device includes forming the first electrode covering a back surface of a wafer after the second electrode is formed on a front surface of the wafer; forming a first groove by selectively removing the first electrode; and dividing the wafer by forming a second groove at the front surface side. The wafer includes a region to be the semiconductor part; and the first and second grooves are provided along a periphery of the region. The first groove is in communication with the first groove. The second groove has a width in a direction along the front surface of the wafer, the width of the first groove being narrower than a width of the first groove in the same direction.Type: GrantFiled: February 27, 2020Date of Patent: May 24, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Shinji Nunotani, Shinji Onzuka
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Patent number: 11329021Abstract: A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.Type: GrantFiled: November 15, 2019Date of Patent: May 10, 2022Assignee: Infineon Technologies AGInventors: Francisco Javier Santos Rodriguez, Fabian Craes, Barbara Eichinger, Martin Mischitz, Frederik Otto, Fabien Thion
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Patent number: 11315804Abstract: A manufacturing method of a mounting structure, the method including a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member; a disposing step of disposing a thermosetting sheet and a thermoplastic sheet on the mounting member, with the thermosetting sheet interposed between the thermoplastic sheet and the first circuit member; a first sealing step of pressing a stack of the thermosetting sheet and the thermoplastic sheet against the first circuit member, and heating the stack, to seal the second circuit members and to cure the thermosetting sheet into a first cured layer; a removal step of removing the thermoplastic sheet from the first cured layer; and a coating film formation step of forming a coating film on the first cured layer, after the removal step.Type: GrantFiled: December 13, 2018Date of Patent: April 26, 2022Assignee: NAGASE CHEMTEX CORPORATIONInventors: Eiichi Nomura, Yutaka Miyamoto, Takayuki Hashimoto
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Pattern part, method for forming pattern part and method for manufacturing display device using same
Patent number: 11276737Abstract: A method of forming a pattern part includes forming a first film on a target object, the first film having a first cure shrinkage ratio, forming a second film on the first film, the second film having a second cure shrinkage ratio greater than the first cure shrinkage ratio, and patterning the first film and the second film to form a pattern.Type: GrantFiled: October 24, 2019Date of Patent: March 15, 2022Assignee: Samsung Display Co., Ltd.Inventors: Seungcheol Ko, Junho Sim, Seyoon Oh -
Patent number: 11270897Abstract: An apparatus and associated method for high speed and/or mass transfer of electronic components onto a substrate comprises transferring, using an ejector assembly, electronics components (e.g., light emitting devices) from a die sheet onto an adhesive receiving structure to form a predefined pattern including electronic components thereon, and then transferring the electronic components defining the predefined pattern onto a substrate (e.g., a translucent superstrate) for light emission therethrough to create a high-density (e.g., high resolution) display device utilizing, for example, mini- or micro-LED display technologies.Type: GrantFiled: February 20, 2020Date of Patent: March 8, 2022Assignee: CREELED, INC.Inventors: Christopher P. Hussell, Peter Scott Andrews
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Patent number: 11260646Abstract: A method of processing a substrate, with a first major surface of the substrate removably bonded to a first major surface of a first carrier and a second major surface of the substrate removably bonded to a first major surface of a second carrier, includes initiating debonding at a first location of an outer peripheral bonded interface between the substrate and the first carrier to separate a portion of the first carrier from the substrate. The method further includes propagating a first debond front from the first debonded location along a first direction extending away from the first debonded location by sequentially applying a plurality of lifting forces to the first carrier at a corresponding plurality of sequential lifting locations of the first carrier.Type: GrantFiled: November 13, 2017Date of Patent: March 1, 2022Assignee: CORNING INCORPORATEDInventors: Christina Sue Bennett, Raymond Charles Cady, Hyun-Soo Choi, Claire Renata Coble, Byungchul Kim, Timothy Michael Miller, Joseph William Soper, Gary Carl Weber
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Patent number: 11244923Abstract: A semiconductor device and a method of manufacturing a semiconductor device. For example, various aspects of this disclosure provide a semiconductor device having an ultra-thin substrate, and a method of manufacturing a semiconductor device having an ultra-thin substrate. As a non-limiting example, a substrate structure comprising a carrier, an adhesive layer formed on the carrier, and an ultra-thin substrate formed on the adhesive layer may be received and/or formed, components may then be mounted to the ultra-thin substrate and encapsulated, and the carrier and adhesive layer may then be removed.Type: GrantFiled: December 9, 2019Date of Patent: February 8, 2022Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventor: Ronald Huemoeller
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Patent number: 11244862Abstract: A method for manufacturing semiconductor devices includes: forming a plurality of semiconductor devices in a first region of a primary surface of a wafer; forming a plurality of cleave initiation portions in a second region of a primary surface different from the first region; and cleaving the wafer sequentially, using the plurality of cleave initiation portions as initiation points, starting from a cleave initiation portion that is relatively difficult to cleave among the plurality of cleave initiation portions. Forming the plurality of cleave initiation portions includes forming the plurality of first grooves by etching portions of the second region. Due to this, the yield and the manufacturing efficiency for semiconductor devices can be enhanced.Type: GrantFiled: April 10, 2018Date of Patent: February 8, 2022Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Kenji Yoshikawa, Masato Negishi, Masato Suzuki, Tatsuro Yoshino
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Patent number: 11195769Abstract: A thermosetting composition for use as an underfill material contains: a mono- or bifunctional acrylic compound; a thermo-radical polymerization initiator; silica; and an elastomer including a 1,2-vinyl group. The thermosetting composition is liquid and has a property of turning, when cured thermally, into a cured product having a relative dielectric constant of 3.2 or less at 25° C. and a dielectric loss tangent of 0.013 or less at 25° C.Type: GrantFiled: February 27, 2018Date of Patent: December 7, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shigeru Yamatsu, Naoki Kanagawa
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Patent number: 11189609Abstract: Methods for reducing heat transfer in semiconductor devices, and associated systems and devices, are described herein. In some embodiments, a method of manufacturing a semiconductor device includes forming a channel in a region of a substrate between a first die stack and a second die stack. The first die stack includes a plurality of first dies attached to each other by first film layers and the second die stack includes a plurality of second dies attached to each other by second film layers. The channel extends entirely through a thickness of the substrate. The method also includes applying heat to the first die stack to cure the first film layers. The channel reduces heat transfer from the first die stack to the second die stack.Type: GrantFiled: May 1, 2020Date of Patent: November 30, 2021Assignee: Micron Technology, Inc.Inventors: Brandon P. Wirz, Andrew M. Bayless
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Patent number: 11152322Abstract: In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D1 according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D2 according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D1 is shallower than a height H of the metal strip, and the depth D2 is also shallower than the height H. Other embodiments are presented.Type: GrantFiled: October 3, 2018Date of Patent: October 19, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Sreenivasan K. Koduri
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Patent number: 11136479Abstract: The electrically conductive adhesive film comprises a metal particle (P), a resin (M) and a prescribed sulfide compound (A), the resin (M) comprises a thermosetting resin (M1), and the metal particle (P) has an average particle size (d50) of 20 ?m or less and comprises 10% by mass or more of a first metal particle (P1) having a fractal dimension of 1.1 or more when viewed in a projection drawing in a primary particle state.Type: GrantFiled: August 7, 2018Date of Patent: October 5, 2021Assignee: Furukawa Electric Co., Ltd.Inventors: Naoaki Mihara, Noriyuki Kirikae, Jirou Sugiyama
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Patent number: 11137559Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.Type: GrantFiled: April 17, 2020Date of Patent: October 5, 2021Assignee: XINTEC INC.Inventors: Jiun-Yen Lai, Yu-Ting Huang, Hsing-Lung Shen, Tsang-Yu Liu, Hui-Hsien Wu
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Patent number: 11114630Abstract: A display panel is provided, including a substrate on a base, a transistor stack on the substrate, and a fluorescent layer between the base and the transistor stack. The fluorescent layer is configured to prevent light from damaging an active layer in the transistor stack in a laser lift-off process, and an orthographic projection of the fluorescent layer on the base overlaps an orthographic projection of the active layer on the base. A display device comprising the display panel, and a manufacturing method of the display panel are further provided.Type: GrantFiled: October 10, 2019Date of Patent: September 7, 2021Assignee: BOE Technology Group Co., Ltd.Inventors: Shipei Li, Qi Yao, Wusheng Li, Jiangnan Lu, Huili Wu, Fang He, Renquan Gu, Dongsheng Yin, Sheng Xu, Wei He
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Patent number: 11114408Abstract: Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.Type: GrantFiled: November 18, 2019Date of Patent: September 7, 2021Assignee: Invensas CorporationInventors: Hong Shen, Liang Wang, Guilian Gao
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Patent number: 11098226Abstract: The electrically conductive adhesive film comprises a metal particle (P), a resin (M) and a prescribed sulfide compound (A), the resin (M) comprises a thermosetting resin (M1), and the metal particle (P) has an average particle size (d50) of 20 ?m or less and comprises 10% by mass or more of a first metal particle (P1) having a fractal dimension of 1.1 or more when viewed in a projection drawing in a primary particle state.Type: GrantFiled: August 7, 2018Date of Patent: August 24, 2021Assignee: Furukawa Electric Co., Ltd.Inventors: Naoaki Mihara, Noriyuki Kirikae, Jirou Sugiyama
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Patent number: 11088041Abstract: Semiconductor packages are disclosed. A semiconductor package includes an integrated circuit, a first die and a second die. The first die includes a first bonding structure and a first seal ring. The first bonding structure is bonded to the integrated circuit and disposed at a first side of the first die. The second die includes a second bonding structure. The second bonding structure is bonded to the integrated circuit and disposed at a first side of the second die. The first side of the first die faces the first side of the second die. A first portion of the first seal ring is disposed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring.Type: GrantFiled: September 17, 2019Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Chih-Chia Hu
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Patent number: 11075071Abstract: To provide a wafer processing method which can simplify the wafer processing process and efficiently obtain chips of stable quality. A wafer processing method includes: a tape attaching step of attaching a back grinding tape to the front surface of a wafer; a modified region forming step of applying a laser beam from the back surface of the wafer along a cut line to form modified regions inside the wafer; a back surface processing step of processing the back surface of the wafer having the modified regions to reduce a thickness of the wafer; and a dividing step of, in a state in which the back grinding tape is attached to the front surface of the wafer, applying a load to the cut line from the back surface of the wafer to divide the wafer along the cut line and obtain individual chips.Type: GrantFiled: May 5, 2020Date of Patent: July 27, 2021Assignee: TOKYO SEIMITSU CO., LTD.Inventors: Ryosuke Kataoka, Takashi Tamogami, Syuhei Oshida
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Patent number: 11037883Abstract: Techniques are provided for containing magnetic fields generated by an integrated switching package and for reducing electromagnetic interference generated from an integrated switching package.Type: GrantFiled: November 16, 2018Date of Patent: June 15, 2021Assignee: Analog Devices International Unlimited CompanyInventors: Leonard Shtargot, Zafer Kutlu, John Underhill Gardner
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Patent number: 11031276Abstract: A wafer expanding method for expanding a wafer having a plurality of rectangular devices respectively formed in a plurality of separate regions defined by a plurality of division lines, thereby increasing spacing between any adjacent ones of the devices, each rectangular device having a pair of shorter sides and a pair of longer sides. The wafer expanding method includes a jig preparing step of preparing an annular jig having an elliptical opening, the elliptical opening having a shorter portion for restricting a width of the annular exposed portion in a first direction where the shorter sides of the devices extend to a first width and a longer portion for restricting the width of the annular exposed portion in a second direction where the longer sides of the devices extend to a second width larger than the first width.Type: GrantFiled: October 29, 2019Date of Patent: June 8, 2021Assignee: DISCO CORPORATIONInventors: Yoshihiro Kawaguchi, Masaru Nakamura
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Patent number: 11024220Abstract: Apparatus and method relating generally to an LED display is disclosed. In such an apparatus, a driver die has a plurality of driver circuits. A plurality of light-emitting diodes, each having a thickness of 10 microns or less and discrete with respect to one another, are respectively interconnected to the plurality of driver circuits. The plurality of light-emitting diodes includes a first portion for a first color, a second portion for a second color, and a third portion for a third color respectively obtained from a first, a second, and a third optical wafer. The first, the second, and the third color are different from one another.Type: GrantFiled: May 31, 2018Date of Patent: June 1, 2021Assignee: Invensas CorporationInventors: Liang Wang, Rajesh Katkar, Javier A. Delacruz, Ilyas Mohammed, Belgacem Haba
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Patent number: 11018044Abstract: A wafer expanding method increases spacing between adjacent devices formed on a wafer. The method includes preparing an annular jig having a first restricting portion, a second restricting portion, and a curved restricting portion connecting the first restricting portion and the second restricting portion, mounting a ring frame supporting the wafer through an adhesive tape on a cylindrical frame fixing member, next mounting the annular jig on the ring frame, and next fixing the ring frame and the annular jig to the cylindrical frame fixing member, and operating a cylindrical pushing member having an outer circumference corresponding to an outer circumference of the wafer to push up an annular exposed portion of the adhesive tape defined between the wafer and the ring frame and thereby lift the wafer away from the ring frame, thereby expanding the annular exposed portion and increasing the spacing between the adjacent devices.Type: GrantFiled: October 25, 2019Date of Patent: May 25, 2021Assignee: DISCO CORPORATIONInventors: Masaru Nakamura, Saki Kozuma
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Patent number: 11004759Abstract: An electronic component includes a resin structure including first and second surfaces facing each other, an electronic component element contained in the resin structure, including first and second main surfaces facing each other, and side surfaces connecting the first and second main surfaces, and being exposed to the first surface of the resin structure, and a through-electrode penetrating the resin structure to connect the first and second surfaces of the resin structure, in which the through-electrode are in contact with at least one of the side surfaces of the electronic component element.Type: GrantFiled: May 15, 2019Date of Patent: May 11, 2021Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Hiroshi Somada
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Patent number: 10978607Abstract: A device includes a substrate and an optoelectronic chip buried in the substrate. The substrate may include an opening above a first optical transduction region of the first optoelectronic chip and above a second optical transduction region of a second optoelectronic chip.Type: GrantFiled: May 10, 2019Date of Patent: April 13, 2021Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Alexandre Coullomb, Romain Coffy, Jean-Michel Riviere
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Patent number: 10971400Abstract: A semiconductor device includes a device layer having a semiconductor element and a wiring layer, a first structure, a second structure at an outer periphery of the first structure and having a thickness smaller than that of the first structure, and a conductive layer that covers the first structure and the second structure. The first structure comprises a first substrate having the device layer formed on a first surface thereof and a through hole formed through a second surface thereof that is opposite to the first surface to reach the device layer, and an inner portion of a second substrate facing the first surface and bonded to the first surface by a first adhesive layer.Type: GrantFiled: September 2, 2019Date of Patent: April 6, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masahiko Murano, Fumito Shoji, Tatsuo Migita, Ippei Kume
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Patent number: 10943794Abstract: A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.Type: GrantFiled: July 16, 2019Date of Patent: March 9, 2021Assignee: MICRON TECHNOLOGY, INC.Inventors: Owen R. Fay, Akshay N. Singh, Kyle K. Kirby
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Patent number: 10937680Abstract: Among other things a method including releasing a discrete component from an interim handle and depositing a discrete component on a handle substrate, attaching the handle substrate to the discrete component, and removing the handle substrate from the discrete component.Type: GrantFiled: December 24, 2019Date of Patent: March 2, 2021Assignee: Uniqarta, Inc.Inventor: Val Marinov
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Patent number: 10903121Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a uniform rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.Type: GrantFiled: August 14, 2019Date of Patent: January 26, 2021Assignee: Applied Materials, Inc.Inventors: Jungrae Park, Karthik Balakrishnan, James S. Papanu
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Patent number: 10888040Abstract: The present disclosure relates to a shielded double-sided module, which includes a module substrate with a ground plane, at least one top electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a number of first module contacts attached to a bottom surface of the module substrate, a second mold compound, and a shielding structure. The second mold compound resides over the bottom surface of the module substrate, and each first module contact is exposed through the second mold compound. The shielding structure completely covers a top surface and a side surface of the module, and is electrically coupled to the ground plane within the module substrate.Type: GrantFiled: August 28, 2018Date of Patent: January 5, 2021Assignee: Qorvo US, Inc.Inventors: David Jandzinski, Thomas Scott Morris, Brian Howard Calhoun
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Patent number: 10856456Abstract: The present disclosure relates to a shielded double-sided module, which includes a module substrate with a ground plane, at least one top electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a number of first module contacts attached to a bottom surface of the module substrate, a second mold compound, and a shielding structure. The second mold compound resides over the bottom surface of the module substrate, and each first module contact is exposed through the second mold compound. The shielding structure completely covers a top surface and a side surface of the module, and is electrically coupled to the ground plane within the module substrate.Type: GrantFiled: August 28, 2018Date of Patent: December 1, 2020Assignee: Qorvo US, Inc.Inventors: David Jandzinski, Thomas Scott Morris, Brian Howard Calhoun
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Patent number: 10847497Abstract: A mounting apparatus of a chip including a mechanism configured to arrange a front surface of a chip and a front surface of a substrate to face each other such that a back surface of the chip is attached to a sheet, the sheet having a first portion corresponding to the selected chip and a the second portion arranged at a periphery of the first portion corresponding to the selected chip in the sheet when seen in a direction perpendicular to the front surface of the substrate; a holding mechanism moving in a direction that is not perpendicular to the front surface of the substrate and arranged to hold the second portion of the sheet; and a pushing mechanism for pushing the back surface of the chip through the first portion of the sheet so that the front surface of the chip is brought close to the front surface of the substrate with the first portion deformed in a state where the second portion is held by the holding mechanism, and configured to release the pushing mechanism from the first portion of the sheet tType: GrantFiled: July 7, 2017Date of Patent: November 24, 2020Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Yoichiro Kurita
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Patent number: 10825731Abstract: Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.Type: GrantFiled: July 9, 2019Date of Patent: November 3, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Takashi Noma
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Patent number: 10825704Abstract: A chip transferring machine includes a chip carrier, a chip transferring module, and a chip carrier substrate. The chip carrier carries a plurality of chips. The chip transferring module includes at least one conveyor belt having an adhesive surface. The chip carrier substrate carries the plurality of chips. The chip carrier, the chip transferring module, and the chip carrier substrate are disposed on a same production line, and the chip carrier and the chip carrier substrate are disposed under or above the adhesive surface of the conveyor belt.Type: GrantFiled: October 11, 2019Date of Patent: November 3, 2020Assignee: ASTI GLOBAL INC., TAIWANInventor: Chien-Shou Liao
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Semiconductor chip including self-aligned, back-side conductive layer and method for making the same
Patent number: 10784161Abstract: A method for manufacturing a semiconductor device includes: partially dicing a substrate wafer arrangement having a plurality of semiconductor chips, wherein the partial dicing forms trenches around the semiconductor chips on a front-side of the substrate wafer arrangement, the depth being greater than a target thickness of a semiconductor chip; filling the trenches with a polymer material to form a polymer structure; first thinning of the back-side to expose portions of the polymer structure; forming a conductive layer on the back-side of the substrate wafer arrangement so that the exposed portions of the polymer structure are covered; second thinning of the back-side to form insular islands of conductive material, the insular islands separated from each other by the polymer structure, each insular island corresponding to a respective one of the semiconductor chips; and dicing the substrate wafer arrangement along the polymer structure.Type: GrantFiled: September 27, 2018Date of Patent: September 22, 2020Assignee: Infineon Technologies AGInventors: Ingo Muri, Bernhard Goller -
Patent number: 10784164Abstract: A wafer having a device area on one side with a plurality of devices partitioned by division lines is divided into dies. An adhesive tape for protecting devices is attached to the one side of the wafer, the adhesive tape adhering to at least some, optionally all, of the devices. A carrier for supporting the tape is attached to the side of the tape opposite to the one side by an attachment means provided over an entire surface area of the adhesive tape which is in contact with the carrier. The wafer is cut along the division lines. The side of the wafer opposite to the one side is mechanically partially cut, and a remaining part of the cuts in the wafer is mechanically cut and/or cut by laser and/or cut by plasma from the side of the wafer opposite to the one side.Type: GrantFiled: March 8, 2016Date of Patent: September 22, 2020Assignee: DISCO CORPORATIONInventor: Karl Heinz Priewasser
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Patent number: 10748800Abstract: A chip bonding device is disclosed, including a first motion stage (110), a second motion stage (200), a chip pickup element (160), a transfer carrier (170), a chip adjustment system (1000), a bonding stage (420) and a control system (500). A chip bonding method is also disclosed, in which a set of chips are temporarily retained on the transfer carrier (170) and their positions on the transfer carrier (170) are accurately adjusted by using the chip adjustment system (1000), followed by bonding the chips on the transfer carrier (170) simultaneously onto the substrate (430). With this batch bonding approach, flip-chips can be bonded with greatly enhanced efficiency. Moreover, picking up and bonding chips in batches can balance times for chip picking up, fine chip position tuning and chip bonding, thereby ensuring high bonding accuracy while increasing the throughput.Type: GrantFiled: February 27, 2017Date of Patent: August 18, 2020Assignee: SHANGHAI MICRO ELECTRONICS EQUIPMENT (GROUP) CO., LTD.Inventors: Yuebin Zhu, Feibiao Chen, Hai Xia, Bin Yu, Song Guo, Yaping Ge
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Patent number: 10748850Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.Type: GrantFiled: March 15, 2018Date of Patent: August 18, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Takashi Noma, Francis J. Carney
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Patent number: 10741504Abstract: A semiconductor wafer provided with a pseudo chip between a product chip and a pattern prohibiting region is prepared. With the edge portion of the semiconductor wafer left, the bottom surface of the inner semiconductor substrate is ground, and then, the semiconductor wafer is cut in a ring shape to remove the edge portion. Here, in the pseudo chip, a protective film covering the conductive pattern is formed on the top surface of the semiconductor substrate and the end surface of the protective film facing the pattern prohibiting region is positioned on the conductive pattern. Further, in plan view, the inner peripheral end of the edge portion is positioned in the pattern prohibiting region, and the pattern prohibiting region between the inner peripheral end of the edge portion and the pseudo chip is cut in a ring shape.Type: GrantFiled: December 6, 2017Date of Patent: August 11, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Takuji Yoshida