Substrate Dicing Patents (Class 438/113)
  • Patent number: 10675791
    Abstract: A plurality of molded cover members are manufactured by first singulating a single sheet of cover material, such as glass, into a plurality of separate, discrete cover members, placing the cover members in spaced-apart positions on a releaseable carrier, and applying a molded material to the perimeter of each cover member. The molded material can be applied by a blanket molding technique whereby gaps between adjacent cover members are filled, and then the cover members are singulated, leaving a portion of the cover material on the perimeter of each cover member, and then the singulated, molded cover members are released from the releasable carrier. Alternatively, the molded material is applied by a patterned molding technique whereby molding material is applied to the perimeter of each cover member without fully filling the gaps between adjacent cover members, and then the molded cover members are released from the releasable carrier.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: June 9, 2020
    Assignee: IDEX Biometrics ASA
    Inventors: David N. Light, Anne L. McAleer
  • Patent number: 10644190
    Abstract: A fluidic assembly method is provided that uses a counterbore pocket structure. The method is based upon the use of a substrate with a plurality of counterbore pocket structures formed in the top surface, with each counterbore pocket structure having a through-hole to the substrate bottom surface. The method flows an ink with a plurality of objects over the substrate top surface. As noted above, the objects may be micro-objects in the shape of a disk. For example, the substrate may be a transparent substrate and the disks may be light emitting diode (LED) disks. Simultaneously, a suction pressure is created at the substrate bottom surface. In response to the suction pressure from the through-holes, the objects are drawn into the counterbore pocket structures. Also provided is a related fluidic substrate assembly.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: May 5, 2020
    Assignee: eLux Inc.
    Inventors: Changqing Zhan, Paul John Schuele, Mark Albert Crowder, Sean Mathew Garner, Timothy James Kiczenski
  • Patent number: 10615106
    Abstract: The present disclosure relates to a chip package structure and a method for forming a chip package. A package unit is formed from the chip and an encapsulant surrounding the chip to have an increased area. A redistribution layer is formed on the package unit to draw out to and redistribute input/output terminals on a surface of the chip. The redistribution layer is then electrically coupled to a leadframe or a printed circuit board by external and electrical connectors. The method and the package structure are suitable for providing a chip package having input/output terminals with high density, reducing package cost, and improving package reliability.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: April 7, 2020
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventor: Jiaming Ye
  • Patent number: 10600670
    Abstract: An apparatus which comprises an expansion unit configured for expanding a foil, and a mounting unit configured for subsequently mounting the expanded foil on a frame and a workpiece, in particular a wafer, on the expanded foil.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies AG
    Inventor: Thomas Fischer
  • Patent number: 10566257
    Abstract: A method for manufacturing a wiring board includes forming on a first support plate a first laminated wiring portion including conductor and insulating layers such that the first portion has a first surface on first support plate side and a second surface, separating the first portion from the first plate, forming a conductor layer exposed on the first surface and including pads, laminating the first portion on a second support plate such that the second surface of the first portion faces second support plate side, forming on the first surface of the first portion a second laminated wiring portion including conductor and insulating layers such that the second portion has a third surface on second support plate side and a fourth surface, forming cavity in the second portion on the second plate such that the cavity exposes the pads, and separating the first and second portions from the second plate.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 18, 2020
    Assignee: IBIDEN CO., LTD.
    Inventor: Naoki Kurahashi
  • Patent number: 10566268
    Abstract: A package to die connection system and method are provided. The system includes a semiconductor device having a substrate with a top surface. A gasket is affixed to the top surface of the substrate and has at least one cavity with a portion of the cavity open to a sidewall of the gasket. A semiconductor die is attached to the top surface of the substrate. A sidewall of the semiconductor die is abutted with the sidewall of the gasket. A portion of a metal layer is exposed to the open portion of the cavity. A pillar located in the cavity is electrically connected to the exposed portion of the metal layer.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: February 18, 2020
    Assignee: NXP USA, INC.
    Inventors: Mark Douglas Hall, Walter J. Ciosek, David Russell Tipple
  • Patent number: 10559546
    Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin
  • Patent number: 10468255
    Abstract: A processing method for performing laser processing on a wafer includes: a reflected light detecting step of irradiating the wafer with light for state detection along a plurality of planned dividing lines, and detecting reflected light of the light from an upper surface of the wafer; a region setting step of setting a first region and a second region to the planned dividing lines based on the reflected light; a first laser processing step of performing laser processing on the first region under a first laser processing condition; and a second laser processing step of performing laser processing on the second region under a second laser processing condition.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: November 5, 2019
    Assignee: DISCO CORPORATION
    Inventor: Jinyan Zhao
  • Patent number: 10461016
    Abstract: A ceramic module for power semiconductor integrated packaging and a preparation method thereof are disclosed. The ceramic module includes a ceramic substrate and an integrated metal dam layer. By providing the integral metal dam layer on the upper surface of the ceramic substrate and forming cavities around die bonding regions, the semiconductor chip can be hermetically sealed. By providing a heat dissipation layer on the lower surface of the ceramic substrate, the heat generated by the semiconductor chip can be quickly conducted to the outside. The product has a simple production process and high product consistency.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: October 29, 2019
    Assignee: DONGGUAN CHINA ADVANCED CERAMIC TECHNOLOGY CO., LTD.
    Inventors: Zhaohui Wu, Wei Kang, Xiaoquan Guo, Jun Zhang
  • Patent number: 10453795
    Abstract: A ground isolation webbing structure package includes a top level with an upper interconnect layer having upper ground contacts, upper data signal contacts, and a conductive material upper ground webbing structure that is connected to the upper ground contacts and surrounds the upper data signal contacts. The upper contacts may be formed over and connected to via contacts or traces of a lower layer of the same interconnect level. The via contacts of the lower layer may be connected to upper contacts of a second interconnect level which may also have such webbing. There may also be at least a third interconnect level having such webbing. The webbing structure electrically isolates and reduces cross talk between the signal contacts, thus providing higher frequency and more accurate data signal transfer between devices such as integrated circuit (IC) chips attached to a package.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Yu Amos Zhang, Mathew J. Manusharow, Kemal Aygun, Mohiuddin Mazumder
  • Patent number: 10424511
    Abstract: A method of processing a plate-shaped workpiece that includes on a face side thereof layered bodies containing metal which are formed in superposed relation to projected dicing lines includes the steps of holding a face side of the workpiece on a holding table, thereafter, applying a laser beam having a wavelength that is absorbable by the workpiece to a reverse side thereof along the projected dicing lines to form laser-processed grooves in the workpiece which terminate short of the layered bodies, and thereafter, cutting bottoms of the laser-processed grooves with a cutting blade to sever the workpiece together with the layered bodies along the projected dicing lines. The step of cutting bottoms of the laser-processed grooves includes the step of cutting bottoms of the laser-processed grooves while supplying a cutting fluid containing an organic acid and an oxidizing agent to the workpiece.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 24, 2019
    Assignee: DISCO CORPORATION
    Inventor: Kenji Takenouchi
  • Patent number: 10418342
    Abstract: A method to fabricate a reconstructed panel based fan-out wafer level package is described. A reconstructed wafer panel is provided comprising a plurality of individual dies encapsulated in a first molding compound. Interconnected metal redistribution layers (RDL) separated by PSV layers are formed on top surfaces of the plurality of individual dies. Thereafter, the reconstructed wafer panel is cut into a plurality of rectangular strips. Thereafter, backend processing is performed on each of the plurality of rectangular strips.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: September 17, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Ian Kent
  • Patent number: 10410909
    Abstract: The invention discloses a support structure for a wafer pedestal; particularly the wafer pedestal has a wafer carrying surface defining holes for accommodation of the support structure. The support structure includes a first surface and extends therebetween. The first surface includes a rising portion for supporting wafer. A center of the first surface and a center of the second surface define an axis that is not parallel to the normal of the first surface. That is, the first surface extends oblique relatively to the second surface such that the support structure according to the invention can be received in the pedestal in an oblique way relative to the wafer carrying surface of the pedestal.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: September 10, 2019
    Assignee: PIOTECH CO., LTD.
    Inventors: Ren Zhou, Xuyen Pham, Shichai Fang
  • Patent number: 10403506
    Abstract: A method of manufacturing electronic dies by separating a wafer into electronic dies, wherein the method comprises forming a groove in the wafer with a first material removal tool having a first thickness, enlarging the groove by a second material removal tool having a second thickness larger than the first thickness, and subsequently increasing a depth of the groove by a third material removal tool having a third thickness smaller than the second thickness until the wafer is separated.
    Type: Grant
    Filed: January 7, 2018
    Date of Patent: September 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Christoph Kamseder, Franco Mariani, Andreas Bauer, Thomas Fischer
  • Patent number: 10340200
    Abstract: A semiconductor device includes: a first semiconductor chip including an electrode pad on one surface of the first semiconductor chip; a multilayer chip stack that is disposed on the one surface of the first semiconductor chip to be connected to the electrode pad; a columnar spacer that is disposed on the one surface of the first semiconductor chip; and an underfill resin. The multilayer chip stack includes a plurality of second semiconductor chips each of which comprises a connection terminal. The connection terminal of one of the second semiconductor chips is directly connected to the electrode pad. Another one of the second semiconductor chips is mounted on the one of the second semiconductor chips. A gap between the first semiconductor chip and the one of the second semiconductor chips and a gap between adjacent ones of the second semiconductor chips are filled with the underfill resin.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: July 2, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Shota Miki
  • Patent number: 10304737
    Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a first modified zone in a wafer by irradiating the wafer with a laser having transmissivity with respect to the wafer along a part of a dicing line on the wafer, and forming a second modified zone in the wafer by irradiating the wafer with the laser along the dicing line on the wafer. The first modified zone is partially formed between a surface of the wafer and the second modified zone, a semiconductor interconnect layer being formed on the surface of the wafer.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 28, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Takanobu Ono, Tsutomu Fujita
  • Patent number: 10283381
    Abstract: An apparatus is for plasma dicing a semiconductor substrate of the type forming part of a workpiece, the workpiece further including a carrier sheet on a frame member, where the carrier sheet carries the semiconductor substrate. The apparatus includes a chamber, a plasma production device configured to produce a plasma within the chamber suitable for dicing the semiconductor substrate, a workpiece support located in the chamber for supporting the workpiece through contact with the carrier sheet, and a frame cover element configured to, in use, contact the frame member thereby clamping the carrier sheet against an auxiliary element disposed in the chamber.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 7, 2019
    Assignee: SPTS TECHNOLOGIES LIMITED
    Inventors: Gautham Ragunathan, David Tossell, Oliver Ansell
  • Patent number: 10276540
    Abstract: A packaging method and a packaging structure are provided. The method includes: providing a first substrate and a second substrate, the second substrate having a fist surface and a second surface opposite to each other, a side surface of the first substrate being adhered to the first surface of the second substrate via an adhesive layer; forming a groove structure on the second surface of the second substrate; providing a base, the base having a first surface and a second surface opposite to each other, the first surface of the base including a sensing region and multiple bonding pads around the sensing region; and laminating the second surface of the second substrate with the first surface of the base to form a cavity between the groove structure and the base, such that the sensing region is located in the cavity.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: April 30, 2019
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Ying Yang, Wei Wang
  • Patent number: 10276525
    Abstract: A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Kuo-Ching Hsu, Mirng-Ji Lii
  • Patent number: 10236246
    Abstract: A semiconductor device includes a crack propagation prevention structure. The crack propagation prevention structure is located at an edge region of a wiring layer stack located on a semiconductor substrate of the semiconductor device. Furthermore, the crack propagation prevention structure laterally surrounds at least one wiring structure located within the wiring layer stack. Additionally, the semiconductor device includes an insulation trench extending into the semiconductor substrate. The insulation trench comprises at least an insulation layer electrically insulating the crack propagation prevention structure from the semiconductor substrate. The crack propagation prevention structure extends vertically at least from a surface of the wiring layer stack to the insulation trench.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: March 19, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Hugo Burke
  • Patent number: 10236428
    Abstract: A lead frame is disclosed. In an embodiment, the lead frame includes a frame having a plurality of lead frame sections, wherein the lead frame sections are connected to the frame, wherein the frame has at least two longitudinal sides and at least two transverse sides, wherein at least in one longitudinal side includes an imprint, and wherein the imprint bolsters stability of the longitudinal side against sagging.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: March 19, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Weng Chung Tan, Rodello Cadiz Sigalat, Hussen Mohd Hanifah, Tobias Gebuhr
  • Patent number: 10211164
    Abstract: A plurality of semiconductor packages are manufactured by a method that includes the steps of bonding a plurality of semiconductor chips on the front side of a wiring substrate, next supplying a sealing compound to the front side of the wiring substrate to form a resin layer from the sealing component on the front side of the wiring substrate, thereby forming a sealed substrate including the wiring substrate and the resin layer covering the semiconductor chips, next cutting the sealed substrate from the resin layer side by using a V blade to thereby form a V groove along each division line, next dividing the wiring substrate along each V groove to obtain a plurality of individual bare packages, and finally forming an electromagnetic shield layer on the upper surface and an inclined side surface of each bare package, thereby obtaining the plural semiconductor packages.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: February 19, 2019
    Assignee: DISCO CORPORATION
    Inventors: Youngsuk Kim, Byeongdeck Jang, Fumio Uchida
  • Patent number: 10186833
    Abstract: A densely-spaced single-emitter laser diode configuration is created by using a laser bar (or similar array configuration) attached to a submount component of a size sufficient to adequately support the enter laser structure. The surface of the submount component upon which the laser structure is attached is metallized and used to form the individual electrical contacts to the laser diodes within the integrated laser structure. Once attached to each other, the laser structure is singulated by creating vertical separations between adjacent light emission areas. The submount metallization is similarly segmented, creating separate electrodes that are used to individually energize their associated laser diodes.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: January 22, 2019
    Assignee: II-VI Incorporated
    Inventors: Giovanni Barbarossa, Norbert Lichtenstein
  • Patent number: 10163750
    Abstract: A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen
  • Patent number: 10160637
    Abstract: A semiconductor package. The semiconductor package includes a first side, a second side, a molded substrate, a die, and a lead frame. The second side of the semiconductor package is opposite the first side of the semiconductor package. The die and lead frame are embedded into the molded substrate. The lead frame is also positioned between the first side and the second side of the semiconductor package to provide a first electrical connection between the first side and the second side of the semiconductor package.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: December 25, 2018
    Assignee: Robert Bosch GmbH
    Inventors: Jay Scott Salmon, Uwe Hansen
  • Patent number: 10153237
    Abstract: A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a scribe line region that extends along the edge of the chip region. The chip package further includes a dielectric layer disposed on the first surface of the substrate. The dielectric layer corresponding to the scribe line region has a through groove that extends along the extending direction of the scribe line region. A method of forming the chip package is also provided.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: December 11, 2018
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Chia-Sheng Lin, Po-Han Lee, Wei-Luen Suen
  • Patent number: 10128214
    Abstract: The present invention discloses a substrate where the lateral surface of the substrate is formed to expose at least one portion of a via(s) for circuit connection. The substrate comprises a plurality of insulating layers; and a plurality of conductive layers separated by the plurality of insulating layers. A first lateral surface of the substrate is formed by the plurality of conductive layers and the plurality of insulating layers. The first lateral surface of the substrate comprises at least one first portion of a first via filled with a first conductive material.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: November 13, 2018
    Assignee: CYNTEC CO., LTD.
    Inventors: Bau-Ru Lu, Ming-Chia Wu, Shao Wei Lu
  • Patent number: 10103008
    Abstract: A micromachining process includes exposing the work piece surface to a precursor gas including a compound having an acid halide functional group; and irradiating the work piece surface with a beam in the presence of the precursor gas, the precursor gas reacting in the presence of the particle beam to remove material from the work piece surface.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: October 16, 2018
    Assignee: FEI COMPANY
    Inventor: Clive D. Chandler
  • Patent number: 10099218
    Abstract: In one aspect, disclosed herein are methods for packaging biochips, including microfluidic chips. The method can comprise bonding a substrate and a cover slide, packaging the bonded chip, creating a vacuum in the package, and applying a pressure on the packaged chip. The method is particularly useful for minimizing bubble formation during low-cost and mass production of microfluidic chips.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 16, 2018
    Assignee: CAPITALBIO CORPORATION
    Inventors: Lei Wang, Xinying Zhou, Li Ma, Juan Xin, Mingxian Lin, Jinhai Feng
  • Patent number: 10083950
    Abstract: A die stacking method is provided. The die stacking method includes executing a manufacturing recipe, and loading an interposer-die mapping file according to the manufacturing recipe. The interposer-die mapping file corresponds to an interposer wafer including interposer dies. The die stacking method also includes loading a combination setting data according to the interposer-die mapping file, and loading a top die number and a top-die ID code of a top-die mapping file according to the combination setting data and the interposer-die mapping file. The top-die ID code corresponds to a top wafer including top dies, and the top die number corresponds to one of the top dies. The die stacking method also includes disposing the one of the top dies of the top wafer on one of the interposer dies of the interposer wafer.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Larry Jann, Chih-Chien Chang, Po-Wen Chuang, Ming-I Chiu, Chang-Hsi Lin, Chih-Chan Li, Yi-Ting Hu
  • Patent number: 10007124
    Abstract: A master wafer includes: a plurality of unit wafers each including a pattern disposed thereon; a coupling surface defined on each of the unit wafers; and a coupling part which couples adjacent unit wafers among the plurality of unit wafers on which the coupling surface is defined, to each other.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: June 26, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joonyong Park, Dongouk Kim, Jihyun Bae, Bongsu Shin, Jong G. Ok, Ilsun Yoon, Sunghoon Lee, Jaeseung Chung, Sukgyu Hahm
  • Patent number: 9960138
    Abstract: Even in case of conductive particles being clamped between stepped sections of substrate electrodes and electrode terminals, conductive particles sandwiched between each main surface of the substrate electrodes and electrode terminals are sufficiently compressed, ensuring electrical conduction. An electronic component is connected to a circuit substrate via an anisotropic conductive adhesive agent, on respective edge-side areas of substrate electrodes of the circuit substrate and electrode terminals of the electronic component, stepped sections are formed and abutted, conductive particles are sandwiched between each main surface and stepped sections of the substrate electrodes and electrode terminals; the conductive particles and stepped sections satisfy formula, a+b+c?0.8 D (1), wherein a is height of the stepped section of the electrode terminals, b is height of the stepped section of the substrate electrodes, c is gap distance between each stepped sections and D is diameter of conductive particles.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: May 1, 2018
    Assignee: DEXERIALS CORPORATION
    Inventors: Kenichi Saruyama, Yasushi Akutsu
  • Patent number: 9957156
    Abstract: An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Chen, Ping-Yin Liu, Chung-Yi Yu, Yeur-Luen Tu
  • Patent number: 9953906
    Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by insulating film, the substrate is divided into element chips by exposing the substrate to a first plasma, element chips having first surface, second surface, and side surface are held spaced from each other on carrier, insulating film is in a state of being exposed, recessed portions are formed by retreating insulating film by exposing element chips to second plasma for ashing, and then recessed portions are covered by protection films by third plasma for formation of the protection film, thereby suppressing creep-up of the conductive material to side surface in the mounting step.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: April 24, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara
  • Patent number: 9911677
    Abstract: A method for manufacturing an element chip includes a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region through etching the protection film anisotropically by exposing the substrate to first plasma and remaining the protection film for covering an end surface of the element region. Furthermore, the method for manufacturing an element chip includes an isotropic etching step of etching the dividing region isotropically by exposing the substrate to second plasma and a plasma dicing step of dividing the substrate to a plurality of element chips including the element region by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: March 6, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Bunzi Mizuno, Mitsuru Hiroshima, Shogo Okita, Noriyuki Matsubara, Atsushi Harikai
  • Patent number: 9905452
    Abstract: In a method of fabricating element chips, a method of forming a mask pattern, and a method of processing a substrate, a process sequence is set such that developing in which the exposure-ended protection film is patterned is performed, after grinding in which the substrate is thinned by grinding a second surface opposite to a first surface to which a photosensitive protection film is pasted. Thereby, it is possible to perform the grinding for thinning in a state where the protection film is stable without being patterned, and to prevent the substrate or the protection film on which a mask pattern of the substrate is formed from being damaged at the time of the grinding, even in a case where a thin substrate of a wafer shape becomes a target.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 27, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Mitsuru Hiroshima, Atsushi Harikai
  • Patent number: 9887113
    Abstract: A semiconductor chip tray is provided that includes a support plate, a first protruding portion, a second protruding portion and a recess. The first protruding portion forms a housing space for a semiconductor chip by being provided on a top surface of the support plate. The second protruding portion is provided on a bottom surface of the support plate, and is fitted to an outer periphery of the first protruding portion of another semiconductor chip tray when the tray is stacked so as to overlap the other tray. The recess is provided on the bottom surface of the support plate. The recess faces a part of the first protruding portion of another chip tray when the tray is stacked so as to overlap the other tray. The recess is formed extending up to an outside of the first protruding portion from the housing space formed by the first protruding portion.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: February 6, 2018
    Assignee: Synaptics Japan GK
    Inventors: Koji Akimoto, Hisao Nakamura, Tsutomu Fukaya
  • Patent number: 9831128
    Abstract: The invention relates to a method of processing a substrate, having a first surface with at least one division line formed thereon and a second surface opposite the first surface. The method comprises applying a pulsed laser beam to the substrate from the side of the first surface, at least in a plurality of positions along the at least one division line, so as to form a plurality of hole regions in the substrate, each hole region extending from the first surface towards the second surface. Each hole region is composed of a modified region and a space in the modified region open to the first surface. The method further comprises removing substrate material along the at least one division line where the plurality of hole regions has been formed.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: November 28, 2017
    Assignee: DISCO CORPORATION
    Inventors: Hiroshi Morikazu, Karl Heinz Priewasser, Nao Hattori
  • Patent number: 9818676
    Abstract: A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe; singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; and plating the exposed side surfaces of the leads with a plating material, wherein the plating material is a different material than the leads. In some embodiments, singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe. In some embodiments, singulating the plurality of semiconductor dies comprises performing separate partial cuts of the leadframe.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: November 14, 2017
    Assignee: UTAC THAI LIMITED
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
  • Patent number: 9812521
    Abstract: An embedded passive chip device includes a chip body and a functional layered structure. The chip body has a circuit-forming surface that is formed with a recess. The functional layered structure is formed on the chip body and includes a conductive layer that has at least a portion which covers at least partially the circuit-forming surface, and a magnetic layer that is disposed within the recess and that is inductively coupled to the conductive layer for generating inductance. A method of making the embedded passive chip device is also disclosed.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: November 7, 2017
    Assignee: WAFER MEMS CO., LTD.
    Inventors: Min-Ho Hsiao, Pang-Yen Lee, Yen-Hao Tseng
  • Patent number: 9780050
    Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: October 3, 2017
    Assignee: XINTEC INC.
    Inventors: Ying-Nan Wen, Chien-Hung Liu, Shih-Yi Lee, Ho-Yin Yiu
  • Patent number: 9777404
    Abstract: A method for manufacturing a silicon carbide epitaxial substrate includes: a step of placing a silicon carbide single crystal substrate within a chamber and reducing a pressure within the chamber; a step of increasing a temperature within the chamber to a first temperature; a step of introducing hydrogen gas into the chamber and adjusting the pressure within the chamber; a step of introducing hydrocarbon gas into the chamber; a substrate reforming step of increasing the temperature within the chamber to a second temperature and holding the temperature at the second temperature for a predetermined time, with the adjusted pressure within the chamber and a flow rate of the hydrogen gas being maintained and the hydrocarbon gas being introduced; and a step of growing an epitaxial layer on the silicon carbide single crystal substrate by introducing silane gas into the chamber with the second temperature being maintained.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: October 3, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Taro Nishiguchi, Jun Genba
  • Patent number: 9735100
    Abstract: A semiconductor device according to the present invention includes a plurality of semiconductor chips, a plate electrode disposed on the plurality of semiconductor chips for connecting the plurality of semiconductor chips, and an electrode disposed on the plate electrode. The electrode has a plurality of intermittent bonding portions to be bonded to the plate electrode and a protruded portion which is protruded erectly from the bonding portions. The protruded portion has an ultrasonic bonding portion which is parallel with the bonding portion and is ultrasonic bonded to an external electrode.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: August 15, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hidetoshi Ishibashi, Yoshihiro Yamaguchi, Naoki Yoshimatsu, Hidehiro Koga
  • Patent number: 9691661
    Abstract: An IC package without using an interposer is disclosed to form a low profile IC package. A single redistribution layer is fabricated according to IC process. A plurality of bottom pads is formed on a bottom of the single redistribution layer adaptive for the IC package to mount onto a mother board. A plurality of top pads is formed on a top of the single redistribution layer. An IC chip mounts on the plurality of top pads. A first molding compound wraps the single redistribution layer on four sides; and a second molding compound embeds the IC chip on top of the redistribution layer.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 27, 2017
    Inventor: Dyi-Chung Hu
  • Patent number: 9671430
    Abstract: A tester includes a level controller for independently restricting the central deformation and the peripheral deformation of a probe card. The level controller includes a single upper plate, a single first lower plate and a plurality of second lower plates. A first elastic force is applied to a central portion of the probe card by the first lower plate to restrict the central deformation. Second elastic forces are independently applied to peripheral portions of the probe card by the individual second lower plates to locally restrict the peripheral deformations.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: June 6, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Young-Hyun Kim
  • Patent number: 9673442
    Abstract: Provided is a method of manufacturing a membrane electrode assembly in which an electrode catalyst layer is formed on a surface of an electrolyte membrane. This method includes: a drying of drying a substrate sheet to which a catalyst ink is applied, the catalyst ink containing catalyst support particles on which a catalytic metal is supported, a solvent, and an ionomer; and a heat treatment of performing a heat treatment on the substrate sheet, on which the catalyst ink is dried, after the drying at a heat treatment temperature which is equal to or higher than a glass transition temperature of the ionomer to prepare the electrode catalyst layer. The heat treatment is performed after a concentration of a solvent gas obtained by gasification of the solvent, which remains in a chamber of a heating device for performing the heat treatment, is a predetermined concentration threshold or lower.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: June 6, 2017
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Shimpei Yano
  • Patent number: 9659879
    Abstract: A semiconductor device includes a semiconductor die having a guard ring disposed in a periphery of the semiconductor die. The semiconductor device also includes a conductive pad over the guard ring. the semiconductor device further has a passivation partially covering the conductive pad, and including a recess to expose a portion of the conductive pad and a post passivation interconnect (PPI) over the passivation. In the semiconductor device, a conductor is extended upwardly from the recess and connected to a portion of the PPI.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Ching-Feng Yang, Chun-Lin Lu, Kai-Chiang Wu, Vincent Chen
  • Patent number: 9648760
    Abstract: A substrate structure includes a dielectric layer, a metal foil, a patterned metal layer, a first patterned solder-resist layer and a second patterned solder-resist layer. The dielectric layer includes a first surface and a second surface, and the first surface has a plurality of recesses. The metal foil is disposed on the second surface. The patterned metal layer is disposed on the first surface, the patterned metal layer has a plurality of openings, and the openings are respectively corresponding to and expose the recesses. The first patterned solder-resist layer is filled in each of the recesses and corresponding to each of the openings. A top surface of the first patterned solder-resist layer is substantially coplanar with a top surface of the patterned metal layer. The second patterned solder-resist layer is disposed on the first patterned solder-resist layer and in the openings, and covers a portion of the patterned metal layer.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 9, 2017
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Chao-Min Wang
  • Patent number: 9640497
    Abstract: A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 2, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Takashi Noma, Shinzo Ishibe
  • Patent number: 9635756
    Abstract: Disclosed herein is a manufacturing method of a circuit board. The manufacturing method includes a first step for preparing a prepreg in which a core material is impregnated with an uncured resin. The prepreg has a through-hole surrounded by the core material and the resin so as to penetrate through the core material and the resin. The manufacturing method further includes a second step for housing a semiconductor IC in the through-hole, and a third step for pressing the prepreg so that a part of the resin flows into the through-hole to allow the semiconductor IC housed in the through-hole to be embedded in the resin.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 25, 2017
    Assignee: TDK CORPORATION
    Inventors: Kazutoshi Tsuyutani, Hiroshige Ohkawa, Yoshihiro Suzuki, Tsuyoshi Mochizuki