Substrate Dicing Patents (Class 438/113)
  • Patent number: 11031276
    Abstract: A wafer expanding method for expanding a wafer having a plurality of rectangular devices respectively formed in a plurality of separate regions defined by a plurality of division lines, thereby increasing spacing between any adjacent ones of the devices, each rectangular device having a pair of shorter sides and a pair of longer sides. The wafer expanding method includes a jig preparing step of preparing an annular jig having an elliptical opening, the elliptical opening having a shorter portion for restricting a width of the annular exposed portion in a first direction where the shorter sides of the devices extend to a first width and a longer portion for restricting the width of the annular exposed portion in a second direction where the longer sides of the devices extend to a second width larger than the first width.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: June 8, 2021
    Assignee: DISCO CORPORATION
    Inventors: Yoshihiro Kawaguchi, Masaru Nakamura
  • Patent number: 11024220
    Abstract: Apparatus and method relating generally to an LED display is disclosed. In such an apparatus, a driver die has a plurality of driver circuits. A plurality of light-emitting diodes, each having a thickness of 10 microns or less and discrete with respect to one another, are respectively interconnected to the plurality of driver circuits. The plurality of light-emitting diodes includes a first portion for a first color, a second portion for a second color, and a third portion for a third color respectively obtained from a first, a second, and a third optical wafer. The first, the second, and the third color are different from one another.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: June 1, 2021
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Rajesh Katkar, Javier A. Delacruz, Ilyas Mohammed, Belgacem Haba
  • Patent number: 11018044
    Abstract: A wafer expanding method increases spacing between adjacent devices formed on a wafer. The method includes preparing an annular jig having a first restricting portion, a second restricting portion, and a curved restricting portion connecting the first restricting portion and the second restricting portion, mounting a ring frame supporting the wafer through an adhesive tape on a cylindrical frame fixing member, next mounting the annular jig on the ring frame, and next fixing the ring frame and the annular jig to the cylindrical frame fixing member, and operating a cylindrical pushing member having an outer circumference corresponding to an outer circumference of the wafer to push up an annular exposed portion of the adhesive tape defined between the wafer and the ring frame and thereby lift the wafer away from the ring frame, thereby expanding the annular exposed portion and increasing the spacing between the adjacent devices.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: May 25, 2021
    Assignee: DISCO CORPORATION
    Inventors: Masaru Nakamura, Saki Kozuma
  • Patent number: 11004759
    Abstract: An electronic component includes a resin structure including first and second surfaces facing each other, an electronic component element contained in the resin structure, including first and second main surfaces facing each other, and side surfaces connecting the first and second main surfaces, and being exposed to the first surface of the resin structure, and a through-electrode penetrating the resin structure to connect the first and second surfaces of the resin structure, in which the through-electrode are in contact with at least one of the side surfaces of the electronic component element.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: May 11, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hiroshi Somada
  • Patent number: 10978607
    Abstract: A device includes a substrate and an optoelectronic chip buried in the substrate. The substrate may include an opening above a first optical transduction region of the first optoelectronic chip and above a second optical transduction region of a second optoelectronic chip.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: April 13, 2021
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Alexandre Coullomb, Romain Coffy, Jean-Michel Riviere
  • Patent number: 10971400
    Abstract: A semiconductor device includes a device layer having a semiconductor element and a wiring layer, a first structure, a second structure at an outer periphery of the first structure and having a thickness smaller than that of the first structure, and a conductive layer that covers the first structure and the second structure. The first structure comprises a first substrate having the device layer formed on a first surface thereof and a through hole formed through a second surface thereof that is opposite to the first surface to reach the device layer, and an inner portion of a second substrate facing the first surface and bonded to the first surface by a first adhesive layer.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: April 6, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masahiko Murano, Fumito Shoji, Tatsuo Migita, Ippei Kume
  • Patent number: 10943794
    Abstract: A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: March 9, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Owen R. Fay, Akshay N. Singh, Kyle K. Kirby
  • Patent number: 10937680
    Abstract: Among other things a method including releasing a discrete component from an interim handle and depositing a discrete component on a handle substrate, attaching the handle substrate to the discrete component, and removing the handle substrate from the discrete component.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: March 2, 2021
    Assignee: Uniqarta, Inc.
    Inventor: Val Marinov
  • Patent number: 10903121
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a uniform rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: January 26, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, Karthik Balakrishnan, James S. Papanu
  • Patent number: 10888040
    Abstract: The present disclosure relates to a shielded double-sided module, which includes a module substrate with a ground plane, at least one top electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a number of first module contacts attached to a bottom surface of the module substrate, a second mold compound, and a shielding structure. The second mold compound resides over the bottom surface of the module substrate, and each first module contact is exposed through the second mold compound. The shielding structure completely covers a top surface and a side surface of the module, and is electrically coupled to the ground plane within the module substrate.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: January 5, 2021
    Assignee: Qorvo US, Inc.
    Inventors: David Jandzinski, Thomas Scott Morris, Brian Howard Calhoun
  • Patent number: 10856456
    Abstract: The present disclosure relates to a shielded double-sided module, which includes a module substrate with a ground plane, at least one top electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a number of first module contacts attached to a bottom surface of the module substrate, a second mold compound, and a shielding structure. The second mold compound resides over the bottom surface of the module substrate, and each first module contact is exposed through the second mold compound. The shielding structure completely covers a top surface and a side surface of the module, and is electrically coupled to the ground plane within the module substrate.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: December 1, 2020
    Assignee: Qorvo US, Inc.
    Inventors: David Jandzinski, Thomas Scott Morris, Brian Howard Calhoun
  • Patent number: 10847497
    Abstract: A mounting apparatus of a chip including a mechanism configured to arrange a front surface of a chip and a front surface of a substrate to face each other such that a back surface of the chip is attached to a sheet, the sheet having a first portion corresponding to the selected chip and a the second portion arranged at a periphery of the first portion corresponding to the selected chip in the sheet when seen in a direction perpendicular to the front surface of the substrate; a holding mechanism moving in a direction that is not perpendicular to the front surface of the substrate and arranged to hold the second portion of the sheet; and a pushing mechanism for pushing the back surface of the chip through the first portion of the sheet so that the front surface of the chip is brought close to the front surface of the substrate with the first portion deformed in a state where the second portion is held by the holding mechanism, and configured to release the pushing mechanism from the first portion of the sheet t
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: November 24, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoichiro Kurita
  • Patent number: 10825731
    Abstract: Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: November 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Takashi Noma
  • Patent number: 10825704
    Abstract: A chip transferring machine includes a chip carrier, a chip transferring module, and a chip carrier substrate. The chip carrier carries a plurality of chips. The chip transferring module includes at least one conveyor belt having an adhesive surface. The chip carrier substrate carries the plurality of chips. The chip carrier, the chip transferring module, and the chip carrier substrate are disposed on a same production line, and the chip carrier and the chip carrier substrate are disposed under or above the adhesive surface of the conveyor belt.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: November 3, 2020
    Assignee: ASTI GLOBAL INC., TAIWAN
    Inventor: Chien-Shou Liao
  • Patent number: 10784161
    Abstract: A method for manufacturing a semiconductor device includes: partially dicing a substrate wafer arrangement having a plurality of semiconductor chips, wherein the partial dicing forms trenches around the semiconductor chips on a front-side of the substrate wafer arrangement, the depth being greater than a target thickness of a semiconductor chip; filling the trenches with a polymer material to form a polymer structure; first thinning of the back-side to expose portions of the polymer structure; forming a conductive layer on the back-side of the substrate wafer arrangement so that the exposed portions of the polymer structure are covered; second thinning of the back-side to form insular islands of conductive material, the insular islands separated from each other by the polymer structure, each insular island corresponding to a respective one of the semiconductor chips; and dicing the substrate wafer arrangement along the polymer structure.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 22, 2020
    Assignee: Infineon Technologies AG
    Inventors: Ingo Muri, Bernhard Goller
  • Patent number: 10784164
    Abstract: A wafer having a device area on one side with a plurality of devices partitioned by division lines is divided into dies. An adhesive tape for protecting devices is attached to the one side of the wafer, the adhesive tape adhering to at least some, optionally all, of the devices. A carrier for supporting the tape is attached to the side of the tape opposite to the one side by an attachment means provided over an entire surface area of the adhesive tape which is in contact with the carrier. The wafer is cut along the division lines. The side of the wafer opposite to the one side is mechanically partially cut, and a remaining part of the cuts in the wafer is mechanically cut and/or cut by laser and/or cut by plasma from the side of the wafer opposite to the one side.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 22, 2020
    Assignee: DISCO CORPORATION
    Inventor: Karl Heinz Priewasser
  • Patent number: 10748800
    Abstract: A chip bonding device is disclosed, including a first motion stage (110), a second motion stage (200), a chip pickup element (160), a transfer carrier (170), a chip adjustment system (1000), a bonding stage (420) and a control system (500). A chip bonding method is also disclosed, in which a set of chips are temporarily retained on the transfer carrier (170) and their positions on the transfer carrier (170) are accurately adjusted by using the chip adjustment system (1000), followed by bonding the chips on the transfer carrier (170) simultaneously onto the substrate (430). With this batch bonding approach, flip-chips can be bonded with greatly enhanced efficiency. Moreover, picking up and bonding chips in batches can balance times for chip picking up, fine chip position tuning and chip bonding, thereby ensuring high bonding accuracy while increasing the throughput.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 18, 2020
    Assignee: SHANGHAI MICRO ELECTRONICS EQUIPMENT (GROUP) CO., LTD.
    Inventors: Yuebin Zhu, Feibiao Chen, Hai Xia, Bin Yu, Song Guo, Yaping Ge
  • Patent number: 10748850
    Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 18, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Takashi Noma, Francis J. Carney
  • Patent number: 10741504
    Abstract: A semiconductor wafer provided with a pseudo chip between a product chip and a pattern prohibiting region is prepared. With the edge portion of the semiconductor wafer left, the bottom surface of the inner semiconductor substrate is ground, and then, the semiconductor wafer is cut in a ring shape to remove the edge portion. Here, in the pseudo chip, a protective film covering the conductive pattern is formed on the top surface of the semiconductor substrate and the end surface of the protective film facing the pattern prohibiting region is positioned on the conductive pattern. Further, in plan view, the inner peripheral end of the edge portion is positioned in the pattern prohibiting region, and the pattern prohibiting region between the inner peripheral end of the edge portion and the pseudo chip is cut in a ring shape.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: August 11, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takuji Yoshida
  • Patent number: 10675791
    Abstract: A plurality of molded cover members are manufactured by first singulating a single sheet of cover material, such as glass, into a plurality of separate, discrete cover members, placing the cover members in spaced-apart positions on a releaseable carrier, and applying a molded material to the perimeter of each cover member. The molded material can be applied by a blanket molding technique whereby gaps between adjacent cover members are filled, and then the cover members are singulated, leaving a portion of the cover material on the perimeter of each cover member, and then the singulated, molded cover members are released from the releasable carrier. Alternatively, the molded material is applied by a patterned molding technique whereby molding material is applied to the perimeter of each cover member without fully filling the gaps between adjacent cover members, and then the molded cover members are released from the releasable carrier.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: June 9, 2020
    Assignee: IDEX Biometrics ASA
    Inventors: David N. Light, Anne L. McAleer
  • Patent number: 10644190
    Abstract: A fluidic assembly method is provided that uses a counterbore pocket structure. The method is based upon the use of a substrate with a plurality of counterbore pocket structures formed in the top surface, with each counterbore pocket structure having a through-hole to the substrate bottom surface. The method flows an ink with a plurality of objects over the substrate top surface. As noted above, the objects may be micro-objects in the shape of a disk. For example, the substrate may be a transparent substrate and the disks may be light emitting diode (LED) disks. Simultaneously, a suction pressure is created at the substrate bottom surface. In response to the suction pressure from the through-holes, the objects are drawn into the counterbore pocket structures. Also provided is a related fluidic substrate assembly.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: May 5, 2020
    Assignee: eLux Inc.
    Inventors: Changqing Zhan, Paul John Schuele, Mark Albert Crowder, Sean Mathew Garner, Timothy James Kiczenski
  • Patent number: 10615106
    Abstract: The present disclosure relates to a chip package structure and a method for forming a chip package. A package unit is formed from the chip and an encapsulant surrounding the chip to have an increased area. A redistribution layer is formed on the package unit to draw out to and redistribute input/output terminals on a surface of the chip. The redistribution layer is then electrically coupled to a leadframe or a printed circuit board by external and electrical connectors. The method and the package structure are suitable for providing a chip package having input/output terminals with high density, reducing package cost, and improving package reliability.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: April 7, 2020
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventor: Jiaming Ye
  • Patent number: 10600670
    Abstract: An apparatus which comprises an expansion unit configured for expanding a foil, and a mounting unit configured for subsequently mounting the expanded foil on a frame and a workpiece, in particular a wafer, on the expanded foil.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies AG
    Inventor: Thomas Fischer
  • Patent number: 10566257
    Abstract: A method for manufacturing a wiring board includes forming on a first support plate a first laminated wiring portion including conductor and insulating layers such that the first portion has a first surface on first support plate side and a second surface, separating the first portion from the first plate, forming a conductor layer exposed on the first surface and including pads, laminating the first portion on a second support plate such that the second surface of the first portion faces second support plate side, forming on the first surface of the first portion a second laminated wiring portion including conductor and insulating layers such that the second portion has a third surface on second support plate side and a fourth surface, forming cavity in the second portion on the second plate such that the cavity exposes the pads, and separating the first and second portions from the second plate.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 18, 2020
    Assignee: IBIDEN CO., LTD.
    Inventor: Naoki Kurahashi
  • Patent number: 10566268
    Abstract: A package to die connection system and method are provided. The system includes a semiconductor device having a substrate with a top surface. A gasket is affixed to the top surface of the substrate and has at least one cavity with a portion of the cavity open to a sidewall of the gasket. A semiconductor die is attached to the top surface of the substrate. A sidewall of the semiconductor die is abutted with the sidewall of the gasket. A portion of a metal layer is exposed to the open portion of the cavity. A pillar located in the cavity is electrically connected to the exposed portion of the metal layer.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: February 18, 2020
    Assignee: NXP USA, INC.
    Inventors: Mark Douglas Hall, Walter J. Ciosek, David Russell Tipple
  • Patent number: 10559546
    Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin
  • Patent number: 10468255
    Abstract: A processing method for performing laser processing on a wafer includes: a reflected light detecting step of irradiating the wafer with light for state detection along a plurality of planned dividing lines, and detecting reflected light of the light from an upper surface of the wafer; a region setting step of setting a first region and a second region to the planned dividing lines based on the reflected light; a first laser processing step of performing laser processing on the first region under a first laser processing condition; and a second laser processing step of performing laser processing on the second region under a second laser processing condition.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: November 5, 2019
    Assignee: DISCO CORPORATION
    Inventor: Jinyan Zhao
  • Patent number: 10461016
    Abstract: A ceramic module for power semiconductor integrated packaging and a preparation method thereof are disclosed. The ceramic module includes a ceramic substrate and an integrated metal dam layer. By providing the integral metal dam layer on the upper surface of the ceramic substrate and forming cavities around die bonding regions, the semiconductor chip can be hermetically sealed. By providing a heat dissipation layer on the lower surface of the ceramic substrate, the heat generated by the semiconductor chip can be quickly conducted to the outside. The product has a simple production process and high product consistency.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: October 29, 2019
    Assignee: DONGGUAN CHINA ADVANCED CERAMIC TECHNOLOGY CO., LTD.
    Inventors: Zhaohui Wu, Wei Kang, Xiaoquan Guo, Jun Zhang
  • Patent number: 10453795
    Abstract: A ground isolation webbing structure package includes a top level with an upper interconnect layer having upper ground contacts, upper data signal contacts, and a conductive material upper ground webbing structure that is connected to the upper ground contacts and surrounds the upper data signal contacts. The upper contacts may be formed over and connected to via contacts or traces of a lower layer of the same interconnect level. The via contacts of the lower layer may be connected to upper contacts of a second interconnect level which may also have such webbing. There may also be at least a third interconnect level having such webbing. The webbing structure electrically isolates and reduces cross talk between the signal contacts, thus providing higher frequency and more accurate data signal transfer between devices such as integrated circuit (IC) chips attached to a package.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Yu Amos Zhang, Mathew J. Manusharow, Kemal Aygun, Mohiuddin Mazumder
  • Patent number: 10424511
    Abstract: A method of processing a plate-shaped workpiece that includes on a face side thereof layered bodies containing metal which are formed in superposed relation to projected dicing lines includes the steps of holding a face side of the workpiece on a holding table, thereafter, applying a laser beam having a wavelength that is absorbable by the workpiece to a reverse side thereof along the projected dicing lines to form laser-processed grooves in the workpiece which terminate short of the layered bodies, and thereafter, cutting bottoms of the laser-processed grooves with a cutting blade to sever the workpiece together with the layered bodies along the projected dicing lines. The step of cutting bottoms of the laser-processed grooves includes the step of cutting bottoms of the laser-processed grooves while supplying a cutting fluid containing an organic acid and an oxidizing agent to the workpiece.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 24, 2019
    Assignee: DISCO CORPORATION
    Inventor: Kenji Takenouchi
  • Patent number: 10418342
    Abstract: A method to fabricate a reconstructed panel based fan-out wafer level package is described. A reconstructed wafer panel is provided comprising a plurality of individual dies encapsulated in a first molding compound. Interconnected metal redistribution layers (RDL) separated by PSV layers are formed on top surfaces of the plurality of individual dies. Thereafter, the reconstructed wafer panel is cut into a plurality of rectangular strips. Thereafter, backend processing is performed on each of the plurality of rectangular strips.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: September 17, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Ian Kent
  • Patent number: 10410909
    Abstract: The invention discloses a support structure for a wafer pedestal; particularly the wafer pedestal has a wafer carrying surface defining holes for accommodation of the support structure. The support structure includes a first surface and extends therebetween. The first surface includes a rising portion for supporting wafer. A center of the first surface and a center of the second surface define an axis that is not parallel to the normal of the first surface. That is, the first surface extends oblique relatively to the second surface such that the support structure according to the invention can be received in the pedestal in an oblique way relative to the wafer carrying surface of the pedestal.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: September 10, 2019
    Assignee: PIOTECH CO., LTD.
    Inventors: Ren Zhou, Xuyen Pham, Shichai Fang
  • Patent number: 10403506
    Abstract: A method of manufacturing electronic dies by separating a wafer into electronic dies, wherein the method comprises forming a groove in the wafer with a first material removal tool having a first thickness, enlarging the groove by a second material removal tool having a second thickness larger than the first thickness, and subsequently increasing a depth of the groove by a third material removal tool having a third thickness smaller than the second thickness until the wafer is separated.
    Type: Grant
    Filed: January 7, 2018
    Date of Patent: September 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Christoph Kamseder, Franco Mariani, Andreas Bauer, Thomas Fischer
  • Patent number: 10340200
    Abstract: A semiconductor device includes: a first semiconductor chip including an electrode pad on one surface of the first semiconductor chip; a multilayer chip stack that is disposed on the one surface of the first semiconductor chip to be connected to the electrode pad; a columnar spacer that is disposed on the one surface of the first semiconductor chip; and an underfill resin. The multilayer chip stack includes a plurality of second semiconductor chips each of which comprises a connection terminal. The connection terminal of one of the second semiconductor chips is directly connected to the electrode pad. Another one of the second semiconductor chips is mounted on the one of the second semiconductor chips. A gap between the first semiconductor chip and the one of the second semiconductor chips and a gap between adjacent ones of the second semiconductor chips are filled with the underfill resin.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: July 2, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Shota Miki
  • Patent number: 10304737
    Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a first modified zone in a wafer by irradiating the wafer with a laser having transmissivity with respect to the wafer along a part of a dicing line on the wafer, and forming a second modified zone in the wafer by irradiating the wafer with the laser along the dicing line on the wafer. The first modified zone is partially formed between a surface of the wafer and the second modified zone, a semiconductor interconnect layer being formed on the surface of the wafer.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 28, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Takanobu Ono, Tsutomu Fujita
  • Patent number: 10283381
    Abstract: An apparatus is for plasma dicing a semiconductor substrate of the type forming part of a workpiece, the workpiece further including a carrier sheet on a frame member, where the carrier sheet carries the semiconductor substrate. The apparatus includes a chamber, a plasma production device configured to produce a plasma within the chamber suitable for dicing the semiconductor substrate, a workpiece support located in the chamber for supporting the workpiece through contact with the carrier sheet, and a frame cover element configured to, in use, contact the frame member thereby clamping the carrier sheet against an auxiliary element disposed in the chamber.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 7, 2019
    Assignee: SPTS TECHNOLOGIES LIMITED
    Inventors: Gautham Ragunathan, David Tossell, Oliver Ansell
  • Patent number: 10276540
    Abstract: A packaging method and a packaging structure are provided. The method includes: providing a first substrate and a second substrate, the second substrate having a fist surface and a second surface opposite to each other, a side surface of the first substrate being adhered to the first surface of the second substrate via an adhesive layer; forming a groove structure on the second surface of the second substrate; providing a base, the base having a first surface and a second surface opposite to each other, the first surface of the base including a sensing region and multiple bonding pads around the sensing region; and laminating the second surface of the second substrate with the first surface of the base to form a cavity between the groove structure and the base, such that the sensing region is located in the cavity.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: April 30, 2019
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Ying Yang, Wei Wang
  • Patent number: 10276525
    Abstract: A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Kuo-Ching Hsu, Mirng-Ji Lii
  • Patent number: 10236428
    Abstract: A lead frame is disclosed. In an embodiment, the lead frame includes a frame having a plurality of lead frame sections, wherein the lead frame sections are connected to the frame, wherein the frame has at least two longitudinal sides and at least two transverse sides, wherein at least in one longitudinal side includes an imprint, and wherein the imprint bolsters stability of the longitudinal side against sagging.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: March 19, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Weng Chung Tan, Rodello Cadiz Sigalat, Hussen Mohd Hanifah, Tobias Gebuhr
  • Patent number: 10236246
    Abstract: A semiconductor device includes a crack propagation prevention structure. The crack propagation prevention structure is located at an edge region of a wiring layer stack located on a semiconductor substrate of the semiconductor device. Furthermore, the crack propagation prevention structure laterally surrounds at least one wiring structure located within the wiring layer stack. Additionally, the semiconductor device includes an insulation trench extending into the semiconductor substrate. The insulation trench comprises at least an insulation layer electrically insulating the crack propagation prevention structure from the semiconductor substrate. The crack propagation prevention structure extends vertically at least from a surface of the wiring layer stack to the insulation trench.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: March 19, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Hugo Burke
  • Patent number: 10211164
    Abstract: A plurality of semiconductor packages are manufactured by a method that includes the steps of bonding a plurality of semiconductor chips on the front side of a wiring substrate, next supplying a sealing compound to the front side of the wiring substrate to form a resin layer from the sealing component on the front side of the wiring substrate, thereby forming a sealed substrate including the wiring substrate and the resin layer covering the semiconductor chips, next cutting the sealed substrate from the resin layer side by using a V blade to thereby form a V groove along each division line, next dividing the wiring substrate along each V groove to obtain a plurality of individual bare packages, and finally forming an electromagnetic shield layer on the upper surface and an inclined side surface of each bare package, thereby obtaining the plural semiconductor packages.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: February 19, 2019
    Assignee: DISCO CORPORATION
    Inventors: Youngsuk Kim, Byeongdeck Jang, Fumio Uchida
  • Patent number: 10186833
    Abstract: A densely-spaced single-emitter laser diode configuration is created by using a laser bar (or similar array configuration) attached to a submount component of a size sufficient to adequately support the enter laser structure. The surface of the submount component upon which the laser structure is attached is metallized and used to form the individual electrical contacts to the laser diodes within the integrated laser structure. Once attached to each other, the laser structure is singulated by creating vertical separations between adjacent light emission areas. The submount metallization is similarly segmented, creating separate electrodes that are used to individually energize their associated laser diodes.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: January 22, 2019
    Assignee: II-VI Incorporated
    Inventors: Giovanni Barbarossa, Norbert Lichtenstein
  • Patent number: 10160637
    Abstract: A semiconductor package. The semiconductor package includes a first side, a second side, a molded substrate, a die, and a lead frame. The second side of the semiconductor package is opposite the first side of the semiconductor package. The die and lead frame are embedded into the molded substrate. The lead frame is also positioned between the first side and the second side of the semiconductor package to provide a first electrical connection between the first side and the second side of the semiconductor package.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: December 25, 2018
    Assignee: Robert Bosch GmbH
    Inventors: Jay Scott Salmon, Uwe Hansen
  • Patent number: 10163750
    Abstract: A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen
  • Patent number: 10153237
    Abstract: A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a scribe line region that extends along the edge of the chip region. The chip package further includes a dielectric layer disposed on the first surface of the substrate. The dielectric layer corresponding to the scribe line region has a through groove that extends along the extending direction of the scribe line region. A method of forming the chip package is also provided.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: December 11, 2018
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Chia-Sheng Lin, Po-Han Lee, Wei-Luen Suen
  • Patent number: 10128214
    Abstract: The present invention discloses a substrate where the lateral surface of the substrate is formed to expose at least one portion of a via(s) for circuit connection. The substrate comprises a plurality of insulating layers; and a plurality of conductive layers separated by the plurality of insulating layers. A first lateral surface of the substrate is formed by the plurality of conductive layers and the plurality of insulating layers. The first lateral surface of the substrate comprises at least one first portion of a first via filled with a first conductive material.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: November 13, 2018
    Assignee: CYNTEC CO., LTD.
    Inventors: Bau-Ru Lu, Ming-Chia Wu, Shao Wei Lu
  • Patent number: 10099218
    Abstract: In one aspect, disclosed herein are methods for packaging biochips, including microfluidic chips. The method can comprise bonding a substrate and a cover slide, packaging the bonded chip, creating a vacuum in the package, and applying a pressure on the packaged chip. The method is particularly useful for minimizing bubble formation during low-cost and mass production of microfluidic chips.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 16, 2018
    Assignee: CAPITALBIO CORPORATION
    Inventors: Lei Wang, Xinying Zhou, Li Ma, Juan Xin, Mingxian Lin, Jinhai Feng
  • Patent number: 10103008
    Abstract: A micromachining process includes exposing the work piece surface to a precursor gas including a compound having an acid halide functional group; and irradiating the work piece surface with a beam in the presence of the precursor gas, the precursor gas reacting in the presence of the particle beam to remove material from the work piece surface.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: October 16, 2018
    Assignee: FEI COMPANY
    Inventor: Clive D. Chandler
  • Patent number: 10083950
    Abstract: A die stacking method is provided. The die stacking method includes executing a manufacturing recipe, and loading an interposer-die mapping file according to the manufacturing recipe. The interposer-die mapping file corresponds to an interposer wafer including interposer dies. The die stacking method also includes loading a combination setting data according to the interposer-die mapping file, and loading a top die number and a top-die ID code of a top-die mapping file according to the combination setting data and the interposer-die mapping file. The top-die ID code corresponds to a top wafer including top dies, and the top die number corresponds to one of the top dies. The die stacking method also includes disposing the one of the top dies of the top wafer on one of the interposer dies of the interposer wafer.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Larry Jann, Chih-Chien Chang, Po-Wen Chuang, Ming-I Chiu, Chang-Hsi Lin, Chih-Chan Li, Yi-Ting Hu
  • Patent number: 10007124
    Abstract: A master wafer includes: a plurality of unit wafers each including a pattern disposed thereon; a coupling surface defined on each of the unit wafers; and a coupling part which couples adjacent unit wafers among the plurality of unit wafers on which the coupling surface is defined, to each other.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: June 26, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joonyong Park, Dongouk Kim, Jihyun Bae, Bongsu Shin, Jong G. Ok, Ilsun Yoon, Sunghoon Lee, Jaeseung Chung, Sukgyu Hahm