Abstract: A method for manufacturing a semiconductor device includes forming at least one stripe-shaped protection film over a multilayer film in a scribe region of a semiconductor substrate having a plurality of semiconductor element regions formed therein, the protection film having a thickness larger in a center portion thereof than at an end surface thereof and being made of a member which transmits a laser beam, and removing the multilayer film in the scribe region by irradiating the protection film with a laser beam.

Abstract: A process to divide a wafer into individual chips is disclosed. The process (1) etches semiconductor layers for an active device to form two grooves putting the virtual cut line therebetween, where the semiconductor wafer is to be divided along the virtual cut line; (2) etches the substrate in a region including the virtual cut line but offset from the groove from the back surface thereof so as to expose the semiconductor layers in the primary surface; and (3) etches the semiconductor layer exposed in step (2).

Abstract: A wafer having a front face formed with a functional device is irradiated with laser light while positioning a light-converging point within the wafer with the rear face of the wafer acting as a laser light incident face, so as to generate multiphoton absorption, thereby forming a starting point region for cutting due to a molten processed region within the wafer along a line. Consequently, a fracture can be generated from the starting point region for cutting naturally or with a relatively small force, so as to reach the front face and rear face. Therefore, when an expansion film is attached to the rear face of the wafer by way of a die bonding resin layer after forming the starting point region for cutting and then expanded, the wafer and die bonding resin layer can be cut along the line.

Abstract: A package structure includes first and second substrates, a sealant and a filler. The first substrate has a surface including an active region and a bonding region. The first substrate has a component in the active region and a pad in bonding region. The pad is electrically connected to the component. The sealant is disposed on the surface surrounding the active region. The sealant has a breach at a side of the active region. The second substrate is bonded to the first substrate via the sealant. The second substrate has a first opening corresponding to the pad, and a second opening corresponding to the breach. The filler fills the second opening, covers the breach such that the first substrate, the second substrate, the sealant and the filler together form a sealed space for accommodating the component.

Abstract: It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor, and the circuit or the semiconductor device to a substrate having flexibility. According to the present invention, a large opening or a plurality of openings is formed at an insulating film, a conductive film connected to a thin film transistor is formed at the opening, and a peeling layer is removed, then, a layer having the thin film transistor is transposed to a substrate provided with a conductive film or the like. A thin film transistor according to the present invention has a semiconductor film which is crystallized by laser irradiation and prevents a peeling layer from exposing at laser irradiation not to be irradiated with laser light.

Abstract: A semiconductor device has a build-up interconnect structure formed over an active surface of a semiconductor wafer containing a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the interconnect structure. Bumps are formed over the interconnect structure. A protective coating material is deposited over the insulating layer and saw street. A lamination tape is applied over the coating material. A portion of a back surface of the semiconductor wafer is removed. A mounting tape is applied over the back surface. The lamination tape is removed while leaving the coating material over the insulating layer and saw street. A first channel is formed through the saw street extending partially through the semiconductor wafer. The coating material is removed after forming the first channel. A second channel is formed through the saw street and the mounting tape is removed to singulate the semiconductor wafer.

Abstract: A method for fabricating a multi-chip stacked structure includes joining multiple wafers with interconnect structures interposed between each set of adjacent wafers. As each wafer is added to the stack, the new wafer is thinned to expose a through silicon via and back side metallization is performed. After the last wafer has been so joined, the wafer stack is diced and then joined to a substrate with a final interconnect structure interposed between the final wafer and the substrate.

Abstract: The present invention aims to provide a film for forming a protective layer that is capable of preventing cracks in a low dielectric material layer of a semiconductor wafer while suppressing an increase in the number of steps in the manufacture of a semiconductor device. This object is achieved by a film for forming a protective layer on a bumped wafer in which a low dielectric material layer is formed, including a support base, an adhesive layer, and a thermosetting resin layer, laminated in this order, wherein the melt viscosity of the thermosetting resin layer is 1×102 Pa·S or more and 2×104 Pa·S or less, and the shear modulus of the adhesive layer is 1×103 Pa or more and 2×106 Pa or less, when the thermosetting resin layer has a temperature in a range of 50 to 120° C.

Abstract: A method is disclosed to divide a wafer into chips. In the method, a substrate is provided. The substrate is made of an isolating material. An epitaxial laminate is provided on the substrate. At least one slit is made through the epitaxial laminate completely to form at least two chips connected to each other by the substrate only so that each of the chips includes a portion of the substrate and a portion of the epitaxial laminate. Positive and negative electrodes are formed in each of the chips. An upper protective film is provided to cover an upper side of each of the chips except the electrodes. A peripheral protective film is provided into the slit to cover the periphery of the portion of the epitaxial laminate of each of the chips. Finally, the chips are separated from each other.

Abstract: A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die.

Abstract: A method for manufacturing an integrated circuit package system includes: providing a base device; attaching a base interconnect to the base device; applying an encapsulant over the base device and the base interconnect; and forming a re-routing film over the encapsulant, the base device, and the base interconnect for connectivity without a substrate.

Abstract: A method for manufacturing a semiconductor device, includes: a step of etching a Si (111) substrate along a (111) plane of the Si (111) substrate to separate a Si (111) thin-film device having a separated surface along the (111) plane.

Abstract: A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of dice are mounted on a carrier (e.g., a plastic carrier). Each die has a plurality of wire bonded contact studs secured to its associated I/O pads. An encapsulant is applied over the carrier to cover the dice and at least portions of the contact studs to form an encapsulant carrier structure. After the encapsulant has been applied, a first surface of the encapsulant and the contact studs are ground such that exposed portions of the contact studs are smooth and substantially co-planar with the encapsulant. In some embodiments, a redistribution layer is formed over the encapsulant carrier structure and solder bumps are attached to the redistribution layer. A contact encapsulant layer is applied over the encapsulant carrier structure to provide extra mechanical support for the resulting packages.

Abstract: A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of dice are mounted on a carrier (e.g., a plastic carrier). Each die has a plurality of wire bonded contact studs secured to its associated I/O pads. An encapsulant is applied over the carrier to cover the dice and at least portions of the contact studs to form an encapsulant carrier structure. After the encapsulant has been applied, a first surface of the encapsulant and the contact studs are ground such that exposed portions of the contact studs are smooth and substantially co-planar with the encapsulant. In some embodiments, a redistribution layer is formed over the encapsulant carrier structure and solder bumps are attached to the redistribution layer. A contact encapsulant layer is applied over the encapsulant carrier structure to provide extra mechanical support for the resulting packages.

Abstract: A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of die cavities are formed in a plastic carrier. In some preferred embodiments, the die cavities are formed by laser ablation. A multiplicity of dice are placed on the carrier, with each die being placed in an associated die cavity. Each of the dice preferably has a multiplicity of I/O bumps formed thereon. An encapsulant is applied over the carrier to form an encapsulant layer that covers the dice and fills portions of the cavities that are not occupied by the dice. In some preferred embodiments, the encapsulant is an epoxy material applied by screen printing and the dice are not physically attached to the carrier prior to the application of the encapsulant. In these embodiments, the epoxy encapsulant serves to secure the dice to the carrier.

Abstract: A method of manufacturing semiconductor chips includes providing a semiconductor substrate including circuit regions, irradiating the semiconductor substrate with a laser beam onto to form a frangible layer, and polishing the semiconductor substrate to separate the circuit regions of the semiconductor substrate from one another into semiconductor chips. The frangible layer may be removed completely during the polishing of the semiconductor substrate.

Abstract: Circuit modules including identification codes and a method of managing them are provided. A module substrate includes signal input output terminals and outer ground terminals provided at the peripheral portions of a surface which becomes a mounting surface when the circuit module is completed. An inner-ground-terminal formation area surrounded by the signal input output terminals and the outer ground terminals includes a plurality of inner ground terminals arranged in a matrix of rows and columns. One of the edge portions is a direction identification area. The inner ground terminal is not provided in the direction identification area, and a first identification code having information about the position of the module substrate is provided in the direction identification area.

Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.

Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.

Abstract: A plurality of chip sealing bodies stacked on a wiring substrate with a connection terminal. The chip sealing body includes a semiconductor chip having a semiconductor integrated circuit, a pad and a conductive connecting material, and a resin sealing the semiconductor chip. The chip sealing body is shaped into a cubic form in which a portion of the conductive connecting material except an end portion located on an external device side and all surfaces of semiconductor chip is sealed by the resin and the end portion of the conductive connecting material located on the external device side is exposed from the cubic form. A conductive bonding wire connects the end portions of the conductive connecting materials and the connection terminal respectively. A resin sealing material seals the plurality of chip sealing bodies, the conductive bonding wire, and the wiring substrate.

Abstract: By performing plasma etching on the second surface of a semiconductor wafer on the first surface of which an insulating film is placed in dividing regions and on the second surface of which a mask for defining the dividing regions are placed, the second surface being located opposite from the first surface, the insulating film is exposed from an etching bottom portion by removing portions that correspond to the dividing regions. Subsequently, by continuously performing the plasma etching in the state in which the exposed insulating film is surface charged with electric charge due to ions in the plasma, corner portions put in contact with the insulating film are removed in the device-formation-regions. Consequently, individualized semiconductor chips having a high transverse rupture strength are manufactured.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a substrate base side and a substrate stack side; mounting an integrated circuit over the substrate stack side; attaching a stack connector to the substrate stack side; forming an encapsulation over the stack connector and the integrated circuit; attaching an external connector to the substrate base side; attaching an adhesive tape to the external connector having spacing between the adhesive tape and the substrate base side; cutting a step portion in the encapsulation to expose the stack connector; cutting a singulation kerf in the package substrate having exit damage on the substrate base side; and removing the adhesive tape.

Abstract: In one embodiment, a method of forming a semiconductor device package includes: (1) providing a carrier and a semiconductor device including an active surface; (2) forming a first redistribution structure including a first electrical interconnect extending laterally within the first structure and a plurality of second electrical interconnects extending vertically from a first surface of the first interconnect, each second interconnect including a lower surface adjacent to the first surface and an upper surface opposite the lower surface; (3) disposing the device on the carrier such that the active surface is adjacent to the carrier; (4) disposing the first structure on the carrier such that the upper surface of each second interconnect is adjacent to the carrier, and the second interconnects are positioned around the device; and (5) forming a second redistribution structure adjacent to the active surface, and including a third electrical interconnect extending laterally within the second structure.

Abstract: A chip package structure includes a substrate, a die, and a package body. The substrate includes a single patterned, electrically conductive layer, and a patterned dielectric layer adjacent to an upper surface of the electrically conductive layer. A part of a lower surface of the electrically conductive layer forms first contact pads for electrical connection externally. The patterned dielectric layer exposes a part of the upper surface of the electrically conductive layer to form second contact pads. The electrically conductive layer exposes the lower surface of the patterned dielectric layer on a lower periphery of the substrate. The die is electrically connected to the second contact pads, the patterned dielectric layer and the die being positioned on the same side of the electrically conductive layer. The package body is disposed adjacent to the upper surface of the electrically conductive layer and covers the patterned dielectric layer and the die.

Abstract: It is an object of the present invention to provide a manufacturing method of a semiconductor device where a semiconductor element is prevented from being damaged and throughput speed thereof is improved, even in a case of thinning or removing a supporting substrate after forming the semiconductor element over the supporting substrate.

Abstract: A prefabricated multi-die leadframe having a plurality of contact pads is mounted over a temporary carrier. A first semiconductor die is mounted over the carrier between the contact pads of the leadframe. A second semiconductor die is mounted over the contact pads of the leadframe and over the first die. An encapsulant is deposited over the leadframe and first and second die. The carrier is removed. A first interconnect structure is formed over the leadframe and the first die and a first surface of the encapsulant. A channel is cut through the encapsulant and leadframe to separate the contact pads. A plurality of conductive vias can be formed through the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The second interconnect structure is electrically connected to the conductive vias.

Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.

Abstract: A method of manufacturing a hybrid integrated circuit device of the present invention includes the steps of preparing a lead frame which constituted by units each having a plurality of leads, and fixing a circuit substrate on each unit of the lead frame by fixing pads which are formed on the surface of the circuit substrate to the leads, where a space between a first pad which is formed at an end edge of the circuit substrate and a second pad which is adjacent to the first pad is set narrower than a space between the pads themselves.

Abstract: A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices, the second lead forming the second external electrode; and cutting the sealing member between the plurality of semiconductor devices to separate

Abstract: A method and apparatus are described for fabricating a low-pin-count chip package (701) including a die pad (706) for receiving an integrated circuit device and a plurality of connection leads (702) having recessed lead ends (704) at the outer peripheral region of each contact lead. After forming the package body (202) over the integrated circuit device, unplated portions (104) of the exposed bottom surface of the selectively plated lead frame are partially etched to form recessed lead ends (302) at the outer peripheral region of each contact lead, and the recessed lead ends are subsequently re-plated (402) to provide wettable recessed lead ends at the outer peripheral region of each contact lead.

Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Abstract: Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

Abstract: An improved manufacturing method for semiconductor devices is provided. This method can prevent chips and cracks from being generated when the rear face of the semiconductor substrate is polished. The manufacturing method includes preparing a semiconductor substrate having a front face and a rear face. The front face has an inner surface area and a peripheral surface area. Circuit elements are provided in the inner surface area of the semiconductor substrate. The manufacturing method also includes sealing the circuit elements with circuit sealing resin. The manufacturing method also includes providing cured resin in the peripheral surface area of the semiconductor substrate. The manufacturing method also includes polishing the rear face of the semiconductor substrate after the circuit sealing step. The manufacturing method also includes cutting the semiconductor substrate after the substrate polishing step so as to obtain semiconductor devices.

Abstract: Embodiments of the invention provide a semiconductor chip having a passivation layer extending along a surface of a semiconductor substrate to an edge of the semiconductor substrate, and methods for their formation. One aspect of the invention provides a semiconductor chip comprising: a semiconductor substrate; a passivation layer including a photosensitive polyimide disposed along a surface of the semiconductor substrate and extending to at least one edge of the semiconductor substrate; and a channel extending through the passivation layer to the surface of the semiconductor substrate.

Abstract: An integrated circuit package system is provided including forming a wafer having a back side and an active side, forming a recess in the wafer from the back side, forming a cover in the recess, and singulating the wafer at the recess filled with the cover.

Abstract: A method provides for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure. A wafer is produced with one or more dies formed thereon with at least one of its edges at an offset angle from a natural cleavage direction of a diamond structure of a base material forming the wafer. At least one dicing line has one or more protection elements for protecting the dies from undesired cracking while the wafer is being diced along the dicing line.

Abstract: A semiconductor device is described that includes a die connected between a conductive platform and a conductive clip. The semiconductor device is formed by a process that includes mounting a first surface of each of multiple die to each of a number of conductive mounting platforms of a lead frame structure. The process also mounts a clip structure to the lead frame structure, the clip structure including a number of conductive clips. Mounting of the clip structure to the lead frame structure includes aligning each of the conductive clips with corresponding ones of the conductive mounting platforms so that a portion of each of the conductive clips contacts a second surface of a corresponding die.

Abstract: The present invention aims to provide a tape for holding a chip that makes pasting and peeling of a chip-shaped workpiece easy. It is a tape for holding a chip having a configuration in which a pressure-sensitive adhesive layer is formed on a base material, wherein the pressure-sensitive adhesive layer has a chip-shaped workpiece pasting region onto which a chip-shaped workpiece is pasted and a frame pasting region onto which a mount frame is pasted, and that is used by pasting the mount frame to the frame pasting region, wherein the 180-degree peeling adhesive power of the pressure-sensitive adhesive layer to a silicon mirror wafer at the frame pasting region is 5 times or more the 180-degree peeling adhesive power of the pressure-sensitive adhesive layer to a silicon mirror wafer at the chip-shaped workpiece pasting region.

Abstract: A die-bonding film contains a glycidyl-group-containing acrylic copolymer (a) having a weight-average molecular weight of 500,000 or more and a phenolic resin (b), wherein the weight ratio (x/y) of the content x of the glycidyl-group-containing acrylic copolymer (a) to the content y of the phenolic resin (b) is 5 or more and 30 or less, and the die-bonding film substantially does not contain an epoxy resin having a weight-average molecular weight of 5000 or less. Thus, a die-bonding film having a high reliability is provided by which a sufficient adhering strength and an elastic modulus at a high temperature can be obtained before and after curing; the workability is good; air bubbles (voids) do not stay at the boundary between the die-bonding film and the adherend; and the die-bonding film can withstand a humidity resistance solder reflow test.

Abstract: Integrated circuits (Ia, Ib) on a wafer (2) comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (3). Only the first integrated circuits (Ia) comprise each at least one bump (8) not contacting their relevant electric circuits (3).

Abstract: A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV.

Abstract: An electronic mail (email) system may include at least one email server having mailboxes for storing email messages, and a plurality of mobile wireless communications devices. The system may further include at least one email aggregation server for repetitively polling the mailboxes for email messages, and forwarding the email messages to respective mobile wireless communications devices. The at least one email aggregation server may determine time overlapped polling of corresponding mailboxes and time stagger a next polling thereof.

Abstract: A laser processing method for preventing particles from occurring from cut sections of chips obtained by cutting a silicon wafer is provided. An irradiation condition of laser light L for forming modified regions 77 to 712 is made different from an irradiation condition of laser light L for forming the modified regions 713 to 719 such as to correct the spherical aberration of laser light L in areas where the depth from the front face 3 of a silicon wafer 11 is 335 ?m to 525 ?m. Therefore, even when the silicon wafer 11 and a functional device layer 16 are cut into semiconductor chips from modified regions 71 to 719 acting as a cutting start point, twist hackles do not appear remarkably in the areas where the depth is 335 ?m to 525 ?m, whereby particles are hard to occur.

Abstract: A method for wafer level chip scale package comprises providing a wafer with semiconductor chips formed thereon, forming a groove alongside each chip, providing a wafer size clip array with a plurality of clip contact areas each extending to a down set connecting bar, connecting the plurality of clip contact areas to a plurality of the electrodes disposed on a top surface of the chips with down set connecting bars disposed inside the grooves, encapsulating top of wafer in molding compound, thinning the bottom portion of the wafer and dicing the thin wafer into single chip packages. The chip has source and gate electrodes on a top surface connected to a first and second clip contact areas extending to a first a second down set connecting bars respectively, with the bottom surfaces of the down set connecting bars substantially coplanar to a drain electrode located at the chip bottom surface.

Abstract: A method for thin wafer handling and processing is provided. In one embodiment, the method comprises providing a wafer having a plurality of semiconductor chips, the wafer having a first side and a second side. A plurality of dies are attached to the first side of the wafer, at least one of the dies are bonded to at least one of the plurality of semiconductor chips. A wafer carrier is provided, wherein the wafer carrier is attached to the second side of the wafer. The first side of the wafer and the plurality of dies are encapsulated with a planar support layer. A first adhesion tape is attached to the planar support layer. The wafer carrier is then removed from the wafer and the wafer is diced into individual semiconductor packages.

Abstract: Provided herein are methods and systems for scribing solar cell structures to create isolated solar cells. According to various embodiments, the methods involve scanning an excimer laser beam along a scribe line of a solar cell structure to ablate electrically active layers of the structure. A photomask having variable transmittance is disposed between the beam source and the solar cell structure. The transmittance is calibrated to produce variable fluence levels such that a stepped scribed profile is obtained. In certain embodiments, a front contact/absorber/back contact stack is removed along a portion of the scribe line, while a front contact/absorber stack is simultaneously removed along a parallel portion, with the back contact layer unremoved. In this manner, the scribe electrically isolates solar cells on either side of the scribe line, while providing a contact point to the back contact layer of one of the solar cells for subsequent cell-cell interconnection.

Abstract: An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate having a first surface and a second surface, wherein at least two conducting pads are disposed on the first surface of the substrate; partially removing the substrate from the second surface of the substrate to form at least two holes extending towards the first surface, wherein the holes correspondingly and respectively align with one of the conducting pads; after the holes are formed, partially removing the substrate from the second substrate to form at least a recess extending towards the first surface, wherein the recess overlaps with the holes; forming an insulating layer on a sidewall and a bottom of the trench and on sidewalls of the holes; and forming a conducting layer on the insulating layer, wherein the conducting layer electrically contacts with one of the conducting pads.

Abstract: Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die.

Abstract: An integrated circuit (IC) device is provided. The IC device includes an IC die having opposing first and second surfaces, a carrier coupled to the first surface of the IC die, a laminate coupled to the carrier and the second surface of the IC die, and a trace located on a surface of the laminate and electrically coupled to a bond pad located on the second surface of the IC die. The trace is configured to couple the bond pad to a circuit board.

Abstract: A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too.