Including Contaminant Removal Or Mitigation Patents (Class 438/115)
  • Publication number: 20090311829
    Abstract: An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom semiconductor chip; and a planar dielectric layer over the top die and the protecting material. The protecting material has a top surface leveled with a top surface of the top die.
    Type: Application
    Filed: June 17, 2008
    Publication date: December 17, 2009
    Inventors: Ku-Feng Yang, Wen-Chih Chiou, Weng-Jin Wu, Ming-Chung Sung
  • Patent number: 7628865
    Abstract: An embodiment of the invention provides a method to clean a surface. The method includes at least partly liberating contaminants from the surface with a contaminant liberating device, and capturing the contaminants that have been at least partly liberated with a contaminant removal device, the contaminant removal device generating at least one optical trap to trap the contaminants that have been at least partly liberated. Embodiments of the invention also provide a device manufacturing method, a method to clean a surface of an optical element, a cleaning assembly and cleaning apparatus, and a lithographic apparatus.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: December 8, 2009
    Assignee: ASML Netherlands B.V.
    Inventor: Mandeep Singh
  • Patent number: 7615406
    Abstract: By joining a lid member to a base member, internal electrodes put in contact with the lid member and an electronic device connected to the internal electrodes are placed in an internal space located in between the base member and the lid member. By performing etching from a surface of the lid member on a side opposite from the base member by a prescribed method, through holes that reach the surface of the internal electrodes are formed. A conductive material is applied to the through holes, and external electrodes connected to the internal electrodes are formed in a plane, completing a thin type electronic device package.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: November 10, 2009
    Assignee: Panasonic Corporation
    Inventors: Kazushi Higashi, Yukihiro Maegawa
  • Patent number: 7595221
    Abstract: A method of fabricating a device using a sacrificial layer by selecting a substrate; forming a first step on the substrate, where the first step is formed from a second material; depositing a sacrificial layer along the first step and the substrate; depositing a second step on a portion of the sacrificial layer; depositing a second layer on each of a portion of the substrate, sacrificial layer and second step that shares a common resistance to removal by a same agent as the substrate, the first step and the second step; removing the second step; removing a portion of the sacrificial layer such that a gap is created between the second layer and the first step, wherein at least a portion of the sacrificial layer remains such that the second layer adhered to the substrate remains; and processing the substrate beneath the gap.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: September 29, 2009
    Assignee: The United States of America as represented by the Director, National Security Agency
    Inventors: John L. Fitz, Harris Turk
  • Publication number: 20090221104
    Abstract: A method of manufacturing a semiconductor device involves the steps of: forming a plurality of product formation areas each having a circuit and a plurality of first electrode pads over a main surface of a semiconductor wafer; arranging a plurality of second electrode pads with larger pitches than the first electrode pads in each of the product formation areas; segmenting the semiconductor wafer to separate the plural product formation areas and provide a plurality of semiconductor devices each having the circuit, the plural first electrode pads and the plural second electrode pads on a first surface; and cleaning foreign matter off the first surface of the semiconductor device after the step of segmenting the semiconductor devices.
    Type: Application
    Filed: May 14, 2009
    Publication date: September 3, 2009
    Inventors: Yoshihiko Yamaguchi, Atsushi Fujishima, Yusuke Ohta
  • Patent number: 7572675
    Abstract: A method is provided for removing excess encapsulation material from unmolded surfaces of a molded substrate including semiconductor packages by utilizing an acid solution. The method comprises the steps of mounting the substrate to a holding device with the unmolded surfaces facing an acid source for supplying an acid solution, contacting the unmolded surfaces with the acid solution for a sufficient time to remove the excess encapsulation material from the unmolded surfaces while substantially avoiding contact with molded surfaces thereof, and thereafter removing the substrate from contact with the acid solution.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: August 11, 2009
    Assignee: ASM Technology Singapore Pte Ltd.
    Inventors: Srikanth Narasimalu, Premkumar Jeromerajan
  • Patent number: 7534658
    Abstract: The specification teaches a technique for manufacturing microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In an embodiment, a process for manufacturing the devices includes efficiently integrating a getter material.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: May 19, 2009
    Assignee: SAES Getters S.p.A.
    Inventor: Marco Amiotti
  • Patent number: 7534657
    Abstract: A method of manufacturing a semiconductor device involves the steps of: forming a plurality of product formation areas each having a circuit and a plurality of first electrode pads over a main surface of a semiconductor wafer; arranging a plurality of second electrode pads with larger pitches than the first electrode pads in each of the product formation areas; segmenting the semiconductor wafer to separate the plural product formation areas and provide a plurality of semiconductor devices each having the circuit, the plural first electrode pads and the plural second electrode pads on a first surface; and cleaning foreign matter off the first surface of the semiconductor device after the step of segmenting the semiconductor devices.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: May 19, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yoshihiko Yamaguchi, Atsushi Fujishima, Yusuke Ohta
  • Patent number: 7531382
    Abstract: A method of creating a patterned device by selecting a substrate; depositing a mask layer on the substrate; forming a first step on the mask layer; depositing a sacrificial layer along the first step and the mask layer; depositing a blocking layer on the sacrificial layer; removing a portion of the blocking layer, where a portion of the blocking layer remains such that no gap exists between the blocking layer and the sacrificial layer and the remaining blocking layer is adhered to the mask layer; removing a portion of the sacrificial layer such that a gap is created between the blocking layer and the first step, where a portion of the sacrificial layer remains such that the blocking layer adhered to the mask layer remains; etching the mask layer beneath the gap; and processing the substrate through the gap in the mask layer.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: May 12, 2009
    Assignee: The United States of America as represented by the Director National Security Agency
    Inventors: John L. Fitz, Harris Turk
  • Patent number: 7485478
    Abstract: A high-quality light emitting device is provided which has a long-lasting light emitting element free from the problems of conventional ones because of a structure that allows less degradation, and a method of manufacturing the light emitting device is provided. After a bank is formed, an exposed anode surface is wiped using a PVA (polyvinyl alcohol)-based porous substance or the like to level the surface and remove dusts from the surface. An insulating film is formed between an interlayer insulating film on a TFT and the anode. Alternatively, plasma treatment is performed on the surface of the interlayer insulating film on the TFT for surface modification.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: February 3, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hirokazu Yamagata, Shunpei Yamazaki, Toru Takayama
  • Publication number: 20090026598
    Abstract: A wafer-level package that employs one or more integrated hydrogen getters within the wafer-level package on a substrate wafer or a cover wafer. The hydrogen getters are provided between and among the integrated circuits on the substrate wafer or the cover wafer, and are deposited during the integrated circuit fabrication process. In one non-limiting embodiment, the substrate wafer is a group III-V semiconductor material, and the hydrogen getter includes a titanium layer, a nickel layer, and a palladium layer.
    Type: Application
    Filed: July 24, 2007
    Publication date: January 29, 2009
    Applicant: Northrop Grumman Space & Mission Systems Corp.
    Inventors: Kelly Jill Tornquist Hennig, Patty Pei-Ling Chang-Chien, Xianglin Zeng, Jeffrey Ming-Jer Yang
  • Publication number: 20090001537
    Abstract: A method for providing improved gettering in a vacuum encapsulated microdevice is described. The method includes designing a getter alloy to more closely approximate the coefficient of thermal expansion of a substrate upon which the getter alloy is deposited. Such a getter alloy may have a weight percentage of less than about 8% iron (Fe) and greater than about 50% zirconium, with the balance being vanadium and titanium, which may better match the coefficient of thermal expansion of a silicon substrate. In one exemplary embodiment, the improved getter alloy is deposited on a silicon substrate prepared with a plurality of indentation features, which increase the surface area of the substrate exposed to the vacuum. Such a getter alloy is less likely to delaminate from the indented surface of the substrate material during heat-activated steps, such as activating the getter material and bonding a lid wafer to the device wafer supporting the microdevice.
    Type: Application
    Filed: June 27, 2007
    Publication date: January 1, 2009
    Applicant: Innovative Micro Technology
    Inventor: Jeffery F. Summers
  • Patent number: 7465977
    Abstract: There is described a method for producing a packaged integrated circuit. The method comprises a first step of building an integrated circuit having a micro-structure suspended above a micro-cavity, and having a heating element on the micro-structure capable of heating itself and its immediate surroundings. A layer of protective material is then deposited on said micro-structure such that at least a top surface of the micro-structure and an opening of the micro-cavity is covered, wherein the protective material is in a solid state at room temperature and can protect the micro-structure during silicon wafer dicing procedures and subsequent packaging. The integrated circuit is packaged and an electric current is passed through the heating element such that a portion of the protective material is removed and an unobstructed volume is provided above and below the micro-structure.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: December 16, 2008
    Assignee: Microbridge Technologies Inc.
    Inventors: Leslie M. Landsberger, Oleg Grudin
  • Patent number: 7459342
    Abstract: The adhesive property of the mold resin exposed to the ball face side of a semiconductor package and under-filling resin is improved, and the manufacturing method of the semiconductor device which can prevent peeling at both interface is obtained. The sputtering step which does sputtering of the ball face side of the semiconductor package whose mold resin in which wax or fatty acid was included exposed to the ball face side by Ar plasma, the step which does flip chip junction of the semiconductor package at wiring substrate upper part after the sputtering step, and the step fills up with under-filling resin between the semiconductor package and the wiring substrate are included.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: December 2, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Eiji Hayashi, Takahiro Sugimura
  • Publication number: 20080280398
    Abstract: A method of forming a MEMS (Micro-Electro-Mechanical System), includes forming an ambient port through a MEMS cap which defines a cavity containing a plurality of MEMS actuators therein; and bonding a lid arrangement to the MEMS cap to hermetically seal the ambient port.
    Type: Application
    Filed: July 21, 2008
    Publication date: November 13, 2008
    Inventors: Charles C. Haluzak, Arthur Piehl, Chien-Hua Chen, Jennifer Shih
  • Publication number: 20080280393
    Abstract: A method for forming a semiconductor structure includes forming a first connector over at least one pad of a first substrate, the first connector having at least one curved sidewall. An encapsulation layer is formed at least partially over the first connector so as to partially expose a top surface of the first connector. A solder structure is formed, contacting the first connector.
    Type: Application
    Filed: May 9, 2007
    Publication date: November 13, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hui Lee, Mirng-Ji Lii
  • Patent number: 7449366
    Abstract: A wafer level packaging cap for covering a device wafer with a device thereon and a fabrication method thereof are provided. The method includes operations of forming a plurality of connection grooves on a wafer, forming a seed layer on the connection grooves, forming connection parts by filling the connection grooves with a metal material, forming cap pads on a top surface of the wafer to be electrically connected to the connection parts, bonding a supporting film with the top surface of the wafer on which the cap pads are formed, forming a cavity on a bottom surface of the wafer to expose the connection parts through the cavity, and forming metal lines on the bottom surface of the wafer to be electrically connected to the connection parts.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: November 11, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-chul Lee, Jong-oh Kwon, Woon-bae Kim, Ji-hyuk Lim, Suk-jin Ham, Jun-sik Hwang, Chang-youl Moon
  • Publication number: 20080265402
    Abstract: A system and method for utilizing lead-free multi-core modules with organic substrates,including a base portion configured to attach a semiconductor chip;and a cap portion further comprising: a bottom portion configured to be sealed to the base portion;and a vacuum port;wherein when a vacuum is drawn at the vacuum port,a re-workable seal between the base portion and the cap portion is provided to enable rework.
    Type: Application
    Filed: April 30, 2007
    Publication date: October 30, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Arvind K. Sinha
  • Patent number: 7442577
    Abstract: The present invention is a method of fabricating a patterned device using a sacrificial spacer layer. The first step in this process is to select an appropriate substrate and form a step thereon. The sacrificial layer is then applied to the substrate and a blocking layer is deposited on the sacrificial layer. The blocking layer is etched back to define the mask for the semiconductor structure and the sacrificial layer is removed. The substrate is then etched using the gap created by removal of the sacrificial layer.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: October 28, 2008
    Assignee: United States of America as represented by the Director, National Security Agency The United
    Inventors: John Leslie Fitz, Harris Turk
  • Publication number: 20080248613
    Abstract: A micromechanical device assembly includes a micromechanical device enclosed within a processing region and a lubricant channel formed through an interior wall of the processing region and in fluid communication with the processing region. Lubricant is injected into the lubricant channel via capillary forces and held therein via surface tension of the lubricant against the internal surfaces of the lubrication channel. The lubricant channel containing the lubricant provides a ready supply of fresh lubricant to prevent stiction from occurring between interacting components of the micromechanical device disposed within the processing region.
    Type: Application
    Filed: September 26, 2007
    Publication date: October 9, 2008
    Inventors: Dongmin Chen, William Spencer Worley, Hung-Nan Chen
  • Patent number: 7416918
    Abstract: A packaging technology that fabricates a microelectronic package including build-up layers, having conductive traces, on an encapsulated microelectronic die and on other packaging material that surrounds the microelectronic die, wherein an moisture barrier structure is simultaneously formed with the conductive traces. An exemplary microelectronic package includes a microelectronic die having an active surface and at least one side. Packaging material(s) is disposed adjacent the microelectronic die side(s), wherein the packaging material includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive trace is then formed on the first dielectric material layer to electrically contact the microelectronic die active surface.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: August 26, 2008
    Assignee: Intel Corporation
    Inventor: Qing Ma
  • Publication number: 20080191336
    Abstract: The invention discloses a subminiature electronic device with a hermetic cavity and method of manufacturing the same. It particularly relates to a chip type or chip scale packaged electronic device produced in substrate level. Firstly, a sacrificial layer is coated onto each of the identical microstructures disposed on a large substrate. A protective layer containing glass powders is then applied to encapsulate the sacrificial layer. Afterwards, the sacrificial layer is removed so as to form a cavity between the microstructure and the protective layer. The whole protective layer is then melted at elevated temperature to seal the cavity in an environment of specific gas. Finally, the large substrate is diced into a plurality of individual devices with a hermetic cavity over the microstructure. The applicable fields include micro-electronic circuits, micro-vibration systems, micro electrical-mechanical systems (MEMS), and gas discharge apparatuses.
    Type: Application
    Filed: May 24, 2007
    Publication date: August 14, 2008
    Inventor: Chon-Ming Tsai
  • Publication number: 20080180924
    Abstract: A broadband surface mounting package includes a housing having a flat bottom wall forming parallel first and second surfaces. An integral wall forms, with the bottom wall, an enclosure having a top opening to provide access to an interior compartment or cavity to receive a microwave component. The second surface is arranged to contact a printed circuit board (PCB) for attachment to lands or pads on the PCB. Cylindrical holes in the enclosure each defines an axis parallel to the bottom wall, and has a dimension, generally transverse to the bottom wall, to extend from the second surface to at least the first surface, and has an axial length sufficient to provide a through hole in the wall and a gap within the bottom wall proximate to and inwardly from the wall.
    Type: Application
    Filed: January 18, 2008
    Publication date: July 31, 2008
    Inventor: Naseer A. Shaikh
  • Publication number: 20080180919
    Abstract: A module substrate structure may include a substrate, a passive device mounted on the substrate, and a protection layer covering the passive device. The protection layer may cover the passive device either completely or partly. Where a plurality of passive devices are present, the protection layer may cover either all or a selected number of the passive devices. A semiconductor module may include the module substrate structure in addition to a semiconductor chip mounted on the substrate, and an encapsulant covering the substrate. The semiconductor chip may be electrically connected to the passive device. Manufacturing processes (e.g., plasma treatment) may cause the passive device to be bombarded by ions and become electrically charged. Consequently, the electrical charges built up in the passive device may discharge (flow) and cause damage to the semiconductor chip.
    Type: Application
    Filed: April 18, 2007
    Publication date: July 31, 2008
    Inventor: Gwang-Man Lim
  • Patent number: 7393716
    Abstract: A semiconductor device comprising organic semiconductor material (14) has one or more barrier layers (16) disposed at least partially thereabout to protect the organic semiconductor material (14) from environment-driven changes that typically lead to inoperability of a corresponding device. If desired, the barrier layer can be comprised of partially permeable material that allows some substances therethrough to thereby effect disabling of the encapsulated organic semiconductor device after a substantially predetermined period of time. Getterers (141) may also be used to protect, at least for a period of time, such organic semiconductor material.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: July 1, 2008
    Assignee: Motorola, Inc.
    Inventors: Steven Scheifers, Daniel Gamota, Andrew Skipor, Krishna Kalyanasundaram
  • Patent number: 7387928
    Abstract: A device and method for making a capacitor and other high frequency and/or microwave components. In particular, an air dielectric capacitor has a first electrode and a second electrode that are spaced apart, planar and each of a different size or area. The first electrode is a smaller, planar electrode that is sealed along its edge with a sealant having a constant dielectric to the second electrode, a larger planar electrode. The dielectric constant of the sealant along the edges of the first electrode is substantially uniform. In addition, an epoxy cover extends around the periphery of the smaller first electrode and is supported along the surface of the larger second electrode.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: June 17, 2008
    Inventor: William S. H. Cheung
  • Patent number: 7387912
    Abstract: A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structure embedded in a plurality of materials having a plurality of vaporization temperatures. The plurality of materials is formed on the electronic chip and the conductive structure is coupled to the electronic chip. To fabricate the circuit assembly, a support structure, including interstices, is formed on an electronic chip. The interstices of the support structure are filled with a material having a vaporization temperature that is less than the vaporization temperature of the support structure. Conductive structures are embedded in the support structure and the material, and a connective structure is mounted on the support structure. Finally, the material is removed from the interstices by heating the circuit assembly.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: June 17, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Publication number: 20080131817
    Abstract: Provided herein are gettering members that include a monitor substrate and a conditioning layer thereon. Also provided herein are methods of forming gettering layers and methods of performing immersion lithography processes using the same.
    Type: Application
    Filed: November 13, 2007
    Publication date: June 5, 2008
    Inventors: Jin-Young Yoon, Hyun-Woo Kim, Chan Hwang, Yun-Kyeong Jang
  • Publication number: 20080130082
    Abstract: Methods for forming a MEMS display device are provided. In one embodiment, a transparent substrate comprising an array of MEMS devices (e.g., interferometric modulators) formed thereon is annealed following removal of a sacrificial silicon layer. The array is subsequently encapsulated with a backplate comprising a desiccant. MEMS devices disposed below the desiccant have an offset voltage substantially equal to zero.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 5, 2008
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: Manish Kothari, Fritz Y.F. Su, Bangalore Natarajan, Nassim Khonsari
  • Patent number: 7377961
    Abstract: Thermally tuned lasers may use a resistive thermal device (RTD), sensitive to hydrogen, within a hermetic enclosure. Over time, hydrogen trapped within the enclosure or out gassed from other components within the enclosure may degrade the accuracy of the RTD. A vent comprising a hydrogen selective permeable membrane, such as palladium or a palladium alloy, provided in the enclosure vents hydrogen to mitigate damage to the RTD.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: May 27, 2008
    Assignee: Intel Corporation
    Inventor: Mark E. McDonald
  • Patent number: 7374974
    Abstract: A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at least partially filled with a dielectric material and a control port adapted to capacitively couple to the at least one thyristor body region in the substrate. In a more specific implementation, the dielectric material includes deposited dielectric material that is adapted to exhibit resistance to voltage-induced stress that thermally-grown dielectric materials generally exhibit. In another implementation, the dielectric material includes thermally-grown dielectric material, and when used in connection with highly-doped material in the trench, grows faster on the highly-doped material than on a sidewall of the trench that faces the at least on thyristor body region in the substrate.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: May 20, 2008
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Andrew Horch, Scott Robins
  • Patent number: 7371614
    Abstract: An image sensor device and methods thereof. In an example method, a protective layer may be formed over at least one microlens. An adhesive layer may be formed over the protective layer. The adhesive layer may be removed so as to expose the protective layer. The protective layer may be removed so as to expose the at least one microlens, the exposed at least one microlens not including residue from the adhesive layer. The at least one microlens may have an improved functionality due at least in part to the lack of residue from the adhesive layer. In an example, the at least one microlens may be included in an image sensor module.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: May 13, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Chai Kwon, Suk-Chae Kang, Kang-Wook Lee, Gu-Sung Kim, Jong-Woo Kim, Seong-Il Han, Sun-Wook Heo, Jung-Hang Yi, Keum-Hee Ma
  • Patent number: 7371603
    Abstract: The invention relates to an LED package and proposes a method of fabricating an LED package including steps of providing a package substrate having a mounting area of an LED and a metal pattern to be connected with the LED, and plasma-treating the package substrate to reform at least a predetermined surface area of the package substrate where a resin-molded part will be formed. The method also includes mounting the LED on the mounting area on the substrate package and electrically connecting the LED with the metal pattern, and forming the resin-molded part in the mounting area of the LED to seal the LED package.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: May 13, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yong Suk Kim, Seog Moon Choi, Hyoung Ho Kim, Yong Sik Kim
  • Patent number: 7332430
    Abstract: The invention relates to a method for improving the mechanical properties of BOC module arrangements in which chips have 3D structures, solder balls, ? springs or soft bumps which are mechanically and electrically connected by means of solder connections to terminal contacts on a printed circuit board or leadframe. Advantages are achieved by providing a casting compound for the wafer or the chips after they have been individually separated and before they are mounted on the printed circuit board in such a way that the tips of the 3D structures protrude from this compound. The casting compound preferably has elastic and mechanical properties comparable to those of silicon.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: February 19, 2008
    Assignee: Infineon Technologies AG
    Inventors: Axel Brintzinger, Octavio Trovarelli
  • Publication number: 20080020514
    Abstract: A bonded wafer is produced by a method comprising a step of implanting ions of a light element such as hydrogen, helium or the like into a wafer for active layer at a predetermined depth position to form an ion implanted layer, a step of bonding the wafer for active layer to a wafer for support substrate through an insulating film, a step of exfoliating the wafer at the ion implanted layer, a first heat treatment step of conducting a sacrificial oxidation for reducing damage on a surface of an active layer exposed through the exfoliation and a second heat treatment step of raising a bonding strength, in which the second heat treatment step is continuously conducted after the first heat treatment step without removing an oxide film formed on the surface of the active layer.
    Type: Application
    Filed: July 20, 2007
    Publication date: January 24, 2008
    Applicant: SUMCO CORPORATION
    Inventors: Hidehiko Okuda, Tatsumi Kusaba
  • Patent number: 7315069
    Abstract: An integrated getter structure and a method for its formation and installation in a circuit module enclosure (24). The integrated structure includes a hydrogen getter structure (10) and selected quantities of a material (20) that is formulated to provide both a particle getter function and an RF absorber function. In one embodiment, the material (20) is placed in discrete quantities over the hydrogen getter structure (10). In another embodiment, the hydrogen getter structure (10) is formed over a sheet of the material (20) and is provided with apertures (30) to expose the material (20).
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: January 1, 2008
    Assignee: Northrop Grumman Corporation
    Inventors: Dean Tran, Jerry T. Fang, Yoshio Saito, Mark Kintis, Chih Chang, Phu H. Tran
  • Patent number: 7303943
    Abstract: In a method of manufacturing an electric device, moisture in a film substrate is reduced by heating the film substrate at a temperature in the range of 80° C. to 100° C. Thereafter, an IC is mounted on the film substrate.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: December 4, 2007
    Assignees: Seiko Instruments Inc, Toray Advanced Film Co., Ltd., Maruwa Corporation
    Inventors: Tsutomu Matsuhira, Hideaki Adachi, Keiichiro Hayashi, Tadahiro Nishigawa, Nobukazu Koizumi
  • Patent number: 7279362
    Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: October 9, 2007
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Daoqiang Lu, Christopher L. Rumer, Paul A. Koning, Darcy E. Fleming, Gudbjorg H. Oskarsdottir, Tiffany Byrne
  • Patent number: 7264998
    Abstract: In an unnecessary matter removal method of joining a separation tape onto a semiconductor wafer and, then, separating the separation tape from the semiconductor wafer, thereby separating an unnecessary matter on the semiconductor wafer together with the separation tape, the separation tape is separated from the semiconductor wafer in such a manner that an edge member is brought into contact with the separation tape joined to the semiconductor wafer, and a tip end of the edge member is pressed to the semiconductor wafer at a separation completion end portion where the unnecessary matter is separated from the wafer.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: September 4, 2007
    Assignee: Nitto Denko Corporation
    Inventor: Masayuki Yamamoto
  • Patent number: 7253027
    Abstract: A method of manufacturing a hybrid integrated circuit device includes the steps of forming a plurality of units each including a conductive pattern on a surface of a board made of metal, forming grooves along boundaries of the respective units of the board, electrically connecting circuit elements to the conductive patterns in the respective units, separating the respective circuit boards by dividing the board along the grooves, and flattening side surfaces of the circuit boards by pressing the side surfaces.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: August 7, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Masaru Kanakubo
  • Patent number: 7250324
    Abstract: A method for manufacturing an image sensor includes the steps of: providing a substrate having an upper surface and a lower surface; mounting a frame layer on the upper surface of the substrate to form a cavity together with the substrate; mounting a photosensitive chip, which is formed with a plurality of bonding pads, to the upper surface of the substrate, the photosensitive chip being located within the cavity; providing a plurality of wires to electrically connect the bonding pads of the photosensitive chip to the substrate; supplying an adhesive medium to the cavity; placing a transparent layer on the frame layer to cover the photosensitive chip so as to form the image sensor; and rotating the image sensor to make the adhesive medium be uniformly distributed over the upper surface of the substrate so that particles within the cavity are adhered to the adhesive medium.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: July 31, 2007
    Assignee: Kingpak Technology Inc.
    Inventors: Jackson Hsieh, Jichen Wu
  • Patent number: 7235427
    Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: June 26, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Thierry Barge, Bruno Ghyselen, Toshiaki Iwamatsu, Hideki Naruoka, Junichiro Furihata, Kiyoshi Mitani
  • Patent number: 7205179
    Abstract: A hydrogen diffusion port for use in a packaged electronic device. In one embodiment, the hydrogen window is characterized by a substantial absence of plating from the external surfaces of the cover the base. The hydrogen diffusion port is selected from the group of materials consisting of palladium and its alloys, platinum and its alloys and titanium and its alloys The cover is welded to the base, and the hydrogen diffusion port is affixed to an aperture in the cover. The port is affixed by a low temperature process that can be accomplished after the cover is attached to the base to form a housing and the housing is degassed, without compromising the electronics within the housing and that does not require a partial pressure of hydrogen (which may be reintroduced into the materials) to accomplish, such as by soldering the diffusion port into the cover aperture, or by swaging the diffusion port into the cover aperture.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: April 17, 2007
    Assignee: The Boeing Company
    Inventors: Robert D. Evans, David Bronson
  • Patent number: 7186587
    Abstract: A singulation method used in a process for making a plurality of image sensor packages is disclosed. Firstly, a semi-finished product including a plurality of package structures formed on a substrate is placed on a support having a plurality of cavities for receiving the package structures. Then, the semi-finished product is sawed into separate image sensor packages. During the sawing step, the air pressure in the cavities is decreased to create suction within the cavities such that the support abuts against at least a portion of the housing of each package structure with a gap between the transparent component and the support whereby the package structures are positioned precisely and clamped in place with the support during the sawing step.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: March 6, 2007
    Assignee: Advanced Semiconductor Engineering
    Inventors: JunYoung Yang, InHo Kim
  • Patent number: 7148084
    Abstract: A radiation shielded and packaged integrated circuit semiconductor device includes a lid secured to a base to enclose an integrated circuit die within, wherein the lid and the base are each constructed from a high Z material to prevent radiation from penetrating therethrough. Another embodiment includes a die attach slug constructed from a high Z material disposed between the integrated circuit die and the base, in combination with a high Z material lid to substantially block incident radiation.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: December 12, 2006
    Assignee: Maxwell Technologies, Inc.
    Inventors: David J. Strobel, David R. Czajkowski
  • Patent number: 7141451
    Abstract: A highly reliable inexpensive RFID medium (Radio-frequency Identification medium) and a method of manufacturing the same is provided, particularly for small, thin RFID mediums. A RFID medium includes a transmitting/receiving antenna 2 and an IC chip 3. A rectangular part of a base sheet 1, having a major surface on which transmitting/receiving antennas 2 are formed, is folded along one of the long sides thereof, and the other three sides are bonded to the base sheet 1 so as to cover the transmitting/receiving antenna 2 and the IC chip 3 connected to the transmitting/receiving antenna 2. The base sheet 1 has spacing parts of a predetermined shape for covering the transmitting/receiving antenna 2 and the IC chip 3 connected to the transmitting/receiving antenna 2. The transmitting/receiving antennas 2 and the spacing parts 22 are arranged alternately. The base sheet 1 is rolled in a roll.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: November 28, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Shigeharu Tsunoda, Naoya Kanda
  • Patent number: 7087465
    Abstract: A semiconductor light emitting device is packaged by forming a sealed compartment enclosing the device, at least one of the walls of the sealed compartment being formed of an elastomeric material. The elastomeric material is then penetrated with a needle and a quantity of softer material is injected through the needle into the sealed compartment. In some embodiments, a coaxial needle or two needles are used, one needle to inject the softer material and one needle to vent air from the compartment.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: August 8, 2006
    Assignee: Philips Lumileds Lighting Company, LLC
    Inventor: William D. Collins, III
  • Patent number: 7087456
    Abstract: A method of releasing a micro-electronic device formed over an insulator of a silicon-on-insulator (SOI) substrate. In one embodiment, the release method includes etching at least a portion of the insulator to separate the micro-electronic device from the SOI substrate, rinsing at least the micro-electronic device, exposing at least the micro-electronic device to a micro-sphere solution and removing the micro-electronic device from the SOI substrate. The release method may also include exposing the micro-electronic device to an etching plasma to substantially expunge the micro-sphere solution.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: August 8, 2006
    Assignee: Zyvex Corporation
    Inventors: Igor Gory, Bruce Gnade, Fadziso Mantiziba
  • Patent number: 7087496
    Abstract: The present invention is directed to a seal structure and a method for forming a seal structure for a semiconductor die. An elongate region which is electrically isolated from the remainder of the substrate, such as a well region of a conductivity type opposite that of the substrate, extends around the major portion of the periphery of the substrate. A gap is left between the two ends of the elongate region along the minor portion of the periphery of the substrate not covered by the elongate region. A conductive seal ring is formed around the periphery of the substrate at the elongate region and spans the gap between the ends of the elongate region. The substrate of the semiconductor die is only brought into electrical contact with the seal ring at the gap between the ends of the elongate region.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: August 8, 2006
    Assignee: Broadcom Corporation
    Inventor: German Gutierrez
  • Patent number: 7084010
    Abstract: A radiation detector (10) has a base (30), a frame (48), a window (46), and solder layers (50, 52) formed from a solder pre-form (58, 60) to define a vacuum chamber (56). Feedthroughs (18, 40, 44) penetrate the base (30) for electrical connection to internal components. A method for sealing the detector (10) aligns a lower detector assembly (62), the frame (48) the window (46), and the solder pre-forms (58, 60) in a non-sealed relation within a processing chamber (80, 94). High temperature and low pressure is imposed, and the getter (42) is activated by resistive heating imposed by current leads (88). The window (46), frame (48), and lower detector assembly (62) are then pressed together and sealed by the liquefied solder pre-forms (58, 60). The method eliminates the need for a seal port, combines several steps within the processing chamber (80, 94), and eliminates certain prior art cleaning steps.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: August 1, 2006
    Assignee: Raytheon Company
    Inventors: Adam M. Kennedy, Michael Bailey, Edward Meissner, Robert K. Dodds, David VanLue