Abstract: A dicing tape is adhered to the lower surface of a silicon wafer that has pillar-shaped electrodes. The silicon wafer is cut along dicing streets, thereby making trenches among the chip-forming regions of the wafer. Next, a seal film is formed. The seal film is cut, substantially along the centerlines of the trenches. A support tape is adhered to the upper surface of the seal film. The dicing tape is peeled off. Then, those parts of the seal film that project from the lower surface of the silicon wafer are polished and removed. The support tape is peeled off. IC chips are thereby obtained. In each IC chip, the seal film covers and protects the upper surface and sides of the semiconductor substrate.

Abstract: Methods for finishing or refurbishing surfaces on protective covers encapsulating microelectronic dies. In one embodiment, a method for fishing a surface of a protective package on a microelectronic device includes abrading the surface of the package by engaging an abrasive media with the surface of the package, terminating the abrasion when a surface blemish has been at least partially removed from the package, and cleaning residual materials from the package after terminating the abrasion of the package surface. The abrasive media can include a fixed-abrasive member, a fixed-abrasive member and a solution, a non-abrasive member and a chemical solution having abrasive particles, or an abrasive blasting media.

Abstract: A semiconductor device comprising a substrate including a metal portion and a resin portion and having a plurality of through holes formed in the resin portion, conductive members formed within the through holes, a semiconductor chip attached to one surface of the substrate, and a plurality of solder balls attached to the other surface of the substrate. The semiconductor chip and solder balls are electrically connected through the conductive members.

Abstract: The present invention teaches a sawn wafer with ultra clean bonding pads on die which enhance the strength of wire bond and results in higher yield and improved reliability of packaged semiconductor die. Clean wafers ready for dicing are coated with a removable insulating water soluble non-ionic film which enhances clean saw cuts and reduces buildup. The protective film is hardened by heat and resists removal by cooling water used in dicing saws. However, after dicing the protective film is removable in a wafer washer using high pressure warm D.I. water. After removal of the protective film the electrode pads are virtually as clean as before dicing. The film may be used as a protective layer until the sawn wafer is ready for use.

Abstract: A plasma-processing apparatus providing a resin mold domed enough to allow no bonding wires to be exposed is presented. The plasma-processing apparatus cleans a board including a chip mounted thereon and a disposing area for a pad formed around the chip. The apparatus includes a chamber for accommodating the board; an electrode mounted to the chamber for generating plasma in the chamber with a voltage applied thereto, a table for supporting the board in the chamber, and a masking member which is provided above the board. The masking member has an opening for exposing the chip and the disposing area to the plasma.

Abstract: CTE differentials between chips and organic dielectric carriers, boards or other substrates to which the chips are attached are accommodated with a layer of a thermoplastic material, preferably a thermotropic polymer whose physical properties can be altered by extrusion or other physical processes, such as liquid crystalline polyesters, that modifies the CTE of at least one component of the package and thereby reduces CTE differentials. The material may be applied to the entire surface of a chip carrier, printed circuit or other substrate, or form an interior layer of a multi-layered structure. It may also be applied to selected regions or areas on the surface of a carrier or other substrate where adjustment is required.

Abstract: A method of manufacturing a semiconductor device. The method includes the steps of: providing a lead frame assembly with joined first and second unit lead frames, with the first unit lead frame having a first support and a plurality of leads and the second unit lead frame having a second support and a plurality of leads; mounting operating components on the first and second unit lead frames; applying a sealing composition over the lead frame assembly and the operating components to define a semiconductor preassembly; cutting the semiconductor preassembly so as to define first and second semiconductor devices, with the first and second semiconductor devices having first and second exposed edges respectively defined by cutting of the semiconductor preassembly; and moving at least the first semiconductor device against another element to break loose flash on the first exposed edge.

Abstract: Particles are removed from the surface of a substrate. Respective position coordinates of the particles on the surface are determined. A beam of electromagnetic energy is directed at the coordinates of each of the particles in turn, such that absorption of the electromagnetic energy at the surface causes the particles to be dislodged from the surface substantially without damage to the surface itself.

Abstract: This invention is related to a method for encapsulating bond regions in electronic components comprising, for example, metallic bond regions, the method comprising the steps of exposing an electronic component having at least one bond region through a primary gas atmosphere comprising unstable or excited gaseous species, the gaseous species being substantially devoid of any electrical charges, the primary gas atmosphere having a pressure ranging from about 0.5×105 Pa to about 3.0×105 Pa, thereby forming a treated, non-encapulated electronic component, then encapsulating the electronic component.

Abstract: A method of using adhesive tape to temporarily retain a die being temporarily held in a fixture during testing and burn-in. The method of the present invention uses a die cut piece of adhesively coated tape to hold a die in a test and burn-in fixture. Upon subsequent heating of the tape beyond the normal operating range of the adhesive coating on the tape, the die is removed from the tape, the tape is removed from the test and burn-in fixture, and the remaining adhesive, if any, is removed from the test and burn-in fixture.

Abstract: An electronic device that is sealed under vacuum includes a substrate, a transistor formed on the substrate, and a dielectric layer covering at least a portion of the transistor. The electronic device further includes a layer of non-evaporable getter material disposed on a portion of the dielectric layer; and a vacuum device disposed on a portion of the substrate. Electrical power pulses activate the non-evaporable getter material.

Abstract: In a method for handling in parallel a plurality of circuit chips, which are arranged in a first arrangement, which corresponds to their arrangement in the original wafer, on the surface of an auxiliary carrier, the plurality of circuit chips is picked up by a plurality of pick up devices. The plurality of pick up devices with the picked up circuit chips is moved simultaneously to one or several carriers, in such a way that, simultaneously with the motion, the first arrangement of the circuit chips is changed into a second arrangement, which is different from the first arrangement. Then the circuit chips are simultaneously placed in the second arrangement on the one or several carriers.

Abstract: A boat is formed with a plurality of through-holes sized to securely maintain ceramic or organic flip chip semiconductor packages in place during assembly. Embodiments comprises a boat having a bottom layer with an array of four-sided through-holes and a top layer with an array of through-holes and tabs extending from the sides of the through-hole. Embodiments further include a boat having a bottom layer with through-holes smaller than substantially aligned overlying through-holes in the top layer, the substantially aligned through-holes forming flip chip package holding pockets. An alignment mechanism ensures that components are accurately positioned on flip chip packages held in the boat during assembly.

Abstract: As a preparation process, a gas supply source 10A supplies WF6 gas for restricting formation of nuclei for growing a metal film onto a surface of a process target semiconductor wafer W for a predetermined period of time. After the preparation process is performed, the gas supply source 10A and a gas supply source 10B respectively supply WF6 gas and NH3 gas onto the surface of the semiconductor wafer W to which the preparation process has been applied, for a predetermined period of time. Thus, a tungsten nitride film which is a metal compound film whose surface has bumps is formed on the semiconductor wafer W. A controller 51 controls operations of the gas supply sources 10A and 10B, and the like in accordance with a program or the like previously provided.

Abstract: Wafer preparation systems and methods for wafer preparation are provided. The wafer preparation system includes a scrubber unit and a dryer unit arranged vertically with the dryer unit above the scrubber unit. The scrubber unit is configured to receive a wafer for mechanical scrub cleaning, and the dryer unit is configured to receive the wafer from the scrubber unit for drying after the mechanical scrub cleaning. The cleaning and the drying are accomplished with the wafer in a vertical orientation. An edge holder attached to a lifter rod lifts the wafer through the scrubber unit to the dryer unit. The method for wafer preparation includes receiving a wafer in a scrubbing station and lifting the wafer internally from the scrubbing station to the drying station that is located above the scrubbing station in a vertical arrangement.

Abstract: A semiconductor substrate is coupled to the upper side of a base. After the semiconductor substrate is processed, a lid material is anode-coupled to the semiconductor substrate. For the anode-coupling, first, the semiconductor substrate and the lid material are anode-coupled in a spot pattern. After this, the semiconductor substrate and the lid material are wholly anode-coupled to each other. Thereafter, the laminate including the base, the semiconductor substrate, and the lid material are divided and separated into predetermined individual areas. Thus, a vacuum container having a vacuum cavity formed inside of the laminate including the base layer, the semiconductor layer, and the lid layer can be formed. The vacuum degree of the vacuum cavity of the vacuum container is considerably enhanced compared to that by a conventional process of producing a vacuum container. In addition, scattering of the vacuum degrees of the vacuum cavities can be suppressed.

Abstract: This invention is related to a method for encapsulating bond regions in electronic components comprising, for example, metallic bond regions, the method comprising the steps of exposing an electronic component having at least one bond region through a primary gas atmosphere comprising unstable or excited gaseous species, the gaseous species being substantially devoid of any electrical charges, the primary gas atmosphere having a pressure ranging from about 0.5×105 Pa to about 3.0×105 Pa, thereby forming a treated, non-encapulated electronic component, then encapsulating the electronic component.

Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is rotated during the second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.

Abstract: A method of producing a semiconductor device is described. The semiconductor device has a semiconductor chip with wiring terminals, conductor tracks for the electrical connection of the semiconductor chip, and a component of a housing configuration that contains organic, silicon-containing material. For this purpose, the semiconductor chip is applied to the component of the housing configuration and permanently connected to it. The conductor tracks and/or the wiring terminals are subsequently subjected to a cleaning process, in which silicon-containing material adhering to a surface is eliminated. The conductor tracks are subsequently connected in an electrically conducting manner to the wiring terminals. The contact quality of these electrical connections is noticeably improved by the cleaning process provided.

Abstract: Disclosed are hydrogen gettering structure (11) and use of such structure and methods of forming such structure. The hydrogen gettering structure (11) includes a titanium member (1) and a silver-doped palladium layer (3) on the titanium member (1), the silver assisting palladium to increase the hydrogen gettering. The silver-doped palladium can be deposited on the titanium member by sputtering. The hydrogen gettering structure (11) can be attached to a semiconductor module component (7) and incorporated in a semiconductor module (10) to increase hydrogen gettering, or can be included in other structure (e.g., nuclear reactor structure) where absorption or gettering of hydrogen is necessary or desired.

Abstract: A hermetically cold weld sealed package and method for sealing where a metal seal member 28 is placed along the edge of a base 36, an organic sealant 26 is placed along the outside of the base adjacent the metal seal member 28, and a lid 30 is placed over the base 36 to create a hermetically sealed cavity 46. The process takes place at room temperature environment in an inert environment, and on heating of the metal sealing member 28 is required. The shrinkage of the organic sealant 26 during curing applies pressure to the metal seal member 28, enhancing the effectiveness of the hermetic seal.

Abstract: An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

Abstract: The present invention is a method for cleaning the cavities in electronic components by providing a semiconductor component having an outside surface and a cavity therein. The component including hole in the outside surface enabling fluid flow in to or out of the cavity. The component is immersed in a solvent bath where solvent is flowed into the cavity using the hole, the solvent cleaning the cavity and then optionally being evacuated from the cavity. Specifically, the principles of the present invention may be used to clean the underfill space of a flip-chip package. The flip-chip package includes a packaging substrate with an evacuation port passing through the bulk of the packaging substrate such that the port is in communication with the underfill space and a bottom surface with the packaging substrate. This assembly is immersed in a solvent filled solvent bath. Solvent is drawn into the underfill space through said port. Alternatively, solvent may be injected into the underfill space through the port.

Abstract: A sealing device to be inserted between a unit-side connection surface and a block-side connection surface, and providing a sealing performance therebetween, includes a first connection surface configured to be suitable to a first sealing feature of the unit-side connection surface, and a second connection surface configured to be suitable to a second sealing feature of the block-side connection surface. The first sealing feature being different from the second sealing feature.

Abstract: A method of manufacturing a semiconductor device which includes a semiconductor chip and a plastic package of a thermosetting polymer, including the steps of performing an ultraviolet cleaning process on the bottom surface of the semiconductor chip and, encapsulating the semiconductor chip through a molding process. The thermosetting polymer of the plastic package fully or partially covers the bottom surface of the semiconductor chip.

Abstract: A method is disclosed for pre-release plastic packaging of MEMS and IMEMS devices. The method can include encapsulating the MEMS device in a transfer molded plastic package. Next, a perforation can be made in the package to provide access to the MEMS elements. The non-ablative material removal process can include wet etching, dry etching, mechanical machining, water jet cutting, and ultrasonic machining, or any combination thereof. Finally, the MEMS elements can be released by using either a wet etching or dry plasma etching process. The MEMS elements can be protected with a parylene protective coating. After releasing the MEMS elements, an anti-stiction coating can be applied. The perforating step can be applied to both sides of the device or package. A cover lid can be attached to the face of the package after releasing any MEMS elements. The cover lid can include a window for providing optical access.

Abstract: A method is described for removing a particle from a surface of a semiconductor wafer. In general, the method involves positioning an electrically conductive surface near the particle to be removed. An electrical charge is created on the electrically conductive surface. A charged particle beam is formed, wherein the charged particle beam includes particles having an electrical charge opposite the electrical charge of the electrically conductive surface. The charged particle beam is directed at the particle to be removed. When struck by the charged particle beam, the particle to be removed absorbs a portion of the charged particles of the charged particle beam and acquires an electrical charge opposite the electrical charge of the electrically conductive surface.

Abstract: A micromachined accelerometer is hermetically sealed in a reduced oxygen environment to allow organics to survive high temperature sealing processes.

Abstract: A mounting structure includes a laminated ceramic capacitor mounted on a mounting substrate. The laminated ceramic capacitor includes a main body chip made by a ceramic dielectric, internal layer electrodes, and pair of terminal electrodes. The mounting substrate is made by alumina substrate, and has a pair of substrate electrodes made by copper plating. The laminated ceramic capacitor is mounted on the mounting substrate by using an Ag paste. Here, the substrate electrode is set to be smaller than the Ag paste. That is, the Ag paste is extruded from the terminal electrodes and the substrate electrode so as to contact to both of the main body chip and the mounting substrate. Because the Ag paste has a high adhesive strength compared to that when it is bonded with a metal, total adhesive strength can be improved. Consequently, the reliability of mounting can be improved.

Abstract: A manufacturing system compares information of foreign matter sensed by semiconductor equipment from on a semiconductor substrate with a selection reference thereby selecting optimum semiconductor equipment corresponding to the information of the foreign matter from a plurality of semiconductor equipment and processing the semiconductor substrate. Thus, a method of manufacturing a semiconductor device capable of improving the yield of the semiconductor device as well as a manufacturing system and semiconductor equipment to which the manufacturing method is applied, and a semiconductor device manufactured by the same are obtained.

Abstract: A chip carrier and lid are sealed by mounting the chip carrier in an inverted position and mounting a lid having a sealing preform in an inverted position beneath and facing the chip carrier. The chip carrier and lid are then heated to melt the sealing preform and the chip carrier and lid are moved together to join them at the sealing preform.

Abstract: A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.

Abstract: A method of protecting an electronic component from damage, wherein the electronic component includes a semiconductor chip. According to the method, a first protective substance is applied to an outer surface of the semiconductor chip. The first protective substance has a coefficient of thermal expansion substantially similar to the coefficient of thermal expansion of the semiconductor chip. A second substance may then applied to an outer surface of the first protective substance. The first protective substance is applied such that it protects the semiconductor chip from damage during the application of the second substance.

Abstract: A method and apparatus for collecting defect includes forming a defect collecting structure on a wafer such that any residue defects tend to settle on the defect collecting structure instead of the circuit patterns. The defect collecting structure can be located within the die or on the scribelines between the dies. When the defect collecting structure is located in a die, it should have dimensions significantly larger than the dimensions of the surrounding circuits patterns. The defect collecting structure can include a plurality of defect collecting structures. The defect collecting structures can be contiguous or non-contiguous. The defect collecting structure(s) can occupy one hundredth of one percent of the die or more. The defect collecting structures can be created on a wafer by coating, exposing, developing, and optionally, detecting defects. The wafer is exposed with a mask that includes a pattern for the defect collecting structure(s).

Abstract: A chip carrier and lid are sealed by mounting the chip carrier in an inverted position and mounting a lid having a sealing preform in an inverted position beneath and facing the chip carrier. The chip carrier and lid are then heated to melt the sealing preform and the chip carrier and lid are moved together to join them at the sealing preform.

Abstract: A method of producing a semiconductor device is described. The semiconductor device has a semiconductor chip with wiring terminals, conductor tracks for the electrical connection of the semiconductor chip, and a component of a housing configuration that contains organic, silicon-containing material. For this purpose, the semiconductor chip is applied to the component of the housing configuration and permanently connected to it. The conductor tracks and/or the wiring terminals are subsequently subjected to a cleaning process, in which silicon-containing material adhering to a surface is eliminated. The conductor tracks are subsequently connected in an electrically conducting manner to the wiring terminals. The contact quality of these electrical connections is noticeably improved by the cleaning process provided.

Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.

Abstract: The specification describes wafer fabrication cleaning processes for silicon optical bench technology. The cleaning processes are designed to remove debris in situ after dicing silicon wafers mounted on a tape carrier. They were also developed specifically to avoid staining and residues that often result from using standard dicing approaches in silicon optical bench integrated circuit manufacture.

Abstract: The invention offers a solution to several problems associated wit IC packages that use a top layer of molded plastic. This has been achieved by inter-posing a dummy layer of dielectric material between the upper surface of the integrated circuit wafer and the molded plastic layer. This dummy layer is patterned and etched so that its surface becomes an alternating series of valleys and ridges, care being taken to ensure that all wiring lines are protected by being within ridges. This structure serves both to protect the wiring lines during the application of the molded plastic and, because of the large surface area of contact between plastic and wafer, excellent adhesion of the molded plastic to the wafer is obtained.

Abstract: The number of elements, an element area, an inter-element wiring region, and the minimum necessary power supply wiring layer region are estimated, and a chip area and a chip region are determined on the basis of the estimation result. Elements are arranged in the chip region, and wirings for connecting the elements to each other are formed. Thereafter, the shapes of the power supply wiring layer and the ground wiring layer connected to the elements and oppositely arranged to be spaced apart from each other in the direction of the thickness of the chip are determined. The power supply wiring layer and the ground wiring layer are designed such that the counter area therebetween is made as large as possible.

Abstract: There is provided a method for fabricating semiconductor devices including resin packages sealing semiconductor elements and external connection terminals respectively resin projections formed on the resin packages and metallic film parts provided to the resin projections. The semiconductor elements are mounted to a lead frame having recess portions located in positions corresponding to positions of the resin projections, metallic film parts being provided in the recess portions. The semiconductor elements are electrically connected to the metallic film parts. The resin packages that seal the semiconductor elements and gate portions are integrally formed with the resin packages. The lead frame is etched so that the resin packages are separated from the lead frame together with the metallic layer parts. The resin packages are attached to an adhesive tape provided to a frame and being used as a carrier.

Abstract: A method for soldering a first component having a metal surface to a second component having a metal surface includes holding the metal surface of the first component in a position above a placement area on the metal surface of the second component to establish a gap between the surfaces. The method further includes reflowing solder within the gap. A structure including a thermally conductive baseplate, an electrical insulator attached to the baseplate, and a metallic shield mounted on the insulator. The structure also includes an integrated power device having a power-dissipating electronic device, and a first metal layer connected to the shield through a solder joint. A substrate includes an aperture, and the integrated power device is mounted with the power-dissipating device sitting within the aperture. The substrate also includes a conductive run electrically connected to a second metal layer of the integrated power device.

Abstract: Apparatus and method of increasing the distance of the gap between a lead frame and a semiconductor die surface in a package assembly. An adhesive layer and a gap increasing layer are disposed between the lead frame and the semiconductor die surface. The gap increasing layer has a thickness selected to reduce likelihood of package particles from being trapped between the lead frame and the die surface. The gap increasing layer includes silver plating, and has a thickness of at least about 300 to 500 microinches.

Abstract: Disclosed are a packaging component for packaging a microelectronic (e.g., III-V semiconductor) device, the packaged microelectronic device formed using such component, and method for forming the package component and packaged microelectronic device. The component (which can be, e.g., a lid or container 21 of the package) has sequentially deposited layers of metal layers (37, 50), to be located within the package, attached to a housing member, to act as a hydrogen getter in the package. The sequentially deposited layers of metal layers includes at least a first layer (3) of Ni adjacent the housing member surface, to improve adherence of the sequentially deposited layers and interstitially trap hydrogen; an outermost layer (11) of palladium to convert molecular hydrogen to hydrogen atoms and as the primary absorber of the hydrogen; and a layer (9) of Ti or Zr adjacent this outermost layer and acting as a secondary absorber of the hydrogen.

Abstract: An electronic circuit device fabrication method securing a bond width of a seal portion when heat treatment is needed in sealing a device cavity by a cap. An electronic part mounting step is executed to secure electronic parts, including a semiconductor acceleration sensor chip, within a package main body by using a silicone group die bonding material and a silicone group silver paste. At a baking step, the package main body mounted with the electronic part is heated to a baking temperature of about 380.degree. C..+-.5.degree. C. In a sealing step, the package main body and the cap are bonded by a sealing material by executing a heat treatment in a state where the sealing material, comprising a low melting point glass, is interposed between a peripheral edge portion of the cavity in the package main body and the cap. The temperature of the package main body is then heated in the heat treatment to about 365.degree. C..+-.5.degree. C., which is lower than the baking temperature at the baking step.

Abstract: An method of separating a slice base mounting member such as a carbon member from sliced wafers, and an jig which is used for treating the wafers in the method, are disclosed. The method of separating a slice base mounting member from sliced wafers comprises the steps of; supporting a plurality of wafers having at least a slice base mounting member in a stacked state, and separating the slice base mounting member from the stacked wafers.

Abstract: A technique for enabling sufficient flow of flux cleaning fluids and an underfill material in the relatively low-profile gap between a flip-chip bonded IC chip and a substrate, such as a printed circuit board, is to provide at least one aperture in the substrate under the IC chip. The use of such an aperture enables, for example, flux cleaning fluid to flow through the aperture into the low-profile gap between the IC chip and the substrate surface, such as by the application of pressure or by gravity, which then exits through openings between formed interconnect bonds at a sufficient flow rate to adequately remove flux residues. An epoxy underfill to the IC chip can be formed in a similar manner. For example, a relatively thick bead of epoxy, such as on the order of the thickness of the IC chip, is deposited or stencil printed on the substrate surface around the edges of the IC chip and capillary action is then relied upon to draw the epoxy into the low-profile gap.

Abstract: A surface treatment method for bonding pad is described, in which a passivation layer is formed on a bonding pad and an opening is formed within the passivation by a plasma etching process. The bonding pad is corroded by the etching plasma containing fluorine during the etching process. The bonding pad is rinsed with deionized water comprising carbon dioxide to reduce the effects of the corrosion phenomenon.

Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is rotated during the second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.

Abstract: A process for manufacturing a package of a semiconductor device, and providing a semiconductor device in which a vapor-impermeable moistureproof plate is embedded in a bottom surface of a hollow package or an inner surface wallthicknesswise therefrom to provide moisture-proofness.