Incorporating Resilient Component (e.g., Spring, Etc.) Patents (Class 438/117)
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Patent number: 8689436Abstract: An align fixture for aligning an electronic component having a receptacle adapted to receive the electronic component and having a first abutting section and a second abutting section, the align fixture further having a first elastic unit and a second elastic unit, the first abutting section is flexibly mounted via the first elastic unit, and the second abutting section is flexibly mounted via the second elastic unit, and the first abutting section and the second abutting section are together adapted to floatingly engage the electronic component.Type: GrantFiled: August 17, 2010Date of Patent: April 8, 2014Assignee: Multitest Elektronische Systeme GmbHInventors: Thomas Hofmann, Helmut Scheibenzuber
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Patent number: 8685778Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a lower wiring layer. The method further includes forming a layer. The method further includes forming a second sacrificial cavity layer over the first sacrificial layer and in contact with the layer. The method further includes forming a lid on the second sacrificial cavity layer. The method further includes forming at least one vent hole in the lid, exposing a portion of the second sacrificial cavity layer. The method further includes venting or stripping the second sacrificial cavity layer such that a top surface of the second sacrificial cavity layer is no longer touching a bottom surface of the lid, before venting or stripping the first sacrificial cavity layer thereby forming a first cavity and second cavity, respectively.Type: GrantFiled: December 20, 2010Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Christopher V. Jahnes, Anthony K. Stamper
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Patent number: 8658911Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.Type: GrantFiled: April 17, 2012Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Moises Cases, Tae Hong Kim, Rohan U. Mandrekar, Nusrat I. Sherali
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Publication number: 20140027890Abstract: A package that electrically connects an integrated circuit to a printed circuit board includes a frame and a package body that encases a portion of the frame and the integrated circuit. The frame includes a mounting region that is connected to the printed circuit board, and a cantilevering region that cantilevers away from the mounting region. The cantilevering region retains the integrated circuit in a flexible fashion.Type: ApplicationFiled: July 27, 2013Publication date: January 30, 2014Applicant: Integrated Device Technology Inc.Inventor: Ajay K. Ghai
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Publication number: 20140030852Abstract: An integrated electromagnetic interference (EMI) shield for a semiconductor module package. The integrated EMI shield includes a plurality of wirebond springs electrically connected between a ground plane in the substrate of the package and a conductive layer printed on the top of the package mold compound. The wirebond springs have a defined shape that causes a spring effect to provide contact electrical connection between the tops of the wirebond springs and the conductive layer. The wirebond springs can be positioned anywhere in the module package, around all or some of the devices included in the package, to create a complete EMI shield around those devices.Type: ApplicationFiled: January 14, 2013Publication date: January 30, 2014Applicant: SKYWORKS SOLUTIONS, INC.Inventor: SKYWORKS SOLUTIONS, INC.
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Patent number: 8637789Abstract: The present invention relates to a process for producing a metallized textile surface having one or more articles needing or generating electric current. A formulation having at least one metal powder is applied as a component atop a textile surface patternedly or uniformly. At least one article needing or generating electric current is fixed in at least two locations where formulation was applied. A further metal is deposited on the textile surface.Type: GrantFiled: February 19, 2008Date of Patent: January 28, 2014Assignee: BASF SEInventors: Rene Lochtman, Norbert Wagner, Jürgen Kaczun, Jürgen Pfister, Antonino Raffaele Addamo, Ralf Nörenberg
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Patent number: 8614514Abstract: Standard ribbon bonds are utilized as clamp-like mechanical fasteners to attach an IC die in a “flip-chip” orientation to a support structure (e.g., a package base substrate or printed circuit board). Electrical connections between the support structure and the IC die are achieved by curved micro-springs that extend through an air-gap region separating the upper structure surface and the active surface of the IC die. The micro-springs have an anchor portion fixedly attached to one of the support structure and the IC die, and a free (tip) end that is in nonattached contact with an associated contact pad disposed on the other of the support structure and the IC die. Once the IC die is placed on the support structure, the ribbon bonds are formed between the support structure and the IC die using conventional wedge bonder, but the ribbon bonds connected to the non-active surface of the IC die.Type: GrantFiled: March 13, 2013Date of Patent: December 24, 2013Assignee: Palo Alto Research Center IncorporatedInventors: Vernon Powers, Eugene M. Chow
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Patent number: 8610265Abstract: An electrical interconnect for providing a temporary interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the conductive traces into the openings. Conductive structures are electrically coupled to the conductive traces over the openings. The conductive structures are adapted to enhance electrical coupling with the terminals on the IC device. Vias electrically extending through the substrate couple the conductive traces to PCB terminals located proximate a second surface of the substrate.Type: GrantFiled: April 17, 2012Date of Patent: December 17, 2013Assignee: Hsio Technologies, LLCInventor: James Rathburn
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Patent number: 8604609Abstract: A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.Type: GrantFiled: October 18, 2012Date of Patent: December 10, 2013Assignee: Infineon Technologies AGInventors: Anwar A. Mohammed, Soon Ing Chew, Donald Fowlkes, Alexander Komposch, Benjamin Pain-Fong Law, Michael Opiz Real
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Patent number: 8592946Abstract: An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed parallel to each of the two facets joined by the ridge causing damage to implanted portions of the masking material layer, which are removed selective to undamaged portions of the masking material layer along the ridge and having a constant width. The semiconductor layer and a dielectric oxide layer underneath are etched selective to the remaining portions of the dielectric nitride. Employing remaining portions of the dielectric oxide layer as an etch mask, the gate conductor layer is patterned to form gate conductor lines having a constant width.Type: GrantFiled: March 14, 2011Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventor: Huilong Zhu
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Patent number: 8581422Abstract: A semiconductor module includes a semiconductor device, a first conductive member, a second conductive member, a cylinder, and a cover. The first conductive member is in contact with a first electrode of the semiconductor device. The second conductive member is in contact with a second electrode of the semiconductor device. The cylinder encompasses the semiconductor device and is fixed to the first conductive member, and a first thread groove is formed on the cylinder. A second thread groove is formed on the cover. The cover is fixed to the cylinder by an engagement of the second thread groove with the first thread groove. The semiconductor device and the second conductive member are fixed by being sandwiched between the first conductive member and the cover. The second conductive member includes a portion extending from inside to outside the cylinder by penetrating an outer peripheral wall of the cylinder.Type: GrantFiled: September 12, 2012Date of Patent: November 12, 2013Assignee: Toyota Jidosha Kabushiki KaishaInventor: Masaki Aoshima
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Patent number: 8581378Abstract: Terminals (2b, 2c) are divided into two along a common boundary, coatings (10, 11) most suitable for two conductive bonding materials (5, 6) to be used are exposed on the terminals (2b, 2c), the most suitable one of the coatings (10, 11) is selected, and the corresponding conductive bonding material (5, 6) is bonded onto the coating. Thus it is possible to improve the reliability of bonding and easily reduce a bonding resistance while suppressing a decrease in the reliability of a semiconductor element 3.Type: GrantFiled: September 29, 2009Date of Patent: November 12, 2013Assignee: Panasonic CorporationInventors: Toshiyuki Yokoe, Chie Fujioka, Daichi Kumano
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Patent number: 8575954Abstract: Based upon a layout of a semiconductor wafer comprising a plurality of integrated circuits at pre-defined locations, each integrated circuit comprising a set of electrical connection pads, a probe chip contactor is established, having a unit standard cell on the probe side of the probe chip to correspond to each of the arranged integrated circuits. The unit standard cell is stepped and repeated for the probe side of the probe chip contactor, to establish a wafer scale standard cell layout. The opposite contact side of the probe chip contactor is connectable to a central structure, e.g. a Z-block or PC board, typically comprising a fixed array of vias with fixed X, Y, and Z locations. The routing of contact side of the probe chip contactor is preferably routed automatically, such as implemented on one or more computers, to provide electrical connections between the substrate through vias and the Z-block through vias.Type: GrantFiled: January 31, 2008Date of Patent: November 5, 2013Assignee: Advantest (Singapore) Pte LtdInventors: Fu Chiung Chong, William R. Bottoms, Erh-Kong Chieh, Nim Cho Lam
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Patent number: 8571405Abstract: A silicon MEMS device can have at least one solder contact formed thereupon. The silicon MEMS device can be configured to be mounted to a circuit board via the solder contact(s). The silicon MEMS device can be configured to be electrically connected to the circuit board via the solder contact(s).Type: GrantFiled: September 28, 2011Date of Patent: October 29, 2013Assignee: DigitalOptics Corporation MEMSInventor: Roman C. Gutierrez
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Patent number: 8564117Abstract: The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.Type: GrantFiled: April 9, 2012Date of Patent: October 22, 2013Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.Inventors: Sang Won Yoon, Koji Shiozaki
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Patent number: 8531042Abstract: A processing technique facilitating the fabrication of the integrated circuit with microsprings at different vertical positions relative to a surface of a substrate is described. During the fabrication technique, microsprings are lithographically defined on surfaces of a first substrate and a second substrate. Then, a hole is created through a first substrate. Moreover, the integrated circuit may be created by rigidly mechanically coupling the two substrates to each other such that the microsprings on the surface of the second substrate are within a region defined at least in part by an edge around the hole. Subsequently, photoresist that constrains the microsprings on the surfaces of the two substrates may be removed. In this way, microsprings at the different vertical positions can be fabricated.Type: GrantFiled: June 30, 2009Date of Patent: September 10, 2013Assignee: Oracle America, Inc.Inventors: Robert J. Drost, John E. Cunningham, Ashok V. Krishnamoorthy
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Patent number: 8519531Abstract: An electrical and/or electronic device including: an electrical and/or electronic component; two layers of material forming front and back faces of the device and between which the electrical and/or electronic component is encapsulated, the component including at least two opposite faces placed facing the two layers of material; an electrical contact element placed in contact with one of the faces of the electrical and/or electronic component; an element based on at least one elastic material placed between one of the two layers of material and the electrical contact element, forming a first layer of elastic material covering the one of the two layers of material; and a second layer based on at least one elastic material with an elastic stiffness less than the stiffness of the elastic material in the first layer, placed in contact with the first layer of elastic material.Type: GrantFiled: December 14, 2010Date of Patent: August 27, 2013Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Eric Pilat, Alexandre Vachez
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Patent number: 8519524Abstract: A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.Type: GrantFiled: August 16, 2012Date of Patent: August 27, 2013Assignee: Industrial Technology Research InstituteInventors: Sheng-Tsai Wu, John H. Lau, Heng-Chieh Chien, Ra-Min Tain, Ming-Ji Dai, Yu-Lin Chao
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Publication number: 20130194752Abstract: In accordance with an embodiment, a semiconductor package includes a first surface configured to be mounted on a circuit board, and a region of thermally expandable material configured to push the first surface of the semiconductor package away from the circuit board when a temperature of the thermally expandable material exceeds a first temperature.Type: ApplicationFiled: January 30, 2012Publication date: August 1, 2013Applicant: Infineon Technologies AGInventors: Carlo Baterna Marbella, Ganesh Vetrivel Periasamy, Kok Kiat Koo, Ai Min Tan
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Patent number: 8476110Abstract: A storage apparatus including a circuit board, a control circuit element, a terminal module and a storage circuit element is provided. The circuit board includes a first surface, a second surface, a connect part, openings, metal contacts and metal units. The openings pass through the circuit board from the first surface to the second surface and the metal contacts are exposed on the first surface. The terminal module is disposed on the first surface and has elastic terminals and each of the elastic terminals has a first contact part and a second contact part. The first contact parts respectively contact with the metal contacts and the second contact parts respectively pass through the openings to protrude from the second surface. The metal units are disposed on the second surface and located between the openings and the connect part. Accordingly, the volume of the storage apparatus can be reduced.Type: GrantFiled: January 22, 2013Date of Patent: July 2, 2013Assignee: Phison Electronics Corp.Inventors: Wei-Hung Lin, Chun-Feng Lee, Chang-Chih Chen
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Publication number: 20130149816Abstract: To reduce defects of a semiconductor device, such as defects in shape and characteristic due to external stress and electrostatic discharge. To provide a highly reliable semiconductor device. In addition, to increase manufacturing yield of a semiconductor device by reducing the above defects in the manufacturing process. The semiconductor device includes a semiconductor integrated circuit sandwiched by impact resistance layers against external stress and an impact diffusion layer diffusing the impact and a conductive layer covering the semiconductor integrated circuit. With the use of the conductive layer covering the semiconductor integrated circuit, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit can be prevented.Type: ApplicationFiled: February 5, 2013Publication date: June 13, 2013Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: SEMICONDUCTOR ENERGY LABORATORY CO., LTD
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Patent number: 8445327Abstract: A wafer-level packaging process of a light-emitting diode is provided. First, a semiconductor stacked layer is formed on a growth substrate. A plurality of barrier patterns and a plurality of reflective layers are then formed on the semiconductor stacked layer, wherein each reflective layer is surrounded by one of the barrier patterns. A first bonding layer is then formed on the semiconductor stacked layer to cover the barrier patterns and the reflective layers. Thereafter, a carrying substrate having a plurality of second bonding layers and a plurality of conductive plugs electrically insulated from each other is provided, and the first bonding layer is bonded with the second bonding layer. The semiconductor stacked layer is then separated from the growth substrate. Next, the semiconductor stacked layer is patterned to form a plurality of semiconductor stacked patterns. Next, each semiconductor stacked pattern is electrically connected to the conductive plug.Type: GrantFiled: February 23, 2012Date of Patent: May 21, 2013Assignee: Lextar Electronics Corp.Inventors: Chia-En Lee, Cheng-Ta Kuo, Der-Ling Hsia
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Patent number: 8440506Abstract: A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.Type: GrantFiled: July 11, 2012Date of Patent: May 14, 2013Assignee: Intel CorporationInventors: Brent M. Roberts, Mihir K. Roy, Sriram Sriniyasan, Sridhar Narasimhan
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Patent number: 8436429Abstract: A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.Type: GrantFiled: May 29, 2011Date of Patent: May 7, 2013Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Yan Xun Xue, Yueh-Se Ho, Lei Shi, Jun Lu, Liang Zhao
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Patent number: 8431438Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.Type: GrantFiled: April 6, 2010Date of Patent: April 30, 2013Assignee: Intel CorporationInventors: Ravi K Nalla, Mathew J Manusharow
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Patent number: 8404523Abstract: A method for fabricating a stacked semiconductor system with encapsulated through wire interconnects includes providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The method also includes stacking two or more substrates and electrically connecting the through wire interconnects on the substrates.Type: GrantFiled: June 27, 2012Date of Patent: March 26, 2013Assignee: Micron Technoloy, Inc.Inventors: David R. Hembree, Alan G. Wood
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Patent number: 8399966Abstract: Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding compound, proximate a selected surface or surfaces of a semiconductor die or dice during encapsulation are disclosed. Flow diverting structures may be included in or associated with one or more portions of a lead frame, such as a paddle, tie bars, or lead fingers. Flow diverting structures may also be inserted into a mold in association with semiconductor dice carried on non-lead frame substrates, such as interposers and circuit boards, to preferentially impede, redirect or both impede and redirect the flow of molding compound flowing between and over the semiconductor dice.Type: GrantFiled: May 31, 2012Date of Patent: March 19, 2013Assignee: Micron Technology, Inc.Inventor: Stephen L. James
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Patent number: 8399297Abstract: Methods of forming pre-encapsulated frames comprise flowing a dielectric encapsulation material around at least one conductive trace. A cavity configured to receive at least one semiconductor device at least partially in the cavity is formed in the encapsulation material. A first connection area of the at least one trace is exposed within the cavity. At least another connection area of the at least one trace is exposed laterally adjacent to the cavity. The dielectric encapsulation material is hardened to form a pre-encapsulated frame.Type: GrantFiled: October 20, 2011Date of Patent: March 19, 2013Assignee: Micron Technology, Inc.Inventors: Tay Wuu Yean, Wang Ai-Chie
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Patent number: 8399296Abstract: A method of assembling a package includes aligning a pad chip with a spring chip to form at least one interconnect in an interconnect area, adhering the pad chip to the spring chip so that there is a gap between the pad chip and the spring chip, dispensing underfill material into the gap to seal the interconnect area from an environment external to the package, and curing the underfill material to form a solid mold.Type: GrantFiled: October 9, 2011Date of Patent: March 19, 2013Assignee: Palo Alto Research Center IncorporatedInventors: Christopher L. Chua, Bowen Cheng, Eugene M. Chow, Dirk De Bruyker
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Patent number: 8383442Abstract: Methods of anchoring components of a Micro-Electro-Mechanical Systems (MEMS) device to a substrate. An exemplary embodiment has a trace anchor bonded to a substrate, a device anchor bonded to the substrate, and an anchor flexure configured to flexibly couple the trace anchor and the device anchor to substantially prevent transmission of a stress induced in the trace anchor from being transmitted to the device anchor.Type: GrantFiled: September 20, 2011Date of Patent: February 26, 2013Assignee: Honeywell International Inc.Inventors: Michael Foster, Mark Williams, Mark Eskridge
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Publication number: 20130037932Abstract: A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.Type: ApplicationFiled: October 18, 2012Publication date: February 14, 2013Applicant: INFINEON TECHNOLOGIES AGInventor: INFINEON TECHNOLOGIES AG
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Patent number: 8373264Abstract: An integrated electromagnetic interference (EMI) shield for a semiconductor module package. The integrated EMI shield includes a plurality of wirebond springs electrically connected between a ground plane in the substrate of the package and a conductive layer printed on the top of the package mold compound. The wirebond springs have a defined shape that causes a spring effect to provide contact electrical connection between the tops of the wirebond springs and the conductive layer. The wirebond springs can be positioned anywhere in the module package, around all or some of the devices included in the package, to create a complete EMI shield around those devices.Type: GrantFiled: December 2, 2010Date of Patent: February 12, 2013Assignee: Skyworks Solutions, Inc.Inventors: Patrick L. Welch, Yifan Guo
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Patent number: 8318542Abstract: A contact spring applicator is provided which includes an applicator substrate, a removable encapsulating layer and a plurality of contact springs embedded in the removable encapsulating layer. The contact springs are positioned such that a bond pad on each contact spring is adjacent to an upper surface of the removable encapsulating layer. The contact spring applicator may also include an applicator substrate, a release layer, a plurality of unreleased contact springs on the release layer and a bond pad at an anchor end of each contact spring. The contact spring applicators apply contact springs to an integrated circuit chip, die or package or to a probe card by aligning the bond pads with bond pad landings on the receiving device. The bond pads are adhered to the bond pad landings. The encapsulating or release layer is then removed to separate the contact springs from the contact spring applicator substrate.Type: GrantFiled: June 16, 2011Date of Patent: November 27, 2012Assignee: Palo Alto Research Center IncorporatedInventors: Eugene M. Chow, Christopher L. Chua, Eric Peeters
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Patent number: 8314487Abstract: A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.Type: GrantFiled: December 18, 2009Date of Patent: November 20, 2012Assignee: Infineon Technologies AGInventors: Anwar A. Mohammed, Soon Ing Chew, Donald Fowlkes, Alexander Komposch, Benjamin Pain-Fong Law, Michael Opiz Real
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Patent number: 8314444Abstract: A piezoresistive pressure sensor is provided, which can prevent the occurrence of ESD breakdown due to the nearness of interconnection layers of a resistive element according to miniaturization thereof. The piezoresistive pressure sensor is so configured that respective semiconductor resistive layers on both sides of an arrangement are formed to be relatively longer than an adjacent semiconductor resistive layer, and thus a corner portion of a semiconductor connection layer that extends from the respective semiconductor resistive layers on both sides of the arrangement and a corner portion of the semiconductor interconnection layer that is nearest to the corner portion of the semiconductor connection layer, between which the ESD breakdown occurs easily, can be separated from each other.Type: GrantFiled: July 5, 2011Date of Patent: November 20, 2012Assignee: Alps Electric Co., Ltd.Inventors: Shinya Yokoyama, Daigo Aoki, Yutaka Takashima
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Patent number: 8274144Abstract: A first semiconductor package includes a first substrate, a first semiconductor chip attached to the first substrate, an encapsulant which covers the first semiconductor chip, and conductive elastic members which are embedded in the encapsulant but with parts thereof exposed. A package on package (POP) includes the first semiconductor package and a second semiconductor package stacked in the first semiconductor package. The second semiconductor package includes a second substrate and a second semiconductor chip attached to the second substrate. The exposed parts of the elastic members are electrically connected to the second substrate. The encapsulant of the first package is formed by a molding process while the conductive elastic members are compressed within their elastic limit by the mold.Type: GrantFiled: May 24, 2011Date of Patent: September 25, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Young-Hoon Ro
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Patent number: 8258014Abstract: According to an embodiment of a method of manufacturing a power transistor module, the method includes mechanically fastening a first terminal, a second terminal and at least two different DC bias terminals to an electrically conductive flange; connecting the flange to a source of a power transistor device; electrically connecting the first terminal to a gate of the power transistor device; electrically connecting the second terminal to a drain of the power transistor device; mechanically fastening a bus bar to the flange which extends between and connects the DC bias terminals; and electrically connecting the bus bar to the drain via one or more RF grounded connections.Type: GrantFiled: June 30, 2011Date of Patent: September 4, 2012Assignee: Infineon Technologies AGInventors: Cynthia Blair, Donald Fowlkes
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Patent number: 8253226Abstract: An electronic part (100) that shields parts on a substrate (101) includes a plurality of chip parts (102) each having on a respective end portion a ground terminal (103A) and an electrode terminal (103B) that supplies a voltage source, and located at regular intervals on the substrate with the respective ground terminals aligned, the ground terminal and the electrode terminal being electrically connected to a ground terminal land (107A) and an electrode terminal land (107B) of the substrate respectively; and a shielding case (104) that shields the plurality of chip parts and includes an opening (105) through which a resin is to be provided for securing strength of the respective electrical connection points of the ground terminal land and the electrode terminal land of the substrate with the ground terminal and the electrode terminal of the chip parts; the opening being formed such that an edge (106) of the opening becomes parallel to the ground terminal of the respective chip parts, and such that upon beingType: GrantFiled: October 3, 2008Date of Patent: August 28, 2012Assignee: NEC CorporationInventor: Shinji Oguri
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Patent number: 8242384Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.Type: GrantFiled: September 30, 2009Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Moises Cases, Tae Hong Kim, Rohan U. Mandrekar, Nusrat I. Sherali
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Patent number: 8241957Abstract: A method for fabricating a negative thermal expanding system device includes coating a wafer with a thermally decomposable polymer, patterning the decomposable polymer into repeating disk patterns, releasing the decomposable polymer from the wafer and forming a sheet of repeating patterned disks, suspending the sheet into a first solution with seeding compounds for electroless decomposition, removing the sheet from the first solution, suspending the sheet into a second solution to electrolessly deposit a first layer material onto the sheet, removing the sheet from the second solution, suspending the sheet into a third solution to deposit a second layer of material having a lower TCE value than the first layer of material, separating the patterned disks from one another, and annealing thermally the patterned disks to decompose the decomposable polymer and creating a cavity in place of the decomposable polymer.Type: GrantFiled: October 18, 2010Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Gareth Geoffrey Hougham, S. Jay Chey, James Patrick Doyle, Xiao Hu Liu, Christopher V. Jahnes, Paul Alfred Lauro, Nancy C. LaBianca, Michael J. Rooks
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Patent number: 8207056Abstract: A method for manufacturing a semiconductor device includes forming an electrode; forming a projection projecting with respect to the electrode by melting a resin; and providing a conductive layer electrically connected to the electrode. The conductive layer is extended to an upper surface of the projection. Therefore, productivity of the semiconductor is improved.Type: GrantFiled: September 2, 2009Date of Patent: June 26, 2012Assignee: Seiko Epson CorporationInventor: Shuichi Tanaka
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Method and apparatus for directing molding compound flow and resulting semiconductor device packages
Patent number: 8207599Abstract: Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding compound, proximate a selected surface or surfaces of a semiconductor die or dice during encapsulation are disclosed. Flow diverting structures may be included in or associated with one or more portions of a lead frame, such as a paddle, tie bars, or lead fingers. Flow diverting structures may also be inserted into a mold in association with semiconductor dice carried on non-lead frame substrates, such as interposers and circuit boards, to preferentially impede, redirect or both impede and redirect the flow of molding compound flowing between and over the semiconductor dice.Type: GrantFiled: March 15, 2011Date of Patent: June 26, 2012Assignee: Micron Technology, Inc.Inventor: Stephen L. James -
Publication number: 20120146210Abstract: A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.Type: ApplicationFiled: December 8, 2010Publication date: June 14, 2012Applicant: TESSERA RESEARCH LLCInventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Piyush Savalia, Craig Mitchell
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Patent number: 8187922Abstract: A low cost flexible substrate is described which comprises a thin metal foil and a layer of solder mask. The metal foil layer is patterned to create tracks and lands for solder bonding and/or wirebonding and the layer of solder mask is patterned to create openings for solder bonding, wirebonding and/or for mounting the die. The substrate may be used as a package substrate to create a packaged die or may be used as a replacement for more expensive flexible printed circuit boards.Type: GrantFiled: September 11, 2009Date of Patent: May 29, 2012Assignee: Cambridge Silicon Radio Ltd.Inventors: Zaid Aboush, Peter John Robinson
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Patent number: 8179692Abstract: A board includes a board body; a first conductor provided at a first surface of the board body; and an electrically conductive connection terminal having a spring property. The connection terminal includes a first end part fixed to the first conductor; a second end part to be connected to a first object of connection to be placed opposite the first surface of the board body; and a projection part provided on the first end part so as to project toward the first conductor.Type: GrantFiled: June 28, 2010Date of Patent: May 15, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventor: Yoshihiro Ihara
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Patent number: 8169082Abstract: A semiconductor device includes: a sensor including a sensor structure on a first side of the sensor and a periphery element surrounding the sensor structure; and a cap covering the sensor structure and having a second side bonded to the first side of the sensor. The cap includes a first wiring layer on the second side of the cap. The first wiring layer steps over the periphery element. The sensor further includes a sensor side connection portion, and the cap further includes a cap side connection portion. The sensor side connection portion is bonded to the cap side connection portion. At least one of the sensor side connection portion and the cap side connection portion provides an eutectic alloy so that the sensor side connection portion and the cap side connection portion are bonded to each other.Type: GrantFiled: November 2, 2011Date of Patent: May 1, 2012Assignee: DENSO CORPORATIONInventors: Tetsuo Fujii, Akitoshi Yamanaka, Hisanori Yokura
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Patent number: 8133762Abstract: A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.Type: GrantFiled: March 17, 2009Date of Patent: March 13, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Reza A. Pagaila, Byung Tai Do, Shuangwu Huang
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Patent number: 8130512Abstract: A method of manufacturing an integrated circuit package system including: providing a circuit board having an interconnect thereon; mounting a first device offset on the circuit board; and applying a first encapsulant of a first thickness over the first device, the first encapsulant of a second thickness thinner than the first thickness over the remainder of the circuit board with the interconnect exposed, or a second encapsulant of a third thickness over a second device on an opposite surface of the circuit board and differently offset from the first device.Type: GrantFiled: November 18, 2008Date of Patent: March 6, 2012Assignee: STATS Chippac Ltd.Inventors: In Sang Yoon, SeongMin Lee, Sungmin Song
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Patent number: 8124456Abstract: Semiconductor device assemblies include elements such as electronic components and substrates secured together by a fastener that includes an elongated portion extending continuously through an aperture in two or more such elements. Computer systems include such semiconductor device assemblies. Fasteners for securing together such elements include an elongated portion, a first end piece, and a second end piece. Methods of securing together a plurality of semiconductor devices include inserting an elongated portion of a fastener through an aperture in a first semiconductor device and an aperture in at least one additional semiconductor device. Circuit boards include a plurality of apertures disposed in an array corresponding to an array of apertures in a semiconductor device assembly. Each aperture is sized and configured to receive a fastener for maintaining an assembled relationship between the semiconductor device assembly and the circuit board.Type: GrantFiled: January 8, 2010Date of Patent: February 28, 2012Assignee: Micron Technology, Inc.Inventor: Thomas H. Kinsley
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Patent number: 8115112Abstract: Chip-scale packages and assemblies thereof are disclosed. The chip-scale package includes a core member of a metal or alloy having a recess for at least partially receiving a die therein and includes at least one flange member partially folded over another portion of the core member. Conductive traces extend from one side of the package over the at least one flange member to an opposing side of the package. Systems including the chip-scale packages and assemblies are also disclosed.Type: GrantFiled: August 29, 2008Date of Patent: February 14, 2012Assignee: Micron Technology, Inc.Inventors: David J. Corisis, Chin Hui Chong, Choon Kuan Lee